interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Print out debug value after the assignment is made. 

Change-Id: I6ba1064c09f48eba97d84ea9db5ff44d82b9d004
This commit is contained in:
Tim Newsome 2023-02-08 11:02:51 -08:00
parent 91552c7999
commit 344e8bd263
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/target/riscv/riscv-013.c
View File

@ -1732,8 +1732,8 @@ static int examine(struct target *target)
LOG_TARGET_WARNING(target, "Couldn't read vlenb; vector register access won't work.");
r->vlenb = 0;
} else {
LOG_TARGET_INFO(target, "Vector support with vlenb=%d", r->vlenb);
r->vlenb = vlenb;
LOG_TARGET_INFO(target, "Vector support with vlenb=%d", r->vlenb);
}
/* Now init registers based on what we discovered. */