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__archive__

add_macos_build

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deinit

dmi_read

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examine_command

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global

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latest

openocd64-41b9c69e92d9660cb2eff508f3bc8218a3b3e461

openocd64-8b80fe1

openocd64-ad4c3e1

openocd64-d486b21

v20170608

v20170612

v20170621

v20170818

v20171231

v2018.12.0

v20180629

v20180928

v20181030

Mono Color

• 12ac628c28
  Merge fb750ab14b into 8f59570468 Ryan QIAN 2025-02-01 16:18:14 +0900
• f7ec8beecf
  Merge 65648f9c8b into 8f59570468 Samuel Obuch 2025-02-01 01:59:45 +0800
• dbc8d4552b
  Merge c65ef19e04 into 8f59570468 fk-sc 2025-02-01 01:59:41 +0800
• bb935f5355
  Merge dc9f9be528 into 8f59570468 Anatoly Parshintsev 2025-01-31 13:13:38 +0100
• de21cc24cb
  Merge 827d2af88a into 8f59570468 fk-sc 2025-01-31 15:10:37 +0300
• 8f59570468
  Merge pull request #1217 from sobuch/not_cachable_mcause_mstatus riscv Evgeniy Naydanov 2025-01-31 15:10:33 +0300
• 9d431c3ec2
  Merge pull request #1207 from en-sc/en-sc/fix-011-init-regs Evgeniy Naydanov 2025-01-31 15:09:46 +0300
• 3b6d737cd9
  Merge 42259dc9fb into 495f144a1d Evgeniy Naydanov 2025-01-31 15:08:34 +0300
• 495f144a1d
  Merge pull request #1215 from en-sc/en-sc/from_upstream Evgeniy Naydanov 2025-01-31 15:07:01 +0300
• dc9f9be528 fix expose_csr for CSR from lower address space Parshintsev Anatoly 2025-01-30 20:22:03 +0300
• c65ef19e04 target/riscv: merged read/write functions to one access function Farid Khaydari 2024-11-26 20:30:09 +0300
• 827d2af88a target/riscv: refactored memory access result codes Farid Khaydari 2025-01-28 15:08:25 +0300
• d8b3aaa9cd
  Merge a54d86f3d0 into 5de7310881 Evgeniy Naydanov 2025-01-29 18:48:44 +0300
• f3a3d5e37b
  Merge 0affedb03f into 5de7310881 lzbro 2025-01-29 18:48:26 +0300
• 5de7310881
  Merge pull request #1190 from lz-bro/enable-hardware-translation latest Evgeniy Naydanov 2025-01-29 18:47:41 +0300
• 550df1603d
  Merge pull request #1192 from cetygamer/patch-1 Evgeniy Naydanov 2025-01-29 18:43:32 +0300
• 65648f9c8b target/riscv: support deprecated user interrupt registers Samuel Obuch 2025-01-29 14:10:09 +0100
• 5197bf59e2
  Merge 2ff738dfba into e870c5f2de Tomas Vanek 2025-01-29 00:01:25 +0000
• 363603d228
  Merge 006680f7b5 into e870c5f2de Anatoly Parshintsev 2025-01-29 00:00:08 +0000
• 309c25f5e2 Merge up to a510d51a78 from upstream Evgeniy Naydanov 2025-01-27 14:04:41 +0300
• 94d739ac9a target/riscv: dont set mcause and mstatus as cachable Samuel Obuch 2025-01-27 17:52:08 +0100
• b2e08ed496
  Merge 8cbd420c94 into e870c5f2de Evgeniy Naydanov 2025-01-27 15:14:12 +0100
• a5ed2b7445
  Merge cfd4dc2b0a into e870c5f2de Rob Bradford 2025-01-27 15:11:39 +0100
• e870c5f2de
  Merge pull request #1206 from JanMatCodasip/jm-codasip/remove-asm-h Evgeniy Naydanov 2025-01-27 15:56:12 +0300
• 57b58b7832
  Merge pull request #1202 from JanMatCodasip/fix-datatypes-around-batch Evgeniy Naydanov 2025-01-27 15:55:21 +0300
• 77b85757c5
  Merge pull request #1200 from JanMatCodasip/jm-codasip/semihosting-3-warn-if-encountered-but-disabled Evgeniy Naydanov 2025-01-27 15:54:57 +0300
• 1d623819e9
  Merge pull request #1193 from en-sc/en-sc/not-busy Evgeniy Naydanov 2025-01-27 15:54:38 +0300
• fb750ab14b target/riscv: make sure target is halted when reset_halt is set Ryan QIAN 2025-01-27 11:38:15 +0800
• 058891a62a
  Merge pull request #1210 from en-sc/en-sc/from_upstream Evgeniy Naydanov 2025-01-27 14:04:18 +0300
• dd69b78fed
  Merge pull request #1204 from sobuch/esp-riscv-cfg-fix Evgeniy Naydanov 2025-01-27 13:59:09 +0300
• a510d51a78 bootstrap: Do not set up Git submodules by default Marc Schink 2024-06-26 15:50:45 +0200
• 77c904fd13 Deprecate jimtcl Git submodule Marc Schink 2024-07-02 17:12:46 +0200
• fceccde0b3 helper/log: Fix build using _DEBUG_FREE_SPACE_ Antonio Borneo 2024-02-19 20:11:07 -0600
• 8038e2f754 configure: allow --enable-malloc-logging only with glibc Antonio Borneo 2024-11-17 22:46:15 +0100
• ac18b8cd6a configure: make more robust the check for elf 64 Antonio Borneo 2024-11-17 21:35:45 +0100
• 345473f3ce helper/options: handle errors in `-l` Evgeniy Naydanov 2024-12-17 18:13:00 +0300
• 778d2dc4bb helper/options: drop redundant argument checks Evgeniy Naydanov 2025-01-17 18:03:40 +0300
• 0b97973bfb vdebug: Fix socket comparison warning on Windows Marek Vrbka 2025-01-13 10:28:15 +0100
• 77f9da7626 flash/nor/kinetis: fix assertion during flash write Tomas Vanek 2025-01-17 18:02:50 +0100
• 3099547069 OpenOCD: fix code indentation Antonio Borneo 2024-09-16 13:45:19 +0200
• 8e89a8af63 target: cortex_m: add support of ARMv8.1-M register 'vpr' Antonio Borneo 2024-12-30 12:14:24 +0100
• 41f7d18161 target: armv7m: add support of per register data_type Antonio Borneo 2024-12-30 12:10:28 +0100
• 8513d6edcc target/riscv: set VLENB/MTOPI/MTOPEI existence on 0.11 targets Evgeniy Naydanov 2025-01-13 16:29:56 +0300
• 05d377af75 target/riscv: move the dcsr modification out of program buffer liangzhen 2024-12-24 11:22:59 +0800
• 4ff476ca47 Makefile.am: fixed missing includes for make dist targets Alexander Rumyantsev 2024-12-25 15:42:07 +0300
• 0affedb03f target/riscv: Fix SMP group is in inconsistent state liangzhen 2024-11-20 19:59:55 +0800
• 83e0293f7b Add Linux SPI device SWD adapter support Richard Pasek 2024-12-11 00:43:57 -0500
• 182092a364 Merge up to 26f2df80c3 from upstream Evgeniy Naydanov 2025-01-22 17:09:42 +0300
• b7d9ab5d1e RISC-V Semihosting 3 of 3: Warn if encountered but disabled Jan Matyas 2025-01-07 12:06:49 +0100
• 88fe56828a
  Merge pull request #1199 from JanMatCodasip/jm-codasip/semihosting-2-refactor-magic-seq-detection Evgeniy Naydanov 2025-01-22 11:23:11 +0300
• a450a7d496 Fix data types around batch.{c,h} Jan Matyas 2025-01-08 22:45:56 +0100
• c1dfb0d50e Remove target/riscv/asm.h Jan Matyas 2025-01-16 16:05:44 +0100
• 8c0a1cde78 RISC-V Semihosting 2 of 3: Refactor magic sequence detection Jan Matyas 2025-01-07 09:16:10 +0100
• 42259dc9fb target/riscv: drop `mtopi_readable/mtopei_readable` `riscv_info` fields Evgeniy Naydanov 2025-01-13 17:33:38 +0300
• 8cbd420c94 target/riscv: pass `jtag_tap` instead of `target` Evgeniy Naydanov 2024-12-24 21:00:55 +0300
• 22108977c0
  Merge pull request #1168 from en-sc/en-sc/ebreak Evgeniy Naydanov 2025-01-17 14:29:04 +0300
• e7b7eefe89 target/riscv: set VLENB/MTOPI/MTOPEI existence on 0.11 targets Evgeniy Naydanov 2025-01-13 16:29:56 +0300
• b9d9d1a6a2 target/riscv: new `ebreak` controls Evgeniy Naydanov 2024-10-22 12:43:04 +0300
• eb9ba216e1
  Merge pull request #1198 from JanMatCodasip/jm-codasip/semihosting-1-remove-dead-code Evgeniy Naydanov 2025-01-13 22:49:24 +0300
• fb16cb5e67 tcl: fix esp riscv configs Samuel Obuch 2025-01-10 16:53:40 +0100
• 26f2df80c3 helper: list: rename macro clashing with sys/queue.h Antonio Borneo 2024-12-31 14:47:02 +0100
• 0ed03df6e9 amend angie build definitions to fix make dist R. Diez 2024-11-28 21:47:34 +0100
• 8b5ea720da make bitbang_interface const R. Diez 2024-11-03 12:06:05 +0100
• d4b3b4ea82 target: free private_config if target initialisation fails Tomas Vanek 2024-12-10 13:48:53 +0100
• cf115c1e2b drivers/cmsis_dap_usb_bulk: allow waiting for bulk write Tomas Vanek 2024-12-10 08:53:49 +0100
• 23796efa38 drivers/cmsis_dap: use blocking flag instead of wait timeout Tomas Vanek 2024-12-10 08:26:48 +0100
• ecb2ad4a8a RISC-V Semihosting 1 of 3: Remove dead code Jan Matyas 2025-01-07 08:34:16 +0100
• 250ab1008b flash/stm32l4x: add STM32C071xx support David (Pololu) 2024-12-18 13:49:00 -0800
• 5233312ea5 configure: fix dependency of bitbang from dummy adapter Antonio Borneo 2024-12-31 10:38:28 +0100
• 4f2744d0fe target/arc: Use LOG_TARGET_xxx() Marc Schink 2024-10-23 12:56:37 +0200
• a75feb0bfd target/armv7m: Use LOG_TARGET_xxx() Marc Schink 2024-10-22 18:22:12 +0200
• 78bc6f34d4 target/esirisc: Use LOG_TARGET_xxx() Marc Schink 2024-10-22 18:24:11 +0200
• 4193322315 target/mem_ap: Use LOG_TARGET_xxx() Marc Schink 2024-10-22 18:23:14 +0200
• e4ad10e0a1 helper/log: Add LOG_TARGET_USER() Marc Schink 2024-10-22 16:36:15 +0200
• 5284a5f3ec tcl/interface: Find proper alias for RP1 on Raspberry Pi 5 Tomas Vanek 2024-10-25 17:17:22 +0200
• 15d90dd21c tcl/target: Add config for STM32U0x Marc Schink 2024-12-13 07:34:03 +0000
• 66faa420a4 flash/nor/stm32l4x: Add support for STM32U0 series Marc Schink 2024-12-13 07:14:02 +0000
• 83dc8a6446 target/riscv: clear `abstract_cmd_maybe_busy` after commands Evgeniy Naydanov 2024-12-25 13:11:33 +0300
• 7d5a0b6a27 tcl/board: Add nRF54L15-DK config file Marc Schink 2024-11-29 20:39:21 +0000
• 4d1b3cbafc tcl/target: Add support for Nordic nRF54L series Marc Schink 2024-11-29 20:29:18 +0000
• 1f2db5d59a rtos/rtos: Remove 'ERROR: ' prefix in error log Marc Schink 2024-11-30 15:35:39 +0100
• 3be1bee753 target/mips: Remove 'ERROR: ' prefix in error log Marc Schink 2024-11-30 15:34:20 +0100
• 9cd0b37112 target/xtensa: Remove 'ERROR: ' prefix in error log Marc Schink 2024-11-30 15:32:09 +0100
• 7f9d25d58a configure.ac: switch from $host to $host_os R. Diez 2024-11-29 21:09:50 +0100
• bb2fc63357 configure.ac: enable the Dummy adapter by default R. Diez 2024-11-29 21:24:23 +0100
• cd9e64a25a rtos: mqx: minor rework to avoid a cast Antonio Borneo 2024-11-27 09:25:01 +0100
• dca76cd5da rtos: mqx: replace malloc+strcpy with strdup Paul Fertser 2024-11-26 22:55:55 +0200
• 42f70a3b95 target: aarch64: fix out-of-bound access to array Antonio Borneo 2024-11-22 18:06:40 +0100
• 1710954977 doc/manual: Add section about logging Marc Schink 2024-10-23 15:42:16 +0200
• cc02bd752c rtt server: fix for dropped data when target has no space fanoush 2024-09-02 13:49:19 +0200
• cb3b8afe47 jimtcl: Fix command not found Pete Moore 2024-12-16 14:02:14 +0100
• d60e1f6693 flash/nor/sfdp: Fix broken DEBUG log line on macOS Pete Moore 2024-12-16 16:55:06 +0100
• a54d86f3d0 target/riscv: access registers via `reg->type` Evgeniy Naydanov 2024-09-10 14:37:23 +0300
• 1c6b7fa2c9 target: Fix force-reading of registers and add flush capability Marek Vrbka 2024-01-12 14:38:56 +0100
• f82c5a7c04
  Merge pull request #1186 from en-sc/en-sc/from_upstream Evgeniy Naydanov 2024-12-20 12:08:03 +0300
• 4b9fb1972f Merge up to 133dd9d669 from upstream Evgeniy Naydanov 2024-12-18 12:41:19 +0300
• cf9963ad81
  Merge pull request #1181 from en-sc/en-sc/reg-invalidate Evgeniy Naydanov 2024-12-11 16:40:20 +0300
• 8dfc806fe3
  Merge pull request #1183 from fk-sc/fk-sc/ternary-operator Evgeniy Naydanov 2024-12-11 16:39:54 +0300
• de20c2ad5f target/riscv: clean-up register invalidation Evgeniy Naydanov 2024-12-05 16:27:26 +0300
• d5c2604418 target/riscv: replaced repeating ternary operator with variable Farid Khaydari 2024-12-10 13:40:01 +0300