riscv-openocd

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FE_402_fix

archive

add_macos_build

autoconf

bscan_optimization

bscan_tunnel

buf_sget

build32

busy

compliance_dev

debug-log-reg-failure

deinit

dmi_read

dmstatus_version

dsp5680_build

eclipse_memory_read

eclipse_multicore_fix

examine_command

examine_unavailable_harts

examine_unavailable_harts_backup

examine_unavailable_harts_rebase

examine_unavailable_harts_squash

fence_i_fix_for_release

fix-halt-reason-after-singlestep

fix_macbuild

gd32vf103

gdb_next_port

gitignore-build

global

halt_examine

haltreq

hypervisor_translate

jlink

log_output

macbuild

macro

manual_hwbp

master

mem64

mpsse_flush

multicore

new_bscan_approach

newprogram

nohartstatus

old_fixes_and_eclipse_memory_read

old_triggers

print_port

race

rbb_cleanup

regcache

regression_test_janmat_experim

release

remove-slot_t-from-riscv-013

reset_test

reverse-resume-order

riscv

riscv-batch-cleanup

riscv-compliance

riscv-compliance-dev

s2_increment

sba_tests

set_group

static

travis-nop

update_defines

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vector2

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latest

openocd64-41b9c69e92d9660cb2eff508f3bc8218a3b3e461

openocd64-8b80fe1

openocd64-ad4c3e1

openocd64-d486b21

v20170608

v20170612

v20170621

v20170818

v20171231

v2018.12.0

v20180629

v20180928

v20181030

71e5baf0c8

Merge 5046d22bdd into 1bf7efb2d5 fk-sc 2024-11-22 13:14:37 +0000
5046d22bdd target/riscv: fix is_mem_access_XXXXed function return in case of assertion Farid Khaydari 2024-11-20 18:12:36 +0300
825538b6fd

Merge 6fafca021c into 1bf7efb2d5 fk-sc 2024-11-22 16:07:23 +0300
6fafca021c target/riscv: use buf_get_uXX instead of manual bit shift Farid Khaydari 2024-11-22 16:03:58 +0300
28e505893e

Merge 53b5b0ada8 into 1bf7efb2d5 Evgeniy Naydanov 2024-11-22 15:59:05 +0300
53b5b0ada8 target/riscv: new `ebreak` controls Evgeniy Naydanov 2024-10-22 12:43:04 +0300
411384c4a0

Merge 2ff738dfba into 1bf7efb2d5 Tomas Vanek 2024-11-22 10:47:16 +0800
4a6a263ad1

Merge 006680f7b5 into 1bf7efb2d5 Anatoly Parshintsev 2024-11-22 09:23:27 +0800
b5fe6fe725

Merge bcf9bab90c into 1bf7efb2d5 fk-sc 2024-11-21 12:53:49 +0000
bcf9bab90c target/riscv: pass memory access info in struct, move write_memory pointer Farid Khaydari 2024-10-05 14:19:15 +0300
43500d83e0

Merge ba8c1eef5a into 1bf7efb2d5 Anatoly Parshintsev 2024-11-21 12:38:31 +0300
51eff3540f

Merge 8b7013028c into 1bf7efb2d5 fk-sc 2024-11-21 12:38:02 +0300
db29baf89b

Merge 21d836aaac into 1bf7efb2d5 lzbro 2024-11-21 12:38:02 +0300
1bf7efb2d5

Merge pull request #1144 from sunnyzhu-learning/resume-before-step-develop riscv latest Evgeniy Naydanov 2024-11-21 12:37:59 +0300
8b7013028c target/riscv: decrease modify_privilege function nesting level Farid Khaydari 2024-10-07 14:34:39 +0300
21d836aaac target/riscv: Ensure to handle all triggered a halt events liangzhen 2024-11-20 19:59:55 +0800
ba8c1eef5a target/riscv: allow hexadecimal values to expose_csr-like commands Parshintsev Anatoly 2024-11-10 00:03:57 +0300
b4e3e28852

Merge 5dae5efe6e into f51900b4a2 Jan Matyas 2024-11-18 19:24:53 +0800
f51900b4a2

Merge pull request #1165 from aap-sc/aap-sc/resume_debug_errors Evgeniy Naydanov 2024-11-18 13:17:25 +0300
463d1b0866

Merge pull request #1157 from zqb-all/support-disable-auto-fence Evgeniy Naydanov 2024-11-18 13:16:54 +0300
c53f9319c8

Merge pull request #1163 from en-sc/en-sc/from_upstream Evgeniy Naydanov 2024-11-18 13:16:18 +0300
a2f5da3289

Merge pull request #1161 from en-sc/en-sc/deassert-reset Evgeniy Naydanov 2024-11-14 13:23:42 +0300
faffae0493 target/riscv: detailed error messages for cases when resume operation fails Parshintsev Anatoly 2024-11-13 19:53:58 +0300
f7ea8245e6

Merge pull request #1160 from zqb-all/reduce-log Evgeniy Naydanov 2024-11-12 17:45:57 +0300
cabb6000df Merge up to fd62626dff from upstream Evgeniy Naydanov 2024-11-12 17:25:33 +0300
fd62626dff target/breakpoints: fix types in `watchpoint_add_internal()` Evgeniy Naydanov 2024-09-16 18:01:17 +0300
215ecdaedf target/riscv:Perform single step before resume if necessary zhusonghe 2024-10-09 18:36:42 +0800
b68d23da3c tcl/target/bl702: implement full software reset Marek Kraus 2024-10-23 16:27:33 +0200
bcebc84882 contrib: convert 'unsigned' to 'unsigned int' Mark Zhuang 2024-10-26 10:30:18 +0800
784687d781 target/riscv: avoid updating `target` if `ackhavereset` fails Evgeniy Naydanov 2024-11-08 15:44:46 +0300
e024f112e3 [NFC] target/riscv: remove LOG_ERROR when COMMAND check ARGC fail Mark Zhuang 2024-11-05 23:11:26 +0800
340e38a9ed target/riscv: support disable auto fence Mark Zhuang 2024-10-29 17:00:05 +0800
40d58ce529 tcl/target/renesas_rz_g2: Rename to renesas_rz and add RZ/V2L-G3S MicBiso 2024-04-10 12:38:09 +0200
3b261fb155 adapter/parport: Coding style changes Marc Schink 2024-08-30 11:22:17 +0200
337db329c9 adapter/bitbang: Use 'bool' data type for blink() Marc Schink 2024-08-30 11:06:13 +0200
f4d81cd4d4 tcl/interface: Restructure parport config files Marc Schink 2024-08-30 10:47:55 +0200
99f60d5e59 jtag: convert 'unsigned' to 'unsigned int' Mark Zhuang 2024-10-26 10:15:00 +0800
b95633b30c flash: convert 'unsigned' to 'unsigned int' Mark Zhuang 2024-10-26 11:09:16 +0800
114ad468ca server: convert 'unsigned' to 'unsigned int' Mark Zhuang 2024-10-26 10:42:03 +0800
134e56338d target: riscv: convert 'unsigned' to 'unsigned int' Mark Zhuang 2024-10-25 22:15:29 +0800
34ec5536c0 stlink: deprecate HLA support Antonio Borneo 2024-10-12 11:48:05 +0200
3ce0962f2c target: cortex_m: fix polling for target kept under reset Antonio Borneo 2024-07-15 11:56:36 +0200
7214c8be46 configure: show adapter Xilinx XVC/PCIe in the configuration summary R. Diez 2024-06-01 21:20:31 +0200
f9a1292716

Merge pull request #1154 from en-sc/en-sc/dcsr-ebreak-halt-on-reset Evgeniy Naydanov 2024-10-30 17:52:56 +0300
e3a47cae3e

Merge pull request #1156 from zqb-all/max-macro Evgeniy Naydanov 2024-10-30 17:51:35 +0300
b7708c84e6 [NFC] target/riscv: simplify code with MAX macros Mark Zhuang 2024-10-28 22:48:25 +0800
9ff272e34b

Merge pull request #1149 from zqb-all/read-write-cross-page Evgeniy Naydanov 2024-10-28 14:40:13 +0300
3fe20e7aa4 target/riscv: avoid unnecessary `dcsr.ebreak*` update on reset Evgeniy Naydanov 2024-10-22 14:06:45 +0300
92d7a5798d [NFC] target/riscv: refactor riscv_read_memory,riscv_write_memory Mark Zhuang 2024-10-15 20:13:02 +0800
4a1bd80842 target/riscv: fix cross-page misaligned access when mmu not enabled Mark Zhuang 2024-10-14 00:18:11 +0800
593b377073 target/riscv: fix read/write virtual memory across page boundaries Mark Zhuang 2024-10-11 16:57:48 +0800
7b4ad6f173

Merge pull request #1152 from fk-sc/translation-drivers Evgeniy Naydanov 2024-10-24 15:06:27 +0300
6a27d9fbc0 target/riscv: added translation drivers Farid Khaydari 2024-10-23 12:36:29 +0300
d09ff47644 gdb_server: Improve const correctness Jan Matyas 2024-09-30 14:55:58 +0200
114ca19f64 gitignore: Start ignoring ".vscode" Jan Matyas 2024-10-03 09:59:24 +0200
21a211d547 arm_adi_v5: Added Cortex-A55 debug unit identifier Florian Fainelli 2024-08-06 15:28:15 -0700
fec3b22421 target: riscv: remove non-trivial 'unsigned' cast Antonio Borneo 2024-09-08 21:47:31 +0200
957eb741a0 target: riscv: convert 'unsigned' to 'unsigned int' Antonio Borneo 2024-09-08 21:23:28 +0200
bcf63ac562 checkpatch: check SPDX in Makefile Antonio Borneo 2024-10-08 00:37:48 +0200
bc68bd71a3

Merge pull request #1146 from en-sc/en-sc/select-dmi-bypass Evgeniy Naydanov 2024-10-18 12:37:31 +0300
417ff401f8

Merge pull request #1150 from borneoa/riscv Evgeniy Naydanov 2024-10-17 11:10:42 +0300
f3ed0ab608 target/riscv: check other TAPs in `select_dmi()` Evgeniy Naydanov 2024-10-10 14:18:59 +0300
006680f7b5 enable additional platforms in CI Parshintsev Anatoly 2024-08-30 23:46:55 +0300
89fb9211ec target: riscv: convert 'unsigned' to 'unsigned int' Antonio Borneo 2024-10-12 17:01:36 +0200
e2388acdb5 [target/riscv]read each word individually in memory progbuf likun2 2024-10-11 19:44:03 +0800
a4020f1a02

Merge pull request #1142 from en-sc/en-sc/from_upstream Evgeniy Naydanov 2024-10-08 14:17:57 +0300
edf2c82cf6 helper/align.h: Fix macro IS_PWR_OF_2 Jan Matyas 2024-09-27 09:49:52 +0200
30c3d077f2 jimtcl: update to version 0.83 Antonio Borneo 2024-09-27 22:40:06 +0200
73390332d2 openocd: fix build with jimtcl 0.83 Antonio Borneo 2024-09-27 22:36:52 +0200
116e9553d1 openocd: build: allow more socket connections on Windows Antonio Borneo 2024-09-22 18:32:21 +0200
595bb965b7 jtag: bcm2835gpio: fix macro definition Antonio Borneo 2024-09-16 10:58:37 +0200
8c23e6c175 target: arm: drop casts commented-out Antonio Borneo 2024-09-16 13:49:04 +0200
3ccf68cd0a OpenOCD: drop comparison with true/false Antonio Borneo 2024-09-16 11:55:20 +0200
66006d83b9 target: drop comparison to NULL Antonio Borneo 2024-09-16 11:37:05 +0200
39197cdb4e jtag: stlink_usb: drop comparison to NULL Antonio Borneo 2024-09-16 11:36:03 +0200
4214fca447 OpenOCD: fix code alignment Antonio Borneo 2024-09-16 11:31:37 +0200
537793bb24 target: mem_ap: drop return from void function Antonio Borneo 2024-09-16 10:45:17 +0200
39f024900e flash: stm32l4x: fix open brace style Antonio Borneo 2024-09-16 10:42:47 +0200
436e6f1770 openocd: convert 'unsigned' to 'unsigned int' Antonio Borneo 2024-09-08 21:22:40 +0200
a64dc23bf1 jtag: convert 'unsigned' to 'unsigned int' Antonio Borneo 2024-09-08 21:21:35 +0200
e72733d590 target: convert 'unsigned' to 'unsigned int' Antonio Borneo 2024-09-08 21:20:48 +0200
2ad48b78d4 flash: convert 'unsigned' to 'unsigned int' Antonio Borneo 2024-09-08 21:15:53 +0200
50586c9a06 target: use 'unsigned int' for smp group Antonio Borneo 2024-09-08 21:44:32 +0200
bf1cf4afbb openocd: fix conversion string for stdint values Antonio Borneo 2024-09-08 23:11:45 +0200
8750beeb44 tcl: update to new syntax of telnet command Antonio Borneo 2024-09-21 11:11:36 +0200
00ee9b09d9 target/mips32: add dsp access support for gdb Walter Ji 2024-02-22 17:06:53 +0800
ab31562131 jep106: update to revision JEP106BK Sep 2024 Antonio Borneo 2024-09-21 10:07:52 +0200
bd93b83f1b jtag: update constant names to follow code style guidelines Parshintsev Anatoly 2024-09-10 06:53:17 +0300
017e61feb4 HACKING: add info on ignoring check-patch checks Antonio Borneo 2023-04-02 20:47:41 +0200
8edfdb02ed rtos: chibios: fix version display Antonio Borneo 2024-09-01 14:45:36 +0200
0a2c146440

Merge pull request #1140 from TommyMurphyTM1234/riscv Evgeniy Naydanov 2024-10-04 16:39:32 +0300
e4f5489723

Merge pull request #1127 from sunnyzhu-learning/Songhe-develop Evgeniy Naydanov 2024-10-04 11:12:02 +0300
ec00140a10 Merge up to 1173473f66 from upstream Evgeniy Naydanov 2024-10-03 21:44:29 +0300
5dae5efe6e target/riscv: Consistent data type for trigger indexes Jan Matyas 2024-10-03 13:26:38 +0200
16fa57da41 Fix riscv013_invalidate_cached_progbuf() off by one error Tommy Murphy 2024-10-02 21:08:24 +0100
1173473f66 flash/nor/atsame5: add PIC32CX-SG device IDs Matt Trescott 2024-07-10 14:46:28 -0400
1cd56854b0

Merge e6d4761146 into 841b61adf3 Anatoly Parshintsev 2024-09-30 10:50:39 +0200
841b61adf3

Merge pull request #1134 from fk-sc/early-exit-support Evgeniy Naydanov 2024-09-30 10:49:35 +0300
27220e4c85

Merge pull request #1136 from en-sc/en-sc/batch-logging Evgeniy Naydanov 2024-09-27 17:50:55 +0300
173086a651 target/riscv: early exit support for memory access operations Farid Khaydari 2024-09-03 15:27:36 +0300