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target/riscv: dont set mcause and mstatus as cachable 

With CLIC extension (smclic), mcause and mstatus CSRs
share mirrored fields for mpp and mpie. Therefore, neither
can be assumed cachable.

Signed-off-by: Samuel Obuch <samuel.obuch@espressif.com>
This commit is contained in:
Samuel Obuch 2025-01-27 17:52:08 +01:00
parent e870c5f2de
commit 94d739ac9a
1 changed files with 0 additions and 2 deletions
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src/target/riscv/riscv_reg_impl.h
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@ -204,9 +204,7 @@ static inline bool riscv_reg_impl_gdb_regno_cacheable(enum gdb_regno regno,
case GDB_REGNO_MISA:
case GDB_REGNO_DCSR:
case GDB_REGNO_DSCRATCH0:
case GDB_REGNO_MSTATUS:
case GDB_REGNO_MEPC:
case GDB_REGNO_MCAUSE:
case GDB_REGNO_SATP:
/*
* WARL registers might not contain the value we just wrote, but