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Merge up to a168c63412 from upstream 

There was a bunch of conflicts due to commit
297844cf46 ("target: Use 'bool' data type
in target_{step,resume}")

Resolved by updating the corresponding data types throughout the
codebase.

Change-Id: I9574deeda754b2843b69b4afe80b293d4b357ddd
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This commit is contained in:
Evgeniy Naydanov 2025-03-05 14:23:01 +03:00
parent fa7e2351c8 a168c63412
commit 8c82210c43
62 changed files with 661 additions and 393 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
configure.ac
View File

@ -137,16 +137,19 @@ m4_define([USB1_ADAPTERS],
[[ft232r], [Bitbang mode of FT232R based devices], [FT232R]],
[[vsllink], [Versaloon-Link JTAG Programmer], [VSLLINK]],
[[xds110], [TI XDS110 Debug Probe], [XDS110]],
[[cmsis_dap_v2], [CMSIS-DAP v2 Compliant Debugger], [CMSIS_DAP_USB]],
[[osbdm], [OSBDM (JTAG only) Programmer], [OSBDM]],
[[opendous], [eStick/opendous JTAG Programmer], [OPENDOUS]],
[[armjtagew], [Olimex ARM-JTAG-EW Programmer], [ARMJTAGEW]],
[[rlink], [Raisonance RLink JTAG Programmer], [RLINK]],
[[usbprog], [USBProg JTAG Programmer], [USBPROG]],
[[esp_usb_jtag], [Espressif JTAG Programmer], [ESP_USB_JTAG]]])
[[esp_usb_jtag], [Espressif JTAG Programmer], [ESP_USB_JTAG]],
[[cmsis_dap_v2], [CMSIS-DAP v2 compliant dongle (USB bulk)], [CMSIS_DAP_USB]]])
# Please keep cmsis_dap_v2 the last in USB1_ADAPTERS
# and cmsis_dap the first in HIDAPI_ADAPTERS
m4_define([HIDAPI_ADAPTERS],
[[[cmsis_dap], [CMSIS-DAP Compliant Debugger], [CMSIS_DAP_HID]],
[[[cmsis_dap], [CMSIS-DAP v1 compliant dongle (HID)], [CMSIS_DAP_HID]],
[[nulink], [Nu-Link Programmer], [HLADAPTER_NULINK]]])
m4_define([HIDAPI_USB1_ADAPTERS],
@ -879,7 +882,7 @@ AS_IF([test "x$use_internal_jimtcl" = "xyes"], [
echo
echo
echo OpenOCD configuration summary
echo --------------------------------------------------
echo ---------------------------------------------------
m4_foreach([adapter], [USB1_ADAPTERS,
HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS,
LIBFTDI_USB1_ADAPTERS,
@ -890,7 +893,7 @@ m4_foreach([adapter], [USB1_ADAPTERS,
DUMMY_ADAPTER,
OPTIONAL_LIBRARIES,
COVERAGE],
[s=m4_format(["%-40s"], ADAPTER_DESC([adapter]))
[s=m4_format(["%-41s"], ADAPTER_DESC([adapter]))
AS_CASE([$ADAPTER_VAR([adapter])],
[auto], [
echo "$s"yes '(auto)'

5
src/flash/nor/rsl10.c
View File

@ -155,11 +155,6 @@ static int rsl10_get_probed_chip_if_halted(struct flash_bank *bank, struct rsl10
static int rsl10_protect_check(struct flash_bank *bank)
{
struct rsl10_bank *nbank = bank->driver_priv;
struct rsl10_info *chip = nbank->chip;
assert(chip);
uint32_t status;
int retval = target_read_u32(bank->target, RSL10_FLASH_REG_IF_STATUS, &status);

49
src/helper/jep106.inc
View File

@ -2,18 +2,18 @@
/*
* The manufacturer's standard identification code list appears in JEP106.
* Copyright (c) 2024 JEDEC. All rights reserved.
* Copyright (c) 2025 JEDEC. All rights reserved.
*
* JEP106 is regularly updated. For the current manufacturer's standard
* identification code list, please visit the JEDEC website at www.jedec.org .
*/
/* This file is aligned to revision JEP106BK September 2024. */
/* This file is aligned to revision JEP106BL February 2025. */
[0][0x01 - 1] = "AMD",
[0][0x02 - 1] = "AMI",
[0][0x03 - 1] = "Fairchild",
[0][0x04 - 1] = "Fujitsu",
[0][0x04 - 1] = "RAMXEED Limited",
[0][0x05 - 1] = "GTE",
[0][0x06 - 1] = "Harris",
[0][0x07 - 1] = "Hitachi",
@ -1373,7 +1373,7 @@
[10][0x65 - 1] = "Esperanto Technologies",
[10][0x66 - 1] = "JinSheng Electronic (Shenzhen) Co Ltd",
[10][0x67 - 1] = "Shenzhen Shi Bolunshuai Technology",
[10][0x68 - 1] = "Shanghai Rui Xuan Information Tech",
[10][0x68 - 1] = "Shanghai Ruixuan Information Tech",
[10][0x69 - 1] = "Fraunhofer IIS",
[10][0x6a - 1] = "Kandou Bus SA",
[10][0x6b - 1] = "Acer",
@ -1745,7 +1745,7 @@
[13][0x5f - 1] = "Guangdong OPPO Mobile Telecommunication",
[13][0x60 - 1] = "Akeana",
[13][0x61 - 1] = "Lyczar",
[13][0x62 - 1] = "Shenzhen Qiji Technology Co Ltd",
[13][0x62 - 1] = "QJTEK",
[13][0x63 - 1] = "Shenzhen Shangzhaoyuan Technology",
[13][0x64 - 1] = "Han Stor",
[13][0x65 - 1] = "China Micro Semicon Co., Ltd.",
@ -1893,7 +1893,7 @@
[14][0x75 - 1] = "HOGE Technology Co Ltd",
[14][0x76 - 1] = "United Micro Technology (Shenzhen) Co",
[14][0x77 - 1] = "Fabric of Truth Inc",
[14][0x78 - 1] = "Epitech",
[14][0x78 - 1] = "Elpitech",
[14][0x79 - 1] = "Elitestek",
[14][0x7a - 1] = "Cornelis Networks Inc",
[14][0x7b - 1] = "WingSemi Technologies Co Ltd",
@ -1916,7 +1916,7 @@
[15][0x0e - 1] = "Shenzhen Ranshuo Technology Co Limited",
[15][0x0f - 1] = "ScaleFlux",
[15][0x10 - 1] = "XC Memory",
[15][0x11 - 1] = "Guangzhou Beimu Technology Co., Ltd",
[15][0x11 - 1] = "Guangzhou Beimu Technology Co Ltd",
[15][0x12 - 1] = "Rays Semiconductor Nanjing Co Ltd",
[15][0x13 - 1] = "Milli-Centi Intelligence Technology Jiangsu",
[15][0x14 - 1] = "Zilia Technologies",
@ -1925,7 +1925,7 @@
[15][0x17 - 1] = "Nanjing Houmo Technology Co Ltd",
[15][0x18 - 1] = "Suzhou Yige Technology Co Ltd",
[15][0x19 - 1] = "Shenzhen Techwinsemi Technology Co Ltd",
[15][0x1a - 1] = "Pure Array Technology (Shanghai) Co. Ltd",
[15][0x1a - 1] = "Pure Array Technology (Shanghai) Co Ltd",
[15][0x1b - 1] = "Shenzhen Techwinsemi Technology Udstore",
[15][0x1c - 1] = "RISE MODE",
[15][0x1d - 1] = "NEWREESTAR",
@ -2016,4 +2016,37 @@
[15][0x72 - 1] = "KEYSOM",
[15][0x73 - 1] = "Shenzhen YYF Info Tech Co Ltd",
[15][0x74 - 1] = "Sharetronics Data Technology Co Ltd",
[15][0x75 - 1] = "AptCore Limited",
[15][0x76 - 1] = "Uchampion Semiconductor Co Ltd",
[15][0x77 - 1] = "YCT Semiconductor",
[15][0x78 - 1] = "FADU Inc",
[15][0x79 - 1] = "Hefei CLT Microelectronics Co LTD",
[15][0x7a - 1] = "Smart Technologies (BD) Ltd",
[15][0x7b - 1] = "Zhangdian District Qunyuan Computer Firm",
[15][0x7c - 1] = "Silicon Xpandas Electronics Co Ltd",
[15][0x7d - 1] = "PC Components Y Multimedia S",
[15][0x7e - 1] = "Shenzhen Tanlr Technology Group Co Ltd",
[16][0x01 - 1] = "Shenzhen JIEQING Technology Co Ltd",
[16][0x02 - 1] = "Orionix",
[16][0x03 - 1] = "JoulWatt Technology Co Ltd",
[16][0x04 - 1] = "Tenstorrent",
[16][0x05 - 1] = "Unis Flash Memory Technology (Chengdu)",
[16][0x06 - 1] = "Huatu Stars",
[16][0x07 - 1] = "Ardor Gaming",
[16][0x08 - 1] = "QuanZhou KunFang Semiconductor Co Ltd",
[16][0x09 - 1] = "EIAI PLANET",
[16][0x0a - 1] = "Ningbo Lingkai Semiconductor Technology Inc",
[16][0x0b - 1] = "Shenzhen Hancun Technology Co Ltd",
[16][0x0c - 1] = "Hongkong Manyi Technology Co Limited",
[16][0x0d - 1] = "Shenzhen Storgon Technology Co Ltd",
[16][0x0e - 1] = "YUNTU Microelectronics",
[16][0x0f - 1] = "Essencore",
[16][0x10 - 1] = "Shenzhen Xingyun Lianchuang Computer Tech",
[16][0x11 - 1] = "ShenZhen Aoscar Digital Tech Co Ltd",
[16][0x12 - 1] = "XOC Technologies Inc",
[16][0x13 - 1] = "BOS Semiconductors",
[16][0x14 - 1] = "Eliyan Corp",
[16][0x15 - 1] = "Hangzhou Lishu Technology Co Ltd",
[16][0x16 - 1] = "Tier IV Inc",
[16][0x17 - 1] = "Wuhan Xuanluzhe Network Technology Co",
/* EOF */

68
src/jtag/drivers/cmsis_dap.c
View File

@ -39,14 +39,22 @@
#include "cmsis_dap.h"
#include "libusb_helper.h"
static const struct cmsis_dap_backend *const cmsis_dap_backends[] = {
#if BUILD_CMSIS_DAP_USB == 1
&cmsis_dap_usb_backend,
/* Create a dummy backend for 'backend' command if real one does not build */
#if BUILD_CMSIS_DAP_USB == 0
const struct cmsis_dap_backend cmsis_dap_usb_backend = {
.name = "usb_bulk",
};
#endif
#if BUILD_CMSIS_DAP_HID == 1
&cmsis_dap_hid_backend,
#if BUILD_CMSIS_DAP_HID == 0
const struct cmsis_dap_backend cmsis_dap_hid_backend = {
.name = "hid"
};
#endif
static const struct cmsis_dap_backend *const cmsis_dap_backends[] = {
&cmsis_dap_usb_backend,
&cmsis_dap_hid_backend,
};
/* USB Config */
@ -261,26 +269,32 @@ static int cmsis_dap_open(void)
return ERROR_FAIL;
}
int retval = ERROR_FAIL;
if (cmsis_dap_backend >= 0) {
/* Use forced backend */
backend = cmsis_dap_backends[cmsis_dap_backend];
if (backend->open(dap, cmsis_dap_vid, cmsis_dap_pid, adapter_get_required_serial()) != ERROR_OK)
backend = NULL;
if (backend->open)
retval = backend->open(dap, cmsis_dap_vid, cmsis_dap_pid, adapter_get_required_serial());
else
LOG_ERROR("Requested CMSIS-DAP backend is disabled by configure");
} else {
/* Try all backends */
for (unsigned int i = 0; i < ARRAY_SIZE(cmsis_dap_backends); i++) {
backend = cmsis_dap_backends[i];
if (backend->open(dap, cmsis_dap_vid, cmsis_dap_pid, adapter_get_required_serial()) == ERROR_OK)
if (!backend->open)
continue;
retval = backend->open(dap, cmsis_dap_vid, cmsis_dap_pid, adapter_get_required_serial());
if (retval == ERROR_OK)
break;
else
backend = NULL;
}
}
if (!backend) {
if (retval != ERROR_OK) {
LOG_ERROR("unable to find a matching CMSIS-DAP device");
free(dap);
return ERROR_FAIL;
return retval;
}
dap->backend = backend;
@ -293,7 +307,8 @@ static int cmsis_dap_open(void)
static void cmsis_dap_close(struct cmsis_dap *dap)
{
if (dap->backend) {
dap->backend->close(dap);
if (dap->backend->close)
dap->backend->close(dap);
dap->backend = NULL;
}
@ -2192,22 +2207,27 @@ COMMAND_HANDLER(cmsis_dap_handle_vid_pid_command)
COMMAND_HANDLER(cmsis_dap_handle_backend_command)
{
if (CMD_ARGC == 1) {
if (strcmp(CMD_ARGV[0], "auto") == 0) {
cmsis_dap_backend = -1; /* autoselect */
} else {
for (unsigned int i = 0; i < ARRAY_SIZE(cmsis_dap_backends); i++) {
if (strcasecmp(cmsis_dap_backends[i]->name, CMD_ARGV[0]) == 0) {
if (CMD_ARGC != 1)
return ERROR_COMMAND_SYNTAX_ERROR;
if (strcmp(CMD_ARGV[0], "auto") == 0) {
cmsis_dap_backend = -1; /* autoselect */
} else {
for (unsigned int i = 0; i < ARRAY_SIZE(cmsis_dap_backends); i++) {
if (strcasecmp(cmsis_dap_backends[i]->name, CMD_ARGV[0]) == 0) {
if (cmsis_dap_backends[i]->open) {
cmsis_dap_backend = i;
return ERROR_OK;
}
}
command_print(CMD, "invalid backend argument to cmsis-dap backend <backend>");
return ERROR_COMMAND_ARGUMENT_INVALID;
command_print(CMD, "Requested cmsis-dap backend %s is disabled by configure",
cmsis_dap_backends[i]->name);
return ERROR_NOT_IMPLEMENTED;
}
}
} else {
return ERROR_COMMAND_SYNTAX_ERROR;
command_print(CMD, "invalid argument %s to cmsis-dap backend", CMD_ARGV[0]);
return ERROR_COMMAND_ARGUMENT_INVALID;
}
return ERROR_OK;

14
src/jtag/drivers/linuxspidev.c
View File

@ -302,8 +302,20 @@ static int spidev_init(void)
return ERROR_JTAG_INIT_FAILED;
}
int ret;
// Set SPI mode.
int ret = ioctl(spi_fd, SPI_IOC_WR_MODE32, &spi_mode);
#ifdef SPI_IOC_WR_MODE32
ret = ioctl(spi_fd, SPI_IOC_WR_MODE32, &spi_mode);
#else
// Linux pre 3.15 does not support MODE32, use 8-bit ioctl
if (spi_mode & ~0xff) {
LOG_ERROR("SPI mode 0x%" PRIx32 ", system permits 8 bits only", spi_mode);
return ERROR_JTAG_INIT_FAILED;
}
uint8_t mode = (uint8_t)spi_mode;
ret = ioctl(spi_fd, SPI_IOC_WR_MODE, &mode);
#endif
if (ret == -1) {
LOG_ERROR("Failed to set SPI mode 0x%" PRIx32, spi_mode);
return ERROR_JTAG_INIT_FAILED;

10
src/rtos/Makefile.am
View File

@ -11,15 +11,15 @@ noinst_LTLIBRARIES += %D%/librtos.la
%D%/rtos_ucos_iii_stackings.c \
%D%/rtos_riot_stackings.c \
%D%/rtos_nuttx_stackings.c \
%D%/FreeRTOS.c \
%D%/ThreadX.c \
%D%/eCos.c \
%D%/freertos.c \
%D%/threadx.c \
%D%/ecos.c \
%D%/linux.c \
%D%/chibios.c \
%D%/chromium-ec.c \
%D%/embKernel.c \
%D%/embkernel.c \
%D%/mqx.c \
%D%/uCOS-III.c \
%D%/ucos_iii.c \
%D%/nuttx.c \
%D%/rtkernel.c \
%D%/hwthread.c \

0
src/rtos/eCos.c → src/rtos/ecos.c
View File

0
src/rtos/embKernel.c → src/rtos/embkernel.c
View File

0
src/rtos/FreeRTOS.c → src/rtos/freertos.c
View File

0
src/rtos/ThreadX.c → src/rtos/threadx.c
View File

0
src/rtos/uCOS-III.c → src/rtos/ucos_iii.c
View File

25
src/server/gdb_server.c
View File

@ -955,7 +955,7 @@ static void gdb_fileio_reply(struct target *target, struct connection *connectio
/* encounter unknown syscall, continue */
gdb_connection->frontend_state = TARGET_RUNNING;
target_resume(target, 1, 0x0, 0, 0);
target_resume(target, true, 0x0, false, false);
return;
}
@ -965,7 +965,7 @@ static void gdb_fileio_reply(struct target *target, struct connection *connectio
if (program_exited) {
/* Use target_resume() to let target run its own exit syscall handler. */
gdb_connection->frontend_state = TARGET_RUNNING;
target_resume(target, 1, 0x0, 0, 0);
target_resume(target, true, 0x0, false, false);
} else {
gdb_connection->frontend_state = TARGET_HALTED;
rtos_update_threads(target);
@ -1755,7 +1755,7 @@ static int gdb_step_continue_packet(struct connection *connection,
char const *packet, int packet_size)
{
struct target *target = get_available_target_from_connection(connection);
int current = 0;
bool current = false;
uint64_t address = 0x0;
int retval = ERROR_OK;
@ -1764,17 +1764,17 @@ static int gdb_step_continue_packet(struct connection *connection,
if (packet_size > 1)
address = strtoull(packet + 1, NULL, 16);
else
current = 1;
current = true;
gdb_running_type = packet[0];
if (packet[0] == 'c') {
LOG_DEBUG("continue");
/* resume at current address, don't handle breakpoints, not debugging */
retval = target_resume(target, current, address, 0, 0);
retval = target_resume(target, current, address, false, false);
} else if (packet[0] == 's') {
LOG_DEBUG("step");
/* step at current or address, don't handle breakpoints */
retval = target_step(target, current, address, 0);
retval = target_step(target, current, address, false);
}
return retval;
}
@ -3080,7 +3080,7 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
LOG_TARGET_DEBUG(target, "target continue");
gdb_connection->output_flag = GDB_OUTPUT_ALL;
retval = target_resume(target, 1, 0, 0, 0);
retval = target_resume(target, true, 0, false, false);
if (retval == ERROR_TARGET_NOT_HALTED)
LOG_TARGET_INFO(target, "target was not halted when resume was requested");
@ -3108,7 +3108,7 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
bool fake_step = false;
struct target *ct = target;
int current_pc = 1;
bool current_pc = true;
int64_t thread_id;
parse++;
if (parse[0] == ':') {
@ -3222,7 +3222,7 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
"Pretending to gdb that it is running until it's available again.");
retval = ERROR_FAIL;
} else {
retval = target_step(ct, current_pc, 0, 0);
retval = target_step(ct, current_pc, 0, false);
if (retval == ERROR_TARGET_NOT_HALTED)
LOG_TARGET_INFO(ct, "target was not halted when step was requested");
}
@ -3551,9 +3551,9 @@ static int gdb_fileio_response_packet(struct connection *connection,
/* After File-I/O ends, keep continue or step */
if (gdb_running_type == 'c')
retval = target_resume(target, 1, 0x0, 0, 0);
retval = target_resume(target, true, 0x0, false, false);
else if (gdb_running_type == 's')
retval = target_step(target, 1, 0x0, 0);
retval = target_step(target, true, 0x0, false);
else
retval = ERROR_FAIL;
@ -3994,7 +3994,8 @@ static int gdb_target_add_one(struct target *target)
}
}
} else if (strcmp(gdb_port_next, "pipe") == 0) {
gdb_port_next = "disabled";
free(gdb_port_next);
gdb_port_next = strdup("disabled");
}
}
return retval;

26
src/target/aarch64.c
View File

@ -589,8 +589,8 @@ static int aarch64_halt(struct target *target)
return aarch64_halt_one(target, HALT_SYNC);
}
static int aarch64_restore_one(struct target *target, int current,
uint64_t *address, int handle_breakpoints, int debug_execution)
static int aarch64_restore_one(struct target *target, bool current,
uint64_t *address, bool handle_breakpoints, bool debug_execution)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct arm *arm = &armv8->arm;
@ -602,7 +602,7 @@ static int aarch64_restore_one(struct target *target, int current,
if (!debug_execution)
target_free_all_working_areas(target);
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
resume_pc = buf_get_u64(arm->pc->value, 0, 64);
if (!current)
resume_pc = *address;
@ -753,7 +753,8 @@ static int aarch64_restart_one(struct target *target, enum restart_mode mode)
/*
* prepare all but the current target for restart
*/
static int aarch64_prep_restart_smp(struct target *target, int handle_breakpoints, struct target **p_first)
static int aarch64_prep_restart_smp(struct target *target,
bool handle_breakpoints, struct target **p_first)
{
int retval = ERROR_OK;
struct target_list *head;
@ -772,7 +773,8 @@ static int aarch64_prep_restart_smp(struct target *target, int handle_breakpoint
continue;
/* resume at current address, not in step mode */
retval = aarch64_restore_one(curr, 1, &address, handle_breakpoints, 0);
retval = aarch64_restore_one(curr, true, &address, handle_breakpoints,
false);
if (retval == ERROR_OK)
retval = aarch64_prepare_restart_one(curr);
if (retval != ERROR_OK) {
@ -799,7 +801,7 @@ static int aarch64_step_restart_smp(struct target *target)
LOG_DEBUG("%s", target_name(target));
retval = aarch64_prep_restart_smp(target, 0, &first);
retval = aarch64_prep_restart_smp(target, false, &first);
if (retval != ERROR_OK)
return retval;
@ -864,8 +866,8 @@ static int aarch64_step_restart_smp(struct target *target)
return retval;
}
static int aarch64_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
static int aarch64_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
int retval = 0;
uint64_t addr = address;
@ -1113,8 +1115,8 @@ static int aarch64_post_debug_entry(struct target *target)
/*
* single-step a target
*/
static int aarch64_step(struct target *target, int current, target_addr_t address,
int handle_breakpoints)
static int aarch64_step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct aarch64_common *aarch64 = target_to_aarch64(target);
@ -1147,7 +1149,7 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres
if (retval != ERROR_OK)
return retval;
if (target->smp && (current == 1)) {
if (target->smp && current) {
/*
* isolate current target so that it doesn't get resumed
* together with the others
@ -1164,7 +1166,7 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres
}
/* all other targets running, restore and restart the current target */
retval = aarch64_restore_one(target, current, &address, 0, 0);
retval = aarch64_restore_one(target, current, &address, false, false);
if (retval == ERROR_OK)
retval = aarch64_restart_one(target, RESTART_LAZY);

3
src/target/adi_v5_swd.c
View File

@ -502,9 +502,6 @@ static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned int reg,
static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned int reg,
uint32_t data)
{
const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
assert(swd);
int retval = swd_check_reconnect(dap);
if (retval != ERROR_OK)
return retval;

3
src/target/algorithm.c
View File

@ -26,7 +26,8 @@ void destroy_mem_param(struct mem_param *param)
param->value = NULL;
}
void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
void init_reg_param(struct reg_param *param, const char *reg_name,
uint32_t size, enum param_direction direction)
{
param->reg_name = reg_name;
param->size = size;

4
src/target/algorithm.h
View File

@ -35,8 +35,8 @@ void init_mem_param(struct mem_param *param,
uint32_t address, uint32_t size, enum param_direction dir);
void destroy_mem_param(struct mem_param *param);
void init_reg_param(struct reg_param *param,
char *reg_name, uint32_t size, enum param_direction dir);
void init_reg_param(struct reg_param *param, const char *reg_name,
uint32_t size, enum param_direction dir);
void destroy_reg_param(struct reg_param *param);
#endif /* OPENOCD_TARGET_ALGORITHM_H */

26
src/target/arc.c
View File

@ -1100,7 +1100,7 @@ static int arc_assert_reset(struct target *target)
/* Resume the target and continue from the current
* PC register value. */
LOG_TARGET_DEBUG(target, "Starting CPU execution after reset");
CHECK_RETVAL(target_resume(target, 1, 0, 0, 0));
CHECK_RETVAL(target_resume(target, true, 0, false, false));
}
target->state = TARGET_RESET;
@ -1246,7 +1246,7 @@ exit:
return retval;
}
static int arc_enable_interrupts(struct target *target, int enable)
static int arc_enable_interrupts(struct target *target, bool enable)
{
uint32_t value;
@ -1269,8 +1269,8 @@ static int arc_enable_interrupts(struct target *target, int enable)
return ERROR_OK;
}
static int arc_resume(struct target *target, int current, target_addr_t address,
int handle_breakpoints, int debug_execution)
static int arc_resume(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints, bool debug_execution)
{
struct arc_common *arc = target_to_arc(target);
uint32_t resume_pc = 0;
@ -1297,7 +1297,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
CHECK_RETVAL(arc_enable_watchpoints(target));
}
/* current = 1: continue on current PC, otherwise continue at <address> */
/* current = true: continue on current PC, otherwise continue at <address> */
if (!current) {
target_buffer_set_u32(target, pc->value, address);
pc->dirty = true;
@ -2030,7 +2030,7 @@ static int arc_hit_watchpoint(struct target *target, struct watchpoint **hit_wat
/* Helper function which switches core to single_step mode by
* doing aux r/w operations. */
static int arc_config_step(struct target *target, int enable_step)
static int arc_config_step(struct target *target, bool enable_step)
{
uint32_t value;
@ -2071,10 +2071,10 @@ static int arc_single_step_core(struct target *target)
CHECK_RETVAL(arc_debug_entry(target));
/* disable interrupts while stepping */
CHECK_RETVAL(arc_enable_interrupts(target, 0));
CHECK_RETVAL(arc_enable_interrupts(target, false));
/* configure single step mode */
CHECK_RETVAL(arc_config_step(target, 1));
CHECK_RETVAL(arc_config_step(target, true));
/* exit debug mode */
CHECK_RETVAL(arc_exit_debug(target));
@ -2082,8 +2082,8 @@ static int arc_single_step_core(struct target *target)
return ERROR_OK;
}
static int arc_step(struct target *target, int current, target_addr_t address,
int handle_breakpoints)
static int arc_step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints)
{
/* get pointers to arch-specific information */
struct arc_common *arc = target_to_arc(target);
@ -2095,7 +2095,7 @@ static int arc_step(struct target *target, int current, target_addr_t address,
return ERROR_TARGET_NOT_HALTED;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
if (!current) {
buf_set_u32(pc->value, 0, 32, address);
pc->dirty = true;
@ -2120,10 +2120,10 @@ static int arc_step(struct target *target, int current, target_addr_t address,
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
/* disable interrupts while stepping */
CHECK_RETVAL(arc_enable_interrupts(target, 0));
CHECK_RETVAL(arc_enable_interrupts(target, false));
/* do a single step */
CHECK_RETVAL(arc_config_step(target, 1));
CHECK_RETVAL(arc_config_step(target, true));
/* make sure we done our step */
alive_sleep(1);

21
src/target/arm11.c
View File

@ -30,8 +30,8 @@
#endif
static int arm11_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints);
static int arm11_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints);
/** Check and if necessary take control of the system
@ -401,7 +401,8 @@ static int arm11_halt(struct target *target)
return ERROR_OK;
}
static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
static uint32_t arm11_nextpc(struct arm11_common *arm11, bool current,
uint32_t address)
{
void *value = arm11->arm.pc->value;
@ -435,8 +436,8 @@ static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t a
return address;
}
static int arm11_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
static int arm11_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
/* LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", */
/* current, address, handle_breakpoints, debug_execution); */
@ -469,7 +470,7 @@ static int arm11_resume(struct target *target, int current,
for (bp = target->breakpoints; bp; bp = bp->next) {
if (bp->address == address) {
LOG_DEBUG("must step over %08" TARGET_PRIxADDR "", bp->address);
arm11_step(target, 1, 0, 0);
arm11_step(target, true, 0, false);
break;
}
}
@ -543,8 +544,8 @@ static int arm11_resume(struct target *target, int current,
return ERROR_OK;
}
static int arm11_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints)
static int arm11_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
LOG_DEBUG("target->state: %s",
target_state_name(target));
@ -569,13 +570,13 @@ static int arm11_step(struct target *target, int current,
/* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070) {
address = arm11_nextpc(arm11, 0, address + 4);
address = arm11_nextpc(arm11, false, address + 4);
LOG_DEBUG("Skipping BKPT %08" TARGET_PRIxADDR, address);
}
/* skip over Wait for interrupt / Standby
* mcr 15, 0, r?, cr7, cr0, {4} */
else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) {
address = arm11_nextpc(arm11, 0, address + 4);
address = arm11_nextpc(arm11, false, address + 4);
LOG_DEBUG("Skipping WFI %08" TARGET_PRIxADDR, address);
}
/* ignore B to self */

13
src/target/arm7_9_common.c
View File

@ -1697,10 +1697,10 @@ static void arm7_9_enable_breakpoints(struct target *target)
}
int arm7_9_resume(struct target *target,
int current,
bool current,
target_addr_t address,
int handle_breakpoints,
int debug_execution)
bool handle_breakpoints,
bool debug_execution)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *arm = &arm7_9->arm;
@ -1717,7 +1717,7 @@ int arm7_9_resume(struct target *target,
if (!debug_execution)
target_free_all_working_areas(target);
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
if (!current)
buf_set_u32(arm->pc->value, 0, 32, address);
@ -1900,7 +1900,8 @@ void arm7_9_disable_eice_step(struct target *target)
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
}
int arm7_9_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int arm7_9_step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *arm = &arm7_9->arm;
@ -1912,7 +1913,7 @@ int arm7_9_step(struct target *target, int current, target_addr_t address, int h
return ERROR_TARGET_NOT_HALTED;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
if (!current)
buf_set_u32(arm->pc->value, 0, 32, address);

8
src/target/arm7_9_common.h
View File

@ -145,10 +145,10 @@ int arm7_9_early_halt(struct target *target);
int arm7_9_soft_reset_halt(struct target *target);
int arm7_9_halt(struct target *target);
int arm7_9_resume(struct target *target, int current, target_addr_t address,
int handle_breakpoints, int debug_execution);
int arm7_9_step(struct target *target, int current, target_addr_t address,
int handle_breakpoints);
int arm7_9_resume(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints, bool debug_execution);
int arm7_9_step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints);
int arm7_9_read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer);
int arm7_9_write_memory(struct target *target, target_addr_t address,

4
src/target/arm_semihosting.c
View File

@ -50,7 +50,7 @@ static int arm_semihosting_resume(struct target *target, int *retval)
if (is_armv8(target_to_armv8(target))) {
struct armv8_common *armv8 = target_to_armv8(target);
if (armv8->last_run_control_op == ARMV8_RUNCONTROL_RESUME) {
*retval = target_resume(target, 1, 0, 0, 0);
*retval = target_resume(target, true, 0, false, false);
if (*retval != ERROR_OK) {
LOG_ERROR("Failed to resume target");
return 0;
@ -58,7 +58,7 @@ static int arm_semihosting_resume(struct target *target, int *retval)
} else if (armv8->last_run_control_op == ARMV8_RUNCONTROL_STEP)
target->debug_reason = DBG_REASON_SINGLESTEP;
} else {
*retval = target_resume(target, 1, 0, 0, 0);
*retval = target_resume(target, true, 0, false, false);
if (*retval != ERROR_OK) {
LOG_ERROR("Failed to resume target");
return 0;

2
src/target/armv4_5.c
View File

@ -1514,7 +1514,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
}
}
retval = target_resume(target, 0, entry_point, 1, 1);
retval = target_resume(target, false, entry_point, true, true);
if (retval != ERROR_OK)
return retval;
retval = run_it(target, exit_point, timeout_ms, arch_info);

2
src/target/armv7m.c
View File

@ -642,7 +642,7 @@ int armv7m_start_algorithm(struct target *target,
/* save previous core mode */
armv7m_algorithm_info->core_mode = core_mode;
retval = target_resume(target, 0, entry_point, 1, 1);
retval = target_resume(target, false, entry_point, true, true);
return retval;
}

10
src/target/avr32_ap7k.c
View File

@ -300,8 +300,8 @@ static int avr32_ap7k_deassert_reset(struct target *target)
return ERROR_OK;
}
static int avr32_ap7k_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
static int avr32_ap7k_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
struct breakpoint *breakpoint = NULL;
@ -321,7 +321,7 @@ static int avr32_ap7k_resume(struct target *target, int current,
*/
}
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
if (!current) {
#if 0
if (retval != ERROR_OK)
@ -382,8 +382,8 @@ static int avr32_ap7k_resume(struct target *target, int current,
return ERROR_OK;
}
static int avr32_ap7k_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints)
static int avr32_ap7k_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
LOG_ERROR("%s: implement me", __func__);

15
src/target/avrt.c
View File

@ -22,10 +22,10 @@ static int avr_init_target(struct command_context *cmd_ctx, struct target *targe
static int avr_arch_state(struct target *target);
static int avr_poll(struct target *target);
static int avr_halt(struct target *target);
static int avr_resume(struct target *target, int current, target_addr_t address,
int handle_breakpoints, int debug_execution);
static int avr_step(struct target *target, int current, target_addr_t address,
int handle_breakpoints);
static int avr_resume(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints, bool debug_execution);
static int avr_step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints);
static int avr_assert_reset(struct target *target);
static int avr_deassert_reset(struct target *target);
@ -105,14 +105,15 @@ static int avr_halt(struct target *target)
return ERROR_OK;
}
static int avr_resume(struct target *target, int current, target_addr_t address,
int handle_breakpoints, int debug_execution)
static int avr_resume(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints, bool debug_execution)
{
LOG_DEBUG("%s", __func__);
return ERROR_OK;
}
static int avr_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
static int avr_step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints)
{
LOG_DEBUG("%s", __func__);
return ERROR_OK;

29
src/target/cortex_a.c
View File

@ -817,8 +817,8 @@ static int cortex_a_halt(struct target *target)
return ERROR_OK;
}
static int cortex_a_internal_restore(struct target *target, int current,
target_addr_t *address, int handle_breakpoints, int debug_execution)
static int cortex_a_internal_restore(struct target *target, bool current,
target_addr_t *address, bool handle_breakpoints, bool debug_execution)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *arm = &armv7a->arm;
@ -849,7 +849,7 @@ static int cortex_a_internal_restore(struct target *target, int current,
}
#endif
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
resume_pc = buf_get_u32(arm->pc->value, 0, 32);
if (!current)
resume_pc = *address;
@ -965,7 +965,7 @@ static int cortex_a_internal_restart(struct target *target)
return ERROR_OK;
}
static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
static int cortex_a_restore_smp(struct target *target, bool handle_breakpoints)
{
int retval = 0;
struct target_list *head;
@ -976,16 +976,16 @@ static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
if ((curr != target) && (curr->state != TARGET_RUNNING)
&& target_was_examined(curr)) {
/* resume current address , not in step mode */
retval += cortex_a_internal_restore(curr, 1, &address,
handle_breakpoints, 0);
retval += cortex_a_internal_restore(curr, true, &address,
handle_breakpoints, false);
retval += cortex_a_internal_restart(curr);
}
}
return retval;
}
static int cortex_a_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
static int cortex_a_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
int retval = 0;
/* dummy resume for smp toggle in order to reduce gdb impact */
@ -997,7 +997,8 @@ static int cortex_a_resume(struct target *target, int current,
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
return 0;
}
cortex_a_internal_restore(target, current, &address, handle_breakpoints, debug_execution);
cortex_a_internal_restore(target, current, &address, handle_breakpoints,
debug_execution);
if (target->smp) {
target->gdb_service->core[0] = -1;
retval = cortex_a_restore_smp(target, handle_breakpoints);
@ -1168,8 +1169,8 @@ static int cortex_a_set_dscr_bits(struct target *target,
return retval;
}
static int cortex_a_step(struct target *target, int current, target_addr_t address,
int handle_breakpoints)
static int cortex_a_step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints)
{
struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
@ -1184,7 +1185,7 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre
return ERROR_TARGET_NOT_HALTED;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
r = arm->pc;
if (!current)
buf_set_u32(r->value, 0, 32, address);
@ -1195,7 +1196,7 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre
* But since Cortex-A uses breakpoint for single step,
* we MUST handle breakpoints.
*/
handle_breakpoints = 1;
handle_breakpoints = true;
if (handle_breakpoints) {
breakpoint = breakpoint_find(target, address);
if (breakpoint)
@ -1222,7 +1223,7 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre
target->debug_reason = DBG_REASON_SINGLESTEP;
retval = cortex_a_resume(target, 1, address, 0, 0);
retval = cortex_a_resume(target, true, address, false, false);
if (retval != ERROR_OK)
return retval;

23
src/target/cortex_m.c
View File

@ -1359,7 +1359,7 @@ static int cortex_m_restore_one(struct target *target, bool current,
r->valid = true;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
r = armv7m->arm.pc;
if (!current) {
buf_set_u32(r->value, 0, 32, *address);
@ -1444,7 +1444,7 @@ static int cortex_m_restore_smp(struct target *target, bool handle_breakpoints)
continue;
int retval = cortex_m_restore_one(curr, true, &address,
handle_breakpoints, false);
handle_breakpoints, false);
if (retval != ERROR_OK)
return retval;
@ -1457,22 +1457,23 @@ static int cortex_m_restore_smp(struct target *target, bool handle_breakpoints)
return ERROR_OK;
}
static int cortex_m_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
static int cortex_m_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
int retval = cortex_m_restore_one(target, !!current, &address, !!handle_breakpoints, !!debug_execution);
int retval = cortex_m_restore_one(target, current, &address,
handle_breakpoints, debug_execution);
if (retval != ERROR_OK) {
LOG_TARGET_ERROR(target, "context restore failed, aborting resume");
return retval;
}
if (target->smp && !debug_execution) {
retval = cortex_m_restore_smp(target, !!handle_breakpoints);
retval = cortex_m_restore_smp(target, handle_breakpoints);
if (retval != ERROR_OK)
LOG_TARGET_WARNING(target, "resume of a SMP target failed, trying to resume current one");
}
cortex_m_restart_one(target, !!debug_execution);
cortex_m_restart_one(target, debug_execution);
if (retval != ERROR_OK) {
LOG_TARGET_ERROR(target, "resume failed");
return retval;
@ -1485,8 +1486,8 @@ static int cortex_m_resume(struct target *target, int current,
}
/* int irqstepcount = 0; */
static int cortex_m_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints)
static int cortex_m_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
@ -1506,7 +1507,7 @@ static int cortex_m_step(struct target *target, int current,
if (target->smp && target->gdb_service)
target->gdb_service->target = target;
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
if (!current) {
buf_set_u32(pc->value, 0, 32, address);
pc->dirty = true;
@ -2316,7 +2317,7 @@ int cortex_m_profiling(struct target *target, uint32_t *samples,
/* Make sure the target is running */
target_poll(target);
if (target->state == TARGET_HALTED)
retval = target_resume(target, 1, 0, 0, 0);
retval = target_resume(target, true, 0, false, false);
if (retval != ERROR_OK) {
LOG_TARGET_ERROR(target, "Error while resuming target");

24
src/target/dsp563xx.c
View File

@ -1115,10 +1115,10 @@ static int dsp563xx_halt(struct target *target)
}
static int dsp563xx_resume(struct target *target,
int current,
bool current,
target_addr_t address,
int handle_breakpoints,
int debug_execution)
bool handle_breakpoints,
bool debug_execution)
{
int err;
struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
@ -1132,7 +1132,7 @@ static int dsp563xx_resume(struct target *target,
if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) {
dsp563xx_write_core_reg(target, DSP563XX_REG_IDX_PC);
address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC];
current = 0;
current = false;
}
LOG_DEBUG("%s %08X %08" TARGET_PRIXADDR, __func__, current, address);
@ -1172,9 +1172,9 @@ static int dsp563xx_resume(struct target *target,
}
static int dsp563xx_step_ex(struct target *target,
int current,
bool current,
uint32_t address,
int handle_breakpoints,
bool handle_breakpoints,
int steps)
{
int err;
@ -1196,7 +1196,7 @@ static int dsp563xx_step_ex(struct target *target,
if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) {
dsp563xx_write_core_reg(target, DSP563XX_REG_IDX_PC);
address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC];
current = 0;
current = false;
}
LOG_DEBUG("%s %08X %08" PRIX32, __func__, current, address);
@ -1288,9 +1288,9 @@ static int dsp563xx_step_ex(struct target *target,
}
static int dsp563xx_step(struct target *target,
int current,
bool current,
target_addr_t address,
int handle_breakpoints)
bool handle_breakpoints)
{
int err;
struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
@ -1359,7 +1359,7 @@ static int dsp563xx_deassert_reset(struct target *target)
* reset vector and need 2 cycles to fill
* the cache (fetch,decode,execute)
*/
err = dsp563xx_step_ex(target, 1, 0, 1, 1);
err = dsp563xx_step_ex(target, true, 0, true, 1);
if (err != ERROR_OK)
return err;
}
@ -1419,7 +1419,7 @@ static int dsp563xx_run_algorithm(struct target *target,
}
/* exec */
retval = target_resume(target, 0, entry_point, 1, 1);
retval = target_resume(target, false, entry_point, true, true);
if (retval != ERROR_OK)
return retval;
@ -1972,7 +1972,7 @@ static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t addres
if (err == ERROR_OK && was_running) {
/* Resume from current PC */
err = dsp563xx_resume(target, 1, 0x0, 0, 0);
err = dsp563xx_resume(target, true, 0x0, false, false);
}
return err;

10
src/target/dsp5680xx.c
View File

@ -993,8 +993,8 @@ static int dsp5680xx_poll(struct target *target)
return ERROR_OK;
}
static int dsp5680xx_resume(struct target *target, int current,
target_addr_t address, int hb, int d)
static int dsp5680xx_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
if (target->state == TARGET_RUNNING) {
LOG_USER("Target already running.");
@ -2048,7 +2048,7 @@ int dsp5680xx_f_wr(struct target *t, const uint8_t *b, uint32_t a, uint32_t coun
retval = core_tx_upper_data(target, tmp, &drscan_data);
err_check_propagate(retval);
retval = dsp5680xx_resume(target, 0, ram_addr, 0, 0);
retval = dsp5680xx_resume(target, false, ram_addr, false, false);
err_check_propagate(retval);
int counter = FLUSH_COUNT_FLASH;
@ -2234,8 +2234,8 @@ int dsp5680xx_f_lock(struct target *target)
return retval;
}
static int dsp5680xx_step(struct target *target, int current, target_addr_t address,
int handle_breakpoints)
static int dsp5680xx_step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints)
{
err_check(ERROR_FAIL, DSP5680XX_ERROR_NOT_IMPLEMENTED_STEP,
"Not implemented yet.");

15
src/target/esirisc.c
View File

@ -846,8 +846,9 @@ static int esirisc_enable_step(struct target *target)
return ERROR_OK;
}
static int esirisc_resume_or_step(struct target *target, int current, target_addr_t address,
int handle_breakpoints, int debug_execution, bool step)
static int esirisc_resume_or_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution,
bool step)
{
struct esirisc_common *esirisc = target_to_esirisc(target);
struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
@ -917,8 +918,8 @@ static int esirisc_resume_or_step(struct target *target, int current, target_add
return ERROR_OK;
}
static int esirisc_resume(struct target *target, int current, target_addr_t address,
int handle_breakpoints, int debug_execution)
static int esirisc_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
LOG_TARGET_DEBUG(target, "-");
@ -926,13 +927,13 @@ static int esirisc_resume(struct target *target, int current, target_addr_t addr
handle_breakpoints, debug_execution, false);
}
static int esirisc_step(struct target *target, int current, target_addr_t address,
int handle_breakpoints)
static int esirisc_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
LOG_TARGET_DEBUG(target, "-");
return esirisc_resume_or_step(target, current, address,
handle_breakpoints, 0, true);
handle_breakpoints, false, true);
}
static int esirisc_debug_step(struct target *target)

3
src/target/espressif/esp32.c
View File

@ -175,7 +175,8 @@ static int esp32_soc_reset(struct target *target)
LOG_DEBUG("Resuming the target");
xtensa = target_to_xtensa(target);
xtensa->suppress_dsr_errors = true;
res = xtensa_resume(target, 0, ESP32_RTC_SLOW_MEM_BASE + 4, 0, 0);
res = xtensa_resume(target, false, ESP32_RTC_SLOW_MEM_BASE + 4, false,
false);
xtensa->suppress_dsr_errors = false;
if (res != ERROR_OK) {
LOG_ERROR("Failed to run stub (%d)!", res);

6
src/target/espressif/esp32_apptrace.c
View File

@ -708,7 +708,7 @@ int esp32_apptrace_safe_halt_targets(struct esp32_apptrace_cmd_ctx *ctx,
}
while (stat) {
/* allow this CPU to leave ERI write critical section */
res = target_resume(ctx->cpus[k], 1, 0, 1, 0);
res = target_resume(ctx->cpus[k], true, 0, true, false);
if (res != ERROR_OK) {
LOG_ERROR("Failed to resume target (%d)!", res);
breakpoint_remove(ctx->cpus[k], bp_addr);
@ -796,7 +796,7 @@ static int esp32_apptrace_connect_targets(struct esp32_apptrace_cmd_ctx *ctx,
/* in SMP mode we need to call target_resume for one core only */
continue;
}
res = target_resume(ctx->cpus[k], 1, 0, 1, 0);
res = target_resume(ctx->cpus[k], true, 0, true, false);
if (res != ERROR_OK) {
command_print(ctx->cmd, "Failed to resume target (%d)!", res);
return res;
@ -1352,7 +1352,7 @@ static int esp32_sysview_stop(struct esp32_apptrace_cmd_ctx *ctx)
/* in SMP mode we need to call target_resume for one core only */
continue;
}
res = target_resume(ctx->cpus[k], 1, 0, 1, 0);
res = target_resume(ctx->cpus[k], true, 0, true, false);
if (res != ERROR_OK) {
LOG_ERROR("sysview: Failed to resume target '%s' (%d)!", target_name(ctx->cpus[k]), res);
return res;

5
src/target/espressif/esp32s2.c
View File

@ -370,7 +370,8 @@ static int esp32s2_on_halt(struct target *target)
return ret;
}
static int esp32s2_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
static int esp32s2_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
int ret = xtensa_step(target, current, address, handle_breakpoints);
if (ret == ERROR_OK) {
@ -397,7 +398,7 @@ static int esp32s2_poll(struct target *target)
if (ret == ERROR_OK && esp_xtensa->semihost.need_resume) {
esp_xtensa->semihost.need_resume = false;
/* Resume xtensa_resume will handle BREAK instruction. */
ret = target_resume(target, 1, 0, 1, 0);
ret = target_resume(target, true, 0, true, false);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to resume target");
return ret;

3
src/target/espressif/esp32s3.c
View File

@ -175,7 +175,8 @@ static int esp32s3_soc_reset(struct target *target)
LOG_DEBUG("Resuming the target");
xtensa = target_to_xtensa(target);
xtensa->suppress_dsr_errors = true;
res = xtensa_resume(target, 0, ESP32_S3_RTC_SLOW_MEM_BASE + 4, 0, 0);
res = xtensa_resume(target, false, ESP32_S3_RTC_SLOW_MEM_BASE + 4, false,
false);
xtensa->suppress_dsr_errors = false;
if (res != ERROR_OK) {
LOG_ERROR("Failed to run stub (%d)!", res);

2
src/target/espressif/esp_xtensa.c
View File

@ -213,7 +213,7 @@ int esp_xtensa_profiling(struct target *target, uint32_t *samples,
/* Make sure the target is running */
target_poll(target);
if (target->state == TARGET_HALTED)
retval = target_resume(target, 1, 0, 0, 0);
retval = target_resume(target, true, 0, false, false);
if (retval != ERROR_OK) {
LOG_TARGET_ERROR(target, "Error while resuming target");

19
src/target/espressif/esp_xtensa_smp.c
View File

@ -218,7 +218,7 @@ int esp_xtensa_smp_poll(struct target *target)
!esp_xtensa_smp->other_core_does_resume) {
esp_xtensa->semihost.need_resume = false;
/* Resume xtensa_resume will handle BREAK instruction. */
ret = target_resume(target, 1, 0, 1, 0);
ret = target_resume(target, true, 0, true, false);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to resume target");
return ret;
@ -229,7 +229,7 @@ int esp_xtensa_smp_poll(struct target *target)
/* check whether any core polled by esp_xtensa_smp_update_halt_gdb() requested resume */
if (target->smp && other_core_resume_req) {
/* Resume xtensa_resume will handle BREAK instruction. */
ret = target_resume(target, 1, 0, 1, 0);
ret = target_resume(target, true, 0, true, false);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to resume target");
return ret;
@ -334,8 +334,7 @@ static inline int esp_xtensa_smp_smpbreak_restore(struct target *target, uint32_
}
static int esp_xtensa_smp_resume_cores(struct target *target,
int handle_breakpoints,
int debug_execution)
bool handle_breakpoints, bool debug_execution)
{
struct target_list *head;
struct target *curr;
@ -348,7 +347,7 @@ static int esp_xtensa_smp_resume_cores(struct target *target,
if ((curr != target) && (curr->state != TARGET_RUNNING) && target_was_examined(curr)) {
/* resume current address, not in SMP mode */
curr->smp = 0;
int res = esp_xtensa_smp_resume(curr, 1, 0, handle_breakpoints, debug_execution);
int res = esp_xtensa_smp_resume(curr, true, 0, handle_breakpoints, debug_execution);
curr->smp = 1;
if (res != ERROR_OK)
return res;
@ -358,10 +357,10 @@ static int esp_xtensa_smp_resume_cores(struct target *target,
}
int esp_xtensa_smp_resume(struct target *target,
int current,
bool current,
target_addr_t address,
int handle_breakpoints,
int debug_execution)
bool handle_breakpoints,
bool debug_execution)
{
int res;
uint32_t smp_break;
@ -420,9 +419,9 @@ int esp_xtensa_smp_resume(struct target *target,
}
int esp_xtensa_smp_step(struct target *target,
int current,
bool current,
target_addr_t address,
int handle_breakpoints)
bool handle_breakpoints)
{
int res;
uint32_t smp_break = 0;

10
src/target/espressif/esp_xtensa_smp.h
View File

@ -27,14 +27,14 @@ struct esp_xtensa_smp_common {
int esp_xtensa_smp_poll(struct target *target);
int esp_xtensa_smp_resume(struct target *target,
int current,
bool current,
target_addr_t address,
int handle_breakpoints,
int debug_execution);
bool handle_breakpoints,
bool debug_execution);
int esp_xtensa_smp_step(struct target *target,
int current,
bool current,
target_addr_t address,
int handle_breakpoints);
bool handle_breakpoints);
int esp_xtensa_smp_assert_reset(struct target *target);
int esp_xtensa_smp_deassert_reset(struct target *target);
int esp_xtensa_smp_soft_reset_halt(struct target *target);

2
src/target/feroceon.c
View File

@ -526,7 +526,7 @@ static int feroceon_bulk_write_memory(struct target *target,
arm->core_state = ARM_STATE_ARM;
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
arm7_9_resume(target, false, arm7_9->dcc_working_area->address, true, true);
/* send data over */
x = 0;

13
src/target/hla_target.c
View File

@ -406,7 +406,8 @@ static int hl_deassert_reset(struct target *target)
target->SAVED_DCRDR = 0; /* clear both DCC busy bits on initial resume */
return target->reset_halt ? ERROR_OK : target_resume(target, 1, 0, 0, 0);
return target->reset_halt ? ERROR_OK : target_resume(target, true, 0, false,
false);
}
static int adapter_halt(struct target *target)
@ -434,9 +435,9 @@ static int adapter_halt(struct target *target)
return ERROR_OK;
}
static int adapter_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints,
int debug_execution)
static int adapter_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints,
bool debug_execution)
{
int res;
struct hl_interface *adapter = target_to_adapter(target);
@ -525,8 +526,8 @@ static int adapter_resume(struct target *target, int current,
return ERROR_OK;
}
static int adapter_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints)
static int adapter_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
int res;
struct hl_interface *adapter = target_to_adapter(target);

10
src/target/lakemont.c
View File

@ -988,8 +988,8 @@ int lakemont_halt(struct target *t)
}
}
int lakemont_resume(struct target *t, int current, target_addr_t address,
int handle_breakpoints, int debug_execution)
int lakemont_resume(struct target *t, bool current, target_addr_t address,
bool handle_breakpoints, bool debug_execution)
{
struct breakpoint *bp = NULL;
struct x86_32_common *x86_32 = target_to_x86_32(t);
@ -1004,7 +1004,7 @@ int lakemont_resume(struct target *t, int current, target_addr_t address,
bp = breakpoint_find(t, eip);
if (bp /*&& bp->type == BKPT_SOFT*/) {
/* the step will step over the breakpoint */
if (lakemont_step(t, 0, 0, 1) != ERROR_OK) {
if (lakemont_step(t, false, 0, true) != ERROR_OK) {
LOG_ERROR("%s stepping over a software breakpoint at 0x%08" PRIx32 " "
"failed to resume the target", __func__, eip);
return ERROR_FAIL;
@ -1029,8 +1029,8 @@ int lakemont_resume(struct target *t, int current, target_addr_t address,
return ERROR_OK;
}
int lakemont_step(struct target *t, int current,
target_addr_t address, int handle_breakpoints)
int lakemont_step(struct target *t, bool current, target_addr_t address,
bool handle_breakpoints)
{
struct x86_32_common *x86_32 = target_to_x86_32(t);
uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);

8
src/target/lakemont.h
View File

@ -84,10 +84,10 @@ int lakemont_init_arch_info(struct target *t, struct x86_32_common *x86_32);
int lakemont_poll(struct target *t);
int lakemont_arch_state(struct target *t);
int lakemont_halt(struct target *t);
int lakemont_resume(struct target *t, int current, target_addr_t address,
int handle_breakpoints, int debug_execution);
int lakemont_step(struct target *t, int current,
target_addr_t address, int handle_breakpoints);
int lakemont_resume(struct target *t, bool current, target_addr_t address,
bool handle_breakpoints, bool debug_execution);
int lakemont_step(struct target *t, bool current,
target_addr_t address, bool handle_breakpoints);
int lakemont_reset_assert(struct target *t);
int lakemont_reset_deassert(struct target *t);
int lakemont_update_after_probemode_entry(struct target *t);

8
src/target/ls1_sap.c
View File

@ -55,15 +55,15 @@ static int ls1_sap_halt(struct target *target)
return ERROR_OK;
}
static int ls1_sap_resume(struct target *target, int current, target_addr_t address,
int handle_breakpoints, int debug_execution)
static int ls1_sap_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
LOG_DEBUG("%s", __func__);
return ERROR_OK;
}
static int ls1_sap_step(struct target *target, int current, target_addr_t address,
int handle_breakpoints)
static int ls1_sap_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
LOG_DEBUG("%s", __func__);
return ERROR_OK;

9
src/target/mem_ap.c
View File

@ -102,8 +102,9 @@ static int mem_ap_halt(struct target *target)
return ERROR_OK;
}
static int mem_ap_resume(struct target *target, int current, target_addr_t address,
int handle_breakpoints, int debug_execution)
static int mem_ap_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints,
bool debug_execution)
{
LOG_TARGET_DEBUG(target, "%s", __func__);
target->state = TARGET_RUNNING;
@ -111,8 +112,8 @@ static int mem_ap_resume(struct target *target, int current, target_addr_t addre
return ERROR_OK;
}
static int mem_ap_step(struct target *target, int current, target_addr_t address,
int handle_breakpoints)
static int mem_ap_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
LOG_TARGET_DEBUG(target, "%s", __func__);
target->state = TARGET_HALTED;

2
src/target/mips32.c
View File

@ -588,7 +588,7 @@ static int mips32_run_and_wait(struct target *target, target_addr_t entry_point,
int retval;
/* This code relies on the target specific resume() and poll()->debug_entry()
* sequence to write register values to the processor and the read them back */
retval = target_resume(target, 0, entry_point, 0, 1);
retval = target_resume(target, false, entry_point, false, true);
if (retval != ERROR_OK)
return retval;

32
src/target/mips_m4k.c
View File

@ -30,9 +30,9 @@ static int mips_m4k_set_breakpoint(struct target *target,
struct breakpoint *breakpoint);
static int mips_m4k_unset_breakpoint(struct target *target,
struct breakpoint *breakpoint);
static int mips_m4k_internal_restore(struct target *target, int current,
target_addr_t address, int handle_breakpoints,
int debug_execution);
static int mips_m4k_internal_restore(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints,
bool debug_execution);
static int mips_m4k_halt(struct target *target);
static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
uint32_t count, const uint8_t *buffer);
@ -398,7 +398,8 @@ static int mips_m4k_single_step_core(struct target *target)
return ERROR_OK;
}
static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
static int mips_m4k_restore_smp(struct target *target, uint32_t address,
bool handle_breakpoints)
{
int retval = ERROR_OK;
struct target_list *head;
@ -408,8 +409,8 @@ static int mips_m4k_restore_smp(struct target *target, uint32_t address, int han
struct target *curr = head->target;
if ((curr != target) && (curr->state != TARGET_RUNNING)) {
/* resume current address , not in step mode */
ret = mips_m4k_internal_restore(curr, 1, address,
handle_breakpoints, 0);
ret = mips_m4k_internal_restore(curr, true, address,
handle_breakpoints, false);
if (ret != ERROR_OK) {
LOG_TARGET_ERROR(curr, "failed to resume at address: 0x%" PRIx32,
@ -421,8 +422,9 @@ static int mips_m4k_restore_smp(struct target *target, uint32_t address, int han
return retval;
}
static int mips_m4k_internal_restore(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
static int mips_m4k_internal_restore(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints,
bool debug_execution)
{
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
@ -440,7 +442,7 @@ static int mips_m4k_internal_restore(struct target *target, int current,
mips_m4k_enable_watchpoints(target);
}
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
if (!current) {
mips_m4k_isa_filter(mips32->isa_imp, &address);
buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32, address);
@ -448,7 +450,7 @@ static int mips_m4k_internal_restore(struct target *target, int current,
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].valid = true;
}
if ((mips32->isa_imp > 1) && debug_execution) /* if more than one isa supported */
if (mips32->isa_imp > 1 && debug_execution) /* if more than one isa supported */
buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 1, mips32->isa_mode);
if (!current)
@ -494,8 +496,8 @@ static int mips_m4k_internal_restore(struct target *target, int current,
return ERROR_OK;
}
static int mips_m4k_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
static int mips_m4k_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
int retval = ERROR_OK;
@ -521,8 +523,8 @@ static int mips_m4k_resume(struct target *target, int current,
return retval;
}
static int mips_m4k_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints)
static int mips_m4k_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
@ -534,7 +536,7 @@ static int mips_m4k_step(struct target *target, int current,
return ERROR_TARGET_NOT_HALTED;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
if (!current) {
mips_m4k_isa_filter(mips32->isa_imp, &address);
buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32, address);

14
src/target/mips_mips64.c
View File

@ -592,9 +592,9 @@ static int mips_mips64_unset_breakpoint(struct target *target,
return ERROR_OK;
}
static int mips_mips64_resume(struct target *target, int current,
uint64_t address, int handle_breakpoints,
int debug_execution)
static int mips_mips64_resume(struct target *target, bool current,
uint64_t address, bool handle_breakpoints,
bool debug_execution)
{
struct mips64_common *mips64 = target->arch_info;
struct mips_ejtag *ejtag_info = &mips64->ejtag_info;
@ -622,7 +622,7 @@ static int mips_mips64_resume(struct target *target, int current,
}
pc = &mips64->core_cache->reg_list[MIPS64_PC];
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
if (!current) {
buf_set_u64(pc->value, 0, 64, address);
pc->dirty = true;
@ -696,8 +696,8 @@ static int mips_mips64_resume(struct target *target, int current,
return ERROR_OK;
}
static int mips_mips64_step(struct target *target, int current,
uint64_t address, int handle_breakpoints)
static int mips_mips64_step(struct target *target, bool current,
uint64_t address, bool handle_breakpoints)
{
struct mips64_common *mips64 = target->arch_info;
struct mips_ejtag *ejtag_info = &mips64->ejtag_info;
@ -713,7 +713,7 @@ static int mips_mips64_step(struct target *target, int current,
if (mips64->mips64mode32)
address = mips64_extend_sign(address);
/* current = 1: continue on current pc, otherwise continue at
/* current = true: continue on current pc, otherwise continue at
* <address> */
if (!current) {
buf_set_u64(pc->value, 0, 64, address);

19
src/target/openrisc/or1k.c
View File

@ -775,9 +775,9 @@ static bool is_any_soft_breakpoint(struct target *target)
return false;
}
static int or1k_resume_or_step(struct target *target, int current,
uint32_t address, int handle_breakpoints,
int debug_execution, int step)
static int or1k_resume_or_step(struct target *target, bool current,
uint32_t address, bool handle_breakpoints, bool debug_execution,
int step)
{
struct or1k_common *or1k = target_to_or1k(target);
struct or1k_du *du_core = or1k_to_du(or1k);
@ -885,9 +885,8 @@ static int or1k_resume_or_step(struct target *target, int current,
return ERROR_OK;
}
static int or1k_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints,
int debug_execution)
static int or1k_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
return or1k_resume_or_step(target, current, address,
handle_breakpoints,
@ -895,12 +894,12 @@ static int or1k_resume(struct target *target, int current,
NO_SINGLE_STEP);
}
static int or1k_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints)
static int or1k_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
return or1k_resume_or_step(target, current, address,
handle_breakpoints,
0,
false,
SINGLE_STEP);
}
@ -1216,7 +1215,7 @@ static int or1k_profiling(struct target *target, uint32_t *samples,
/* Make sure the target is running */
target_poll(target);
if (target->state == TARGET_HALTED)
retval = target_resume(target, 1, 0, 0, 0);
retval = target_resume(target, true, 0, false, false);
if (retval != ERROR_OK) {
LOG_ERROR("Error while resuming target");

2
src/target/quark_d20xx.c
View File

@ -65,7 +65,7 @@ static int quark_d20xx_reset_deassert(struct target *t)
}
/* resume target if reset mode is run */
if (!t->reset_halt) {
retval = lakemont_resume(t, 1, 0, 0, 0);
retval = lakemont_resume(t, true, 0, false, false);
if (retval != ERROR_OK) {
LOG_ERROR("%s could not resume target", __func__);
return retval;

9
src/target/riscv/riscv-011.c
View File

@ -1453,8 +1453,8 @@ static int strict_step(struct target *target, bool announce)
return ERROR_OK;
}
static int step(struct target *target, int current, target_addr_t address,
int handle_breakpoints)
static int step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints)
{
jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
@ -1947,8 +1947,9 @@ static int riscv011_poll(struct target *target)
return poll_target(target, true);
}
static int riscv011_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
static int riscv011_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints,
bool debug_execution)
{
RISCV_INFO(r);
jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);

51
src/target/riscv/riscv.c
View File

@ -2428,8 +2428,8 @@ static int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_w
return ERROR_FAIL;
}
static int oldriscv_step(struct target *target, int current, uint32_t address,
int handle_breakpoints)
static int oldriscv_step(struct target *target, bool current, uint32_t address,
bool handle_breakpoints)
{
struct target_type *tt = get_target_type(target);
if (!tt)
@ -2437,14 +2437,15 @@ static int oldriscv_step(struct target *target, int current, uint32_t address,
return tt->step(target, current, address, handle_breakpoints);
}
static int riscv_openocd_step_impl(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int handle_callbacks);
static int riscv_openocd_step_impl(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, int handle_callbacks);
static int old_or_new_riscv_step_impl(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int handle_callbacks)
static int old_or_new_riscv_step_impl(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, int handle_callbacks)
{
RISCV_INFO(r);
LOG_TARGET_DEBUG(target, "handle_breakpoints=%d", handle_breakpoints);
LOG_TARGET_DEBUG(target, "handle_breakpoints=%s",
handle_breakpoints ? "true" : "false");
if (!r->get_hart_state)
return oldriscv_step(target, current, address, handle_breakpoints);
else
@ -2452,8 +2453,8 @@ static int old_or_new_riscv_step_impl(struct target *target, int current,
handle_callbacks);
}
static int old_or_new_riscv_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints)
static int old_or_new_riscv_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
return old_or_new_riscv_step_impl(target, current, address,
handle_breakpoints, true /* handle callbacks*/);
@ -2817,8 +2818,8 @@ static int enable_watchpoints(struct target *target, bool *wp_is_set)
/**
* Get everything ready to resume.
*/
static int resume_prep(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
static int resume_prep(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
assert(target->state == TARGET_HALTED);
RISCV_INFO(r);
@ -2859,8 +2860,8 @@ static int resume_prep(struct target *target, int current,
* Resume all the harts that have been prepped, as close to instantaneous as
* possible.
*/
static int resume_go(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
static int resume_go(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
assert(target->state == TARGET_HALTED);
RISCV_INFO(r);
@ -2878,7 +2879,7 @@ static int resume_go(struct target *target, int current,
return result;
}
static int resume_finish(struct target *target, int debug_execution)
static int resume_finish(struct target *target, bool debug_execution)
{
assert(target->state == TARGET_HALTED);
if (riscv_reg_cache_any_dirty(target, LOG_LVL_ERROR)) {
@ -2903,10 +2904,10 @@ static int resume_finish(struct target *target, int debug_execution)
*/
static int riscv_resume(
struct target *target,
int current,
bool current,
target_addr_t address,
int handle_breakpoints,
int debug_execution,
bool handle_breakpoints,
bool debug_execution,
bool single_hart)
{
int result = ERROR_OK;
@ -2967,8 +2968,8 @@ static int riscv_resume(
return result;
}
static int riscv_target_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
static int riscv_target_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "Not halted.");
@ -3649,8 +3650,8 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
return ERROR_FAIL;
/* Run algorithm */
LOG_TARGET_DEBUG(target, "Resume at 0x%" TARGET_PRIxADDR, entry_point);
if (riscv_resume(target, 0, entry_point, 0, 1, true) != ERROR_OK)
LOG_TARGET_DEBUG(target, "resume at 0x%" TARGET_PRIxADDR, entry_point);
if (riscv_resume(target, false, entry_point, false, true, true) != ERROR_OK)
return ERROR_FAIL;
int64_t start = timeval_ms();
@ -4133,8 +4134,8 @@ int riscv_openocd_poll(struct target *target)
return ERROR_OK;
}
static int riscv_openocd_step_impl(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int handle_callbacks)
static int riscv_openocd_step_impl(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, int handle_callbacks)
{
LOG_TARGET_DEBUG(target, "stepping hart");
@ -4228,8 +4229,8 @@ _exit:
return success ? ERROR_OK : ERROR_FAIL;
}
int riscv_openocd_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints)
int riscv_openocd_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
return riscv_openocd_step_impl(target, current, address, handle_breakpoints,
true /* handle_callbacks */);

4
src/target/riscv/riscv.h
View File

@ -449,9 +449,9 @@ int riscv_halt(struct target *target);
int riscv_openocd_step(
struct target *target,
int current,
bool current,
target_addr_t address,
int handle_breakpoints
bool handle_breakpoints
);
/*** RISC-V Interface ***/

16
src/target/stm8.c
View File

@ -980,9 +980,9 @@ static int stm8_single_step_core(struct target *target)
return ERROR_OK;
}
static int stm8_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints,
int debug_execution)
static int stm8_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints,
bool debug_execution)
{
struct stm8_common *stm8 = target_to_stm8(target);
struct breakpoint *breakpoint = NULL;
@ -1004,7 +1004,7 @@ static int stm8_resume(struct target *target, int current,
stm8_set_hwbreak(target, comparator_list);
}
/* current = 1: continue on current pc,
/* current = true: continue on current pc,
otherwise continue at <address> */
if (!current) {
buf_set_u32(stm8->core_cache->reg_list[STM8_PC].value,
@ -1290,8 +1290,8 @@ static int stm8_arch_state(struct target *target)
return ERROR_OK;
}
static int stm8_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints)
static int stm8_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
LOG_DEBUG("%x " TARGET_ADDR_FMT " %x",
current, address, handle_breakpoints);
@ -1305,7 +1305,7 @@ static int stm8_step(struct target *target, int current,
return ERROR_TARGET_NOT_HALTED;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
if (!current) {
buf_set_u32(stm8->core_cache->reg_list[STM8_PC].value, 0, 32, address);
stm8->core_cache->reg_list[STM8_PC].dirty = true;
@ -1789,7 +1789,7 @@ static int stm8_run_and_wait(struct target *target, uint32_t entry_point,
/* This code relies on the target specific resume() and
poll()->debug_entry() sequence to write register values to the
processor and the read them back */
retval = target_resume(target, 0, entry_point, 0, 1);
retval = target_resume(target, false, entry_point, false, true);
if (retval != ERROR_OK)
return retval;

21
src/target/target.c
View File

@ -554,8 +554,8 @@ int target_halt(struct target *target)
* hand the infrastructure for running such helpers might use this
* procedure but rely on hardware breakpoint to detect termination.)
*/
int target_resume(struct target *target, int current, target_addr_t address,
int handle_breakpoints, int debug_execution)
int target_resume(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints, bool debug_execution)
{
int retval;
@ -580,7 +580,8 @@ int target_resume(struct target *target, int current, target_addr_t address,
* in the correct order.
*/
bool save_poll_mask = jtag_poll_mask();
retval = target->type->resume(target, current, address, handle_breakpoints, debug_execution);
retval = target->type->resume(target, current, address, handle_breakpoints,
debug_execution);
jtag_poll_unmask(save_poll_mask);
if (retval != ERROR_OK)
@ -1414,7 +1415,7 @@ bool target_supports_gdb_connection(const struct target *target)
}
int target_step(struct target *target,
int current, target_addr_t address, int handle_breakpoints)
bool current, target_addr_t address, bool handle_breakpoints)
{
int retval;
@ -2315,7 +2316,7 @@ int target_profiling_default(struct target *target, uint32_t *samples,
uint32_t t = buf_get_u32(reg->value, 0, 32);
samples[sample_count++] = t;
/* current pc, addr = 0, do not handle breakpoints, not debugging */
retval = target_resume(target, 1, 0, 0, 0);
retval = target_resume(target, true, 0, false, false);
target_poll(target);
alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
} else if (target->state == TARGET_RUNNING) {
@ -3297,7 +3298,7 @@ COMMAND_HANDLER(handle_reset_command)
COMMAND_HANDLER(handle_resume_command)
{
int current = 1;
bool current = true;
if (CMD_ARGC > 1)
return ERROR_COMMAND_SYNTAX_ERROR;
@ -3309,10 +3310,10 @@ COMMAND_HANDLER(handle_resume_command)
target_addr_t addr = 0;
if (CMD_ARGC == 1) {
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr);
current = 0;
current = false;
}
return target_resume(target, current, addr, 1, 0);
return target_resume(target, current, addr, true, false);
}
COMMAND_HANDLER(handle_step_command)
@ -3334,7 +3335,7 @@ COMMAND_HANDLER(handle_step_command)
struct target *target = get_current_target(CMD_CTX);
return target_step(target, current_pc, addr, 1);
return target_step(target, current_pc, addr, true);
}
void target_handle_md_output(struct command_invocation *cmd,
@ -4363,7 +4364,7 @@ COMMAND_HANDLER(handle_profile_command)
} else if (target->state == TARGET_HALTED && !halted_before_profiling) {
/* The target was running before we started and is halted now. Resume
* it, for consistency. */
retval = target_resume(target, 1, 0, 0, 0);
retval = target_resume(target, true, 0, false, false);
if (retval != ERROR_OK) {
free(samples);
return retval;

6
src/target/target.h
View File

@ -392,8 +392,8 @@ int target_unregister_trace_callback(
* yet it is possible to detect error conditions.
*/
int target_poll(struct target *target);
int target_resume(struct target *target, int current, target_addr_t address,
int handle_breakpoints, int debug_execution);
int target_resume(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints, bool debug_execution);
int target_halt(struct target *target);
int target_call_event_callbacks(struct target *target, enum target_event event);
int target_call_reset_callbacks(struct target *target, enum target_reset_mode reset_mode);
@ -542,7 +542,7 @@ bool target_supports_gdb_connection(const struct target *target);
* This routine is a wrapper for target->type->step.
*/
int target_step(struct target *target,
int current, target_addr_t address, int handle_breakpoints);
bool current, target_addr_t address, bool handle_breakpoints);
/**
* Run an algorithm on the @a target given.
*

8
src/target/target_type.h
View File

@ -42,10 +42,10 @@ struct target_type {
/* halt will log a warning, but return ERROR_OK if the target is already halted. */
int (*halt)(struct target *target);
/* See target.c target_resume() for documentation. */
int (*resume)(struct target *target, int current, target_addr_t address,
int handle_breakpoints, int debug_execution);
int (*step)(struct target *target, int current, target_addr_t address,
int handle_breakpoints);
int (*resume)(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints, bool debug_execution);
int (*step)(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints);
/* target reset control. assert reset can be invoked when OpenOCD and
* the target is out of sync.
*

24
src/target/xscale.c
View File

@ -47,8 +47,8 @@
*/
/* forward declarations */
static int xscale_resume(struct target *, int current,
target_addr_t address, int handle_breakpoints, int debug_execution);
static int xscale_resume(struct target *, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution);
static int xscale_debug_entry(struct target *);
static int xscale_restore_banked(struct target *);
static int xscale_get_reg(struct reg *reg);
@ -997,7 +997,7 @@ static int xscale_debug_entry(struct target *target)
* can only happen in fill mode. */
if (xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL) {
if (--xscale->trace.fill_counter > 0)
xscale_resume(target, 1, 0x0, 1, 0);
xscale_resume(target, true, 0x0, true, false);
} else /* entered debug for other reason; reset counter */
xscale->trace.fill_counter = 0;
}
@ -1106,8 +1106,8 @@ static void xscale_free_trace_data(struct xscale_common *xscale)
xscale->trace.data = NULL;
}
static int xscale_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution)
static int xscale_resume(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
struct xscale_common *xscale = target_to_xscale(target);
struct arm *arm = &xscale->arm;
@ -1130,7 +1130,7 @@ static int xscale_resume(struct target *target, int current,
if (retval != ERROR_OK)
return retval;
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
if (!current)
buf_set_u32(arm->pc->value, 0, 32, address);
@ -1277,8 +1277,8 @@ static int xscale_resume(struct target *target, int current,
return ERROR_OK;
}
static int xscale_step_inner(struct target *target, int current,
uint32_t address, int handle_breakpoints)
static int xscale_step_inner(struct target *target, bool current,
uint32_t address, bool handle_breakpoints)
{
struct xscale_common *xscale = target_to_xscale(target);
struct arm *arm = &xscale->arm;
@ -1372,8 +1372,8 @@ static int xscale_step_inner(struct target *target, int current,
return ERROR_OK;
}
static int xscale_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints)
static int xscale_step(struct target *target, bool current,
target_addr_t address, bool handle_breakpoints)
{
struct arm *arm = target_to_arm(target);
struct breakpoint *breakpoint = NULL;
@ -1386,7 +1386,7 @@ static int xscale_step(struct target *target, int current,
return ERROR_TARGET_NOT_HALTED;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
/* current = true: continue on current pc, otherwise continue at <address> */
if (!current)
buf_set_u32(arm->pc->value, 0, 32, address);
@ -1598,7 +1598,7 @@ static int xscale_deassert_reset(struct target *target)
target->state = TARGET_HALTED;
/* resume the target */
xscale_resume(target, 1, 0x0, 1, 0);
xscale_resume(target, true, 0x0, true, false);
}
}

25
src/target/xtensa/xtensa.c
View File

@ -1591,10 +1591,10 @@ int xtensa_halt(struct target *target)
}
int xtensa_prepare_resume(struct target *target,
int current,
bool current,
target_addr_t address,
int handle_breakpoints,
int debug_execution)
bool handle_breakpoints,
bool debug_execution)
{
struct xtensa *xtensa = target_to_xtensa(target);
uint32_t bpena = 0;
@ -1671,13 +1671,14 @@ int xtensa_do_resume(struct target *target)
}
int xtensa_resume(struct target *target,
int current,
bool current,
target_addr_t address,
int handle_breakpoints,
int debug_execution)
bool handle_breakpoints,
bool debug_execution)
{
LOG_TARGET_DEBUG(target, "start");
int res = xtensa_prepare_resume(target, current, address, handle_breakpoints, debug_execution);
int res = xtensa_prepare_resume(target, current, address,
handle_breakpoints, debug_execution);
if (res != ERROR_OK) {
LOG_TARGET_ERROR(target, "Failed to prepare for resume!");
return res;
@ -1719,7 +1720,8 @@ static bool xtensa_pc_in_winexc(struct target *target, target_addr_t pc)
return false;
}
int xtensa_do_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int xtensa_do_step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints)
{
struct xtensa *xtensa = target_to_xtensa(target);
int res;
@ -1844,7 +1846,7 @@ int xtensa_do_step(struct target *target, int current, target_addr_t address, in
/* Now that ICOUNT (LX) or DCR.StepRequest (NX) is set,
* we can resume as if we were going to run
*/
res = xtensa_prepare_resume(target, current, address, 0, 0);
res = xtensa_prepare_resume(target, current, address, false, false);
if (res != ERROR_OK) {
LOG_TARGET_ERROR(target, "Failed to prepare resume for single step");
return res;
@ -1941,7 +1943,8 @@ int xtensa_do_step(struct target *target, int current, target_addr_t address, in
return res;
}
int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
int xtensa_step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints)
{
int retval = xtensa_do_step(target, current, address, handle_breakpoints);
if (retval != ERROR_OK)
@ -2806,7 +2809,7 @@ int xtensa_start_algorithm(struct target *target,
}
}
return xtensa_resume(target, 0, entry_point, 1, 1);
return xtensa_resume(target, false, entry_point, true, true);
}
/** Waits for an algorithm in the target. */

18
src/target/xtensa/xtensa.h
View File

@ -378,18 +378,20 @@ int xtensa_poll(struct target *target);
void xtensa_on_poll(struct target *target);
int xtensa_halt(struct target *target);
int xtensa_resume(struct target *target,
int current,
bool current,
target_addr_t address,
int handle_breakpoints,
int debug_execution);
bool handle_breakpoints,
bool debug_execution);
int xtensa_prepare_resume(struct target *target,
int current,
bool current,
target_addr_t address,
int handle_breakpoints,
int debug_execution);
bool handle_breakpoints,
bool debug_execution);
int xtensa_do_resume(struct target *target);
int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints);
int xtensa_do_step(struct target *target, int current, target_addr_t address, int handle_breakpoints);
int xtensa_step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints);
int xtensa_do_step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints);
int xtensa_mmu_is_enabled(struct target *target, int *enabled);
int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer);

34
tcl/target/bl602.cfg Normal file
View File

@ -0,0 +1,34 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Bouffalo Labs BL602 and BL604 target
#
# https://en.bouffalolab.com/product/?type=detail&id=1
#
# Default JTAG pins: (if not changed by eFuse configuration)
# TDO - GPIO11
# TMS - GPIO12
# TCK - GPIO14
# TDI - GPIO17
#
if { [info exists CHIPNAME] } {
set BL602_CHIPNAME $CHIPNAME
} else {
set BL602_CHIPNAME bl602
}
set CPUTAPID 0x20000c05
# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1 cache and XIP
set WORKAREAADDR 0x42014000
set WORKAREASIZE 0xC000
source [find target/bl602_common.cfg]
# JTAG reset is broken. Read comment of bl602_sw_reset_hbn_wait function for more information
$_TARGETNAME configure -event reset-assert {
halt
bl602_sw_reset_hbn_wait
}

143
tcl/target/bl602_common.cfg Normal file
View File

@ -0,0 +1,143 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# Script for Bouffalo chips with similar architecture used in BL602
# based on SiFive E21 core
source [find mem_helper.tcl]
transport select jtag
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
error "you must specify a tap id"
}
if { [info exists BL602_CHIPNAME] } {
set _CHIPNAME $BL602_CHIPNAME
} else {
error "you must specify a chip name"
}
if { [info exists WORKAREAADDR] } {
set _WORKAREAADDR $WORKAREAADDR
} else {
error "you must specify a work area address"
}
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
error "you must specify a work area size"
}
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
riscv set_mem_access sysbus
riscv set_enable_virt2phys off
$_TARGETNAME configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 1
# Internal RC ticks on 32 MHz, so this speed should be safe to use.
adapter speed 8000
# Useful functions
set dmcontrol 0x10
set dmcontrol_dmactive [expr {1 << 0}]
set dmcontrol_ndmreset [expr {1 << 1}]
set dmcontrol_resumereq [expr {1 << 30}]
set dmcontrol_haltreq [expr {1 << 31}]
proc bl602_restore_clock_defaults { } {
# Switch clock to internal RC32M
# In HBN_GLB, set ROOT_CLK_SEL = 0
mmw 0x4000f030 0x0 0x00000003
# Wait for clock switch
sleep 10
# GLB_REG_BCLK_DIS_FALSE
mww 0x40000ffc 0x0
# HCLK is RC32M, so BCLK/HCLK doesn't need divider
# In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
mmw 0x40000000 0x0 0x00FFFF00
# Wait for clock to stabilize
sleep 10
}
# By spec, ndmreset should reset whole chip. This implementation resets only few parts of the chip.
# CTRL_PWRON_RESET register in GLB core triggers full "power-on like" reset, so we use it instead
# for full software reset.
proc bl602_sw_reset { } {
# In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
mmw 0x40000018 0x0 0x00000007
# This Software reset method resets everything, so CPU as well.
# It does that in not much good way, resulting in Debug Module being reset as well.
# This also means, that right after CPU and Debug Module are turned on, we need to
# enable Debug Module and halt CPU if needed. Additionally, we trigger this SW reset
# through system bus access directly with DMI commands, to avoid errors printed by
# OpenOCD about unsuccessful register write.
# In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
riscv dmi_write 0x39 0x40000018
riscv dmi_write 0x3c 0x7
# We need to wait for chip to finish reset and execute BootROM
sleep 1
# JTAG Debug Transport Module is reset as well, so we need to get into RUN/IDLE state
runtest 10
# We need to enable Debug Module and halt the CPU, so we can reset Program Counter
# and to do additional clean-ups. If reset was called without halt, resume is handled
# by reset-deassert-post event handler.
# In Debug Module Control (dmcontrol), set dmactive to 1 and then haltreq to 1
riscv dmi_write $::dmcontrol $::dmcontrol_dmactive
riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_haltreq} ]
# Set Program Counter to start of BootROM
set_reg {pc 0x21000000}
}
# On BL602 and BL702, the only way to force chip stay in BootROM (until JTAG attaches)
# is by putting infinity loop into HBN RAM (which is not reset by sw reset), and then
# configure HBN registers, which will cause BootROM to jump into our code early in BootROM.
proc bl602_sw_reset_hbn_wait {} {
# Restore clocks to defaults
bl602_restore_clock_defaults
# In HBN RAM, write infinity loop instruction
# beq zero, zero, 0
mww 0x40010000 0x00000063
# In HNB, set HBN_RSV0 (Status Flag) to "EHBN" (as uint32_t)
mww 0x4000f100 0x4e424845
# In HBN, set HBN_RSV1 (WakeUp Address) to HBN RAM address
mww 0x4000f104 0x40010000
# Perform software reset
bl602_sw_reset
# Clear HBN RAM, HBN_RSV0 and HBN_RSV1
mww 0x40010000 0x00000000
mww 0x4000f100 0x00000000
mww 0x4000f104 0x00000000
# This early jump method locks up BootROM through Trust Zone Controller.
# That means any read of BootROM returns 0xDEADBEEF.
# Only way to reset it, is through JTAG Reset, thus toggling ndmreset in dmcontrol.
riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_ndmreset} ]
riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive} ]
}
$_TARGETNAME configure -event reset-deassert-post {
# Resume the processor if reset was triggered without halt request
if {$halt == 0} {
riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_resumereq} ]
}
}

59
tcl/target/bl702.cfg
View File

@ -12,62 +12,23 @@
# TDO - GPIO9
#
source [find mem_helper.tcl]
transport select jtag
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
set BL602_CHIPNAME $CHIPNAME
} else {
set _CHIPNAME bl702
set BL602_CHIPNAME bl702
}
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000e05
set CPUTAPID 0x20000e05
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1 cache and XIP
set WORKAREAADDR 0x22014000
set WORKAREASIZE 0xC000
riscv set_mem_access sysbus
source [find target/bl602_common.cfg]
$_TARGETNAME configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1
# Internal RC ticks on 32 MHz, so this speed should be safe to use.
adapter speed 4000
# Debug Module's ndmreset resets only Trust Zone Controller, so we need to do SW reset instead.
# CTRL_PWRON_RESET triggers full "power-on like" reset.
# This means that pinmux configuration to access JTAG is reset as well, and configured back early
# in BootROM.
$_TARGETNAME configure -event reset-assert-pre {
# JTAG reset is broken. Read comment of bl602_sw_reset_hbn_wait function for more information
$_TARGETNAME configure -event reset-assert {
halt
# Switch clock to internal RC32M
# In HBN_GLB, set ROOT_CLK_SEL = 0
mmw 0x4000f030 0x0 0x00000003
# Wait for clock switch
sleep 10
# GLB_REG_BCLK_DIS_FALSE
mww 0x40000ffc 0x0
# HCLK is RC32M, so BCLK/HCLK doesn't need divider
# In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
mmw 0x40000000 0x0 0x00FFFF00
# Wait for clock to stabilize
sleep 10
# Do reset
# In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
mmw 0x40000018 0x0 0x00000007
# Since this full software reset resets GPIO pinmux as well, we will lose access
# to JTAG right away after writing to register. This chip doesn't support abstract
# memory access, so when this is done by progbuf or sysbus, OpenOCD will fail to read
# if write was successful or not, and will print error about that. Since receiving of
# this error is expected, we will turn off log printing for a moment,
set lvl [lindex [debug_level] 1]
debug_level -1
# In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
catch {mmw 0x40000018 0x7 0x0}
debug_level $lvl
bl602_sw_reset_hbn_wait
}

47
tcl/target/bl702l.cfg Normal file
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@ -0,0 +1,47 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Bouffalo Labs BL702L and BL704L target
#
# https://en.bouffalolab.com/product/?type=detail&id=26
#
# Default JTAG pins: (if not changed by eFuse configuration)
# TMS - GPIO0
# TDI - GPIO1
# TCK - GPIO2
# TDO - GPIO7
#
if { [info exists CHIPNAME] } {
set BL602_CHIPNAME $CHIPNAME
} else {
set BL602_CHIPNAME bl702l
}
set CPUTAPID 0x20000e05
# For work-area we use beginning of OCRAM, since BL702L have only ITCM, which can be taken
# by L1 cache and XIP during runtime.
set WORKAREAADDR 0x42020000
set WORKAREASIZE 0x10000
source [find target/bl602_common.cfg]
# JTAG reset is broken. Read comment of bl602_sw_reset function for more information
# On BL702L, we are forcing boot into ISP mode, so chip stays in BootROM until JTAG re-attach
$_TARGETNAME configure -event reset-assert {
halt
# Restore clocks to defaults
bl602_restore_clock_defaults
# In HBN_RSV2, set HBN_RELEASE_CORE to HBN_RELEASE_CORE_FLAG (4)
# and HBN_USER_BOOT_SEL to 1 (ISP)
mww 0x4000f108 0x44000000
# Perform software reset
bl602_sw_reset
# Reset HBN_RSV2 so BootROM will not force ISP mode again
mww 0x4000f108 0x00000000
}