target/espressif: add application tracing functionality over JTAG
This feature allows to transfer arbitrary data between host and ESP32 via JTAG. The main use cases: 1- Collecting application specific data 2- Lightweight logging to the host 3- System behaviour analysis with SEGGER SystemView 4- Source code coverage Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I95dee00ac22891fa326915a3fcac3c088cbb2afc Reviewed-on: https://review.openocd.org/c/openocd/+/7163 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Erhan Kurubas
Antonio Borneo
parent
0384fe5d59
commit
8d1dcf293a
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@ -11137,6 +11137,46 @@ Stop current trace as started by the tracestart command.
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Dump trace memory to a file.
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@end deffn
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@section Espressif Specific Commands
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@deffn {Command} {esp apptrace} (start <destination> [<poll_period> [<trace_size> [<stop_tmo> [<wait4halt> [<skip_size>]]]]])
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Starts
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@uref{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#application-level-tracing-library, application level tracing}.
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Data will be stored to specified destination. Available destinations are:
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@itemize @bullet
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@item @code{file://<outfile>} - Save trace logs into file.
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@item @code{tcp://<host>:<port>} - Send trace logs to tcp port on specified host. OpenOCD will act as a tcp client.
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@item @code{con:} - Print trace logs to the stdout.
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@end itemize
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Other parameters will be same for each destination.
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@itemize @bullet
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@item @code{poll_period} - trace data polling period in ms.
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@item @code{trace_size} - maximum trace data size.
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Tracing will be stopped automatically when that amount is reached.
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Use "-1" to disable the limitation.
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@item @code{stop_tmo} - Data reception timeout in ms.
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Tracing will be stopped automatically when no data is received within that period.
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@item @code{wait4halt} - if non-zero then wait for target to be halted before tracing start.
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@item @code{skip_size} - amount of tracing data to be skipped before writing it to destination.
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@end itemize
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@end deffn
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@deffn {Command} {esp apptrace} (stop)
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Stops tracing started with above command.
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@end deffn
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@deffn {Command} {esp apptrace} (status)
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Requests ongoing tracing status.
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@end deffn
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@deffn {Command} {esp apptrace} (dump file://<outfile>)
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Dumps tracing data from target buffer. It can be useful to dump the latest data
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buffered on target for post-mortem analysis. For example when target starts tracing automatically
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w/o OpenOCD command and keeps only the latest data window which fit into the buffer.
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@uref{https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/app_trace.html#application-level-tracing-library, application level tracing}.
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Data will be stored to specified destination.
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@end deffn
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@anchor{softwaredebugmessagesandtracing}
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@section Software Debug Messages and Tracing
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@cindex Linux-ARM DCC support
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@ -8,6 +8,10 @@ noinst_LTLIBRARIES += %D%/libespressif.la
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%D%/esp_xtensa_smp.h \
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%D%/esp_xtensa_semihosting.c \
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%D%/esp_xtensa_semihosting.h \
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%D%/esp_xtensa_apptrace.c \
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%D%/esp_xtensa_apptrace.h \
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%D%/esp32_apptrace.c \
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%D%/esp32_apptrace.h \
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%D%/esp32.c \
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%D%/esp32s2.c \
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%D%/esp32s3.c \
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@ -440,6 +440,11 @@ static const struct command_registration esp32_command_handlers[] = {
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{
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.chain = esp_xtensa_smp_command_handlers,
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},
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{
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.name = "esp",
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.usage = "",
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.chain = esp32_apptrace_command_handlers,
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},
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{
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.name = "esp32",
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.usage = "",
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,126 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* ESP32 application trace module *
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* Copyright (C) 2017-2019 Espressif Systems Ltd. *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_ESP32_APPTRACE_H
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#define OPENOCD_TARGET_ESP32_APPTRACE_H
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#include <helper/command.h>
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#include <helper/time_support.h>
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#include <target/target.h>
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#define ESP32_APPTRACE_MAX_CORES_NUM 2
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struct esp32_apptrace_hw {
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uint32_t max_block_id;
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uint32_t (*max_block_size_get)(struct target *target);
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int (*status_reg_read)(struct target *target, uint32_t *stat);
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int (*ctrl_reg_write)(struct target *target,
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uint32_t block_id,
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uint32_t len,
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bool conn,
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bool data);
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int (*ctrl_reg_read)(struct target *target,
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uint32_t *block_id,
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uint32_t *len,
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bool *conn);
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int (*data_len_read)(struct target *target,
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uint32_t *block_id,
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uint32_t *len);
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int (*data_read)(struct target *target,
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uint32_t size,
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uint8_t *buffer,
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uint32_t block_id,
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bool ack);
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uint32_t (*usr_block_max_size_get)(struct target *target);
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int (*buffs_write)(struct target *target,
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uint32_t bufs_num,
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uint32_t buf_sz[],
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const uint8_t *bufs[],
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uint32_t block_id,
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bool ack,
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bool data);
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int (*leave_trace_crit_section_start)(struct target *target);
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int (*leave_trace_crit_section_stop)(struct target *target);
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};
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struct esp_apptrace_host2target_hdr {
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uint16_t block_sz;
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};
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struct esp32_apptrace_dest {
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void *priv;
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int (*write)(void *priv, uint8_t *data, int size);
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int (*clean)(void *priv);
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bool log_progress;
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};
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struct esp32_apptrace_format {
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uint32_t hdr_sz;
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int (*core_id_get)(struct target *target, uint8_t *hdr_buf);
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uint32_t (*usr_block_len_get)(struct target *target, uint8_t *hdr_buf, uint32_t *wr_len);
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};
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struct esp32_apptrace_cmd_stats {
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uint32_t incompl_blocks;
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uint32_t lost_bytes;
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float min_blk_read_time;
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float max_blk_read_time;
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float min_blk_proc_time;
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float max_blk_proc_time;
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};
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struct esp32_apptrace_cmd_ctx {
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volatile int running;
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int mode;
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/* TODO: use subtargets from target arch info */
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struct target *cpus[ESP32_APPTRACE_MAX_CORES_NUM];
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/* TODO: use cores num from target */
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unsigned int cores_num;
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const struct esp32_apptrace_hw *hw;
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enum target_state target_state;
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uint32_t last_blk_id;
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struct list_head free_trace_blocks;
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struct list_head ready_trace_blocks;
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uint32_t max_trace_block_sz;
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struct esp32_apptrace_format trace_format;
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int (*process_data)(struct esp32_apptrace_cmd_ctx *ctx, unsigned int core_id, uint8_t *data, uint32_t data_len);
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void (*auto_clean)(struct esp32_apptrace_cmd_ctx *ctx);
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uint32_t tot_len;
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uint32_t raw_tot_len;
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float stop_tmo;
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struct esp32_apptrace_cmd_stats stats;
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struct duration read_time;
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struct duration idle_time;
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void *cmd_priv;
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struct target *target;
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struct command_invocation *cmd;
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};
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struct esp32_apptrace_cmd_data {
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struct esp32_apptrace_dest data_dest;
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uint32_t poll_period;
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uint32_t max_len;
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uint32_t skip_len;
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bool wait4halt;
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};
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int esp32_apptrace_cmd_ctx_init(struct esp32_apptrace_cmd_ctx *cmd_ctx, struct command_invocation *cmd, int mode);
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int esp32_apptrace_cmd_ctx_cleanup(struct esp32_apptrace_cmd_ctx *cmd_ctx);
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void esp32_apptrace_cmd_args_parse(struct esp32_apptrace_cmd_ctx *cmd_ctx,
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struct esp32_apptrace_cmd_data *cmd_data,
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const char **argv,
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int argc);
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int esp32_apptrace_dest_init(struct esp32_apptrace_dest dest[], const char *dest_paths[], unsigned int max_dests);
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int esp32_apptrace_dest_cleanup(struct esp32_apptrace_dest dest[], unsigned int max_dests);
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int esp_apptrace_usr_block_write(const struct esp32_apptrace_hw *hw, struct target *target,
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uint32_t block_id,
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const uint8_t *data,
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uint32_t size);
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extern const struct command_registration esp32_apptrace_command_handlers[];
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#endif /* OPENOCD_TARGET_ESP32_APPTRACE_H */
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@ -496,6 +496,11 @@ static const struct command_registration esp32s2_command_handlers[] = {
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{
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.chain = xtensa_command_handlers,
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},
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{
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.name = "esp",
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.usage = "",
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.chain = esp32_apptrace_command_handlers,
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},
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{
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.name = "arm",
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.mode = COMMAND_ANY,
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@ -364,6 +364,11 @@ static const struct command_registration esp32s3_command_handlers[] = {
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.usage = "",
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.chain = esp_xtensa_smp_command_handlers,
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},
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{
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.name = "esp",
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.usage = "",
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.chain = esp32_apptrace_command_handlers,
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},
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{
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.name = "esp32",
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.usage = "",
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@ -12,6 +12,7 @@
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#include <stdbool.h>
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#include <stdint.h>
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#include <target/smp.h>
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#include "esp_xtensa_apptrace.h"
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#include <target/register.h>
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#include "esp_xtensa.h"
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#include "esp_semihosting.h"
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@ -25,6 +26,7 @@ int esp_xtensa_init_arch_info(struct target *target,
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if (ret != ERROR_OK)
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return ret;
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esp_xtensa->semihost.ops = (struct esp_semihost_ops *)semihost_ops;
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esp_xtensa->apptrace.hw = &esp_xtensa_apptrace_hw;
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return ERROR_OK;
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}
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@ -12,10 +12,12 @@
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#include <target/xtensa/xtensa.h>
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#include "esp_xtensa.h"
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#include "esp_semihosting.h"
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#include "esp_xtensa_apptrace.h"
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struct esp_xtensa_common {
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struct xtensa xtensa; /* must be the first element */
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struct esp_semihost_data semihost;
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struct esp_xtensa_apptrace_info apptrace;
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};
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static inline struct esp_xtensa_common *target_to_esp_xtensa(struct target *target)
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@ -0,0 +1,497 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/***************************************************************************
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* Xtensa application tracing module for OpenOCD *
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* Copyright (C) 2017 Espressif Systems Ltd. *
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***************************************************************************/
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/*
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How it works?
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https://github.com/espressif/esp-idf/blob/master/components/app_trace/port/xtensa/port.c#L8
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <helper/align.h>
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#include <target/xtensa/xtensa.h>
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#include <target/xtensa/xtensa_debug_module.h>
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#include "esp_xtensa_apptrace.h"
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/* TRAX is disabled, so we use its registers for our own purposes
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* | 31..XXXXXX..24 | 23 .(host_connect). 23 | 22 .(host_data). 22| 21..(block_id)..15 | 14..(block_len)..0 |
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*/
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#define XTENSA_APPTRACE_CTRL_REG XDMREG_DELAYCNT
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#define XTENSA_APPTRACE_BLOCK_ID_MSK 0x7FUL
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#define XTENSA_APPTRACE_BLOCK_ID_MAX XTENSA_APPTRACE_BLOCK_ID_MSK
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/* if non-zero then apptrace code entered the critical section and the value is an address of the
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* critical section's exit point */
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#define XTENSA_APPTRACE_STAT_REG XDMREG_TRIGGERPC
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#define XTENSA_APPTRACE_BLOCK_LEN_MSK 0x7FFFUL
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#define XTENSA_APPTRACE_BLOCK_LEN(_l_) ((_l_) & XTENSA_APPTRACE_BLOCK_LEN_MSK)
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#define XTENSA_APPTRACE_BLOCK_LEN_GET(_v_) ((_v_) & XTENSA_APPTRACE_BLOCK_LEN_MSK)
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#define XTENSA_APPTRACE_BLOCK_ID(_id_) (((_id_) & XTENSA_APPTRACE_BLOCK_ID_MSK) << 15)
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#define XTENSA_APPTRACE_BLOCK_ID_GET(_v_) (((_v_) >> 15) & XTENSA_APPTRACE_BLOCK_ID_MSK)
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#define XTENSA_APPTRACE_HOST_DATA BIT(22)
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#define XTENSA_APPTRACE_HOST_CONNECT BIT(23)
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static int esp_xtensa_apptrace_leave_crit_section_start(struct target *target);
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static int esp_xtensa_apptrace_leave_crit_section_stop(struct target *target);
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static int esp_xtensa_apptrace_buffs_write(struct target *target,
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uint32_t bufs_num,
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uint32_t buf_sz[],
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const uint8_t *bufs[],
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uint32_t block_id,
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bool ack,
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bool data);
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struct esp32_apptrace_hw esp_xtensa_apptrace_hw = {
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.max_block_id = XTENSA_APPTRACE_BLOCK_ID_MAX,
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.max_block_size_get = esp_xtensa_apptrace_block_max_size_get,
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.status_reg_read = esp_xtensa_apptrace_status_reg_read,
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.ctrl_reg_write = esp_xtensa_apptrace_ctrl_reg_write,
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.ctrl_reg_read = esp_xtensa_apptrace_ctrl_reg_read,
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.data_len_read = esp_xtensa_apptrace_data_len_read,
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.data_read = esp_xtensa_apptrace_data_read,
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.usr_block_max_size_get = esp_xtensa_apptrace_usr_block_max_size_get,
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.buffs_write = esp_xtensa_apptrace_buffs_write,
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.leave_trace_crit_section_start = esp_xtensa_apptrace_leave_crit_section_start,
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.leave_trace_crit_section_stop = esp_xtensa_apptrace_leave_crit_section_stop,
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};
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uint32_t esp_xtensa_apptrace_block_max_size_get(struct target *target)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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struct xtensa_trace_status trace_status;
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struct xtensa_trace_config trace_config;
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uint32_t max_trace_block_sz;
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int res = xtensa_dm_trace_status_read(&xtensa->dbg_mod, &trace_status);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to read TRAX status (%d)!", res);
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return 0;
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}
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max_trace_block_sz = BIT(((trace_status.stat >> 8) & 0x1f) - 2) * 4;
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res = xtensa_dm_trace_config_read(&xtensa->dbg_mod, &trace_config);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to read TRAX config (%d)!", res);
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return 0;
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}
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LOG_DEBUG("ctrl=0x%" PRIx32 " memadrstart=0x%" PRIx32 " memadrend=0x%" PRIx32 " traxadr=0x%" PRIx32,
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trace_config.ctrl,
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trace_config.memaddr_start,
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trace_config.memaddr_end,
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trace_config.addr);
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return max_trace_block_sz;
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}
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uint32_t esp_xtensa_apptrace_usr_block_max_size_get(struct target *target)
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{
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return esp_xtensa_apptrace_block_max_size_get(target) - sizeof(struct esp_apptrace_host2target_hdr);
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}
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int esp_xtensa_apptrace_data_len_read(struct target *target,
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uint32_t *block_id,
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uint32_t *len)
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{
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return esp_xtensa_apptrace_ctrl_reg_read(target, block_id, len, NULL);
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}
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int esp_xtensa_apptrace_usr_block_write(struct target *target,
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uint32_t block_id,
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const uint8_t *data,
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uint32_t size)
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{
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return esp_apptrace_usr_block_write(&esp_xtensa_apptrace_hw, target, block_id, data, size);
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}
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static int esp_xtensa_apptrace_data_reverse_read(struct xtensa *xtensa,
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uint32_t size,
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uint8_t *buffer,
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uint8_t *unal_bytes)
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{
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int res = 0;
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uint32_t rd_sz = ALIGN_UP(size, 4);
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res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, (xtensa->core_config->trace.mem_sz - rd_sz) / 4);
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if (res != ERROR_OK)
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return res;
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if (!IS_ALIGNED(size, 4)) {
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res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, unal_bytes);
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if (res != ERROR_OK)
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return res;
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}
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for (unsigned int i = size / 4; i != 0; i--) {
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res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, &buffer[(i - 1) * 4]);
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if (res != ERROR_OK)
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return res;
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}
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return ERROR_OK;
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}
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static int esp_xtensa_apptrace_data_normal_read(struct xtensa *xtensa,
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uint32_t size,
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uint8_t *buffer,
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uint8_t *unal_bytes)
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{
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int res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, 0);
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if (res != ERROR_OK)
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return res;
|
||||
for (unsigned int i = 0; i < size / 4; i++) {
|
||||
res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, &buffer[i * 4]);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
}
|
||||
if (!IS_ALIGNED(size, 4)) {
|
||||
res = xtensa_queue_dbg_reg_read(xtensa, XDMREG_TRAXDATA, unal_bytes);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
}
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int esp_xtensa_apptrace_data_read(struct target *target,
|
||||
uint32_t size,
|
||||
uint8_t *buffer,
|
||||
uint32_t block_id,
|
||||
bool ack)
|
||||
{
|
||||
struct xtensa *xtensa = target_to_xtensa(target);
|
||||
int res;
|
||||
uint32_t tmp = XTENSA_APPTRACE_HOST_CONNECT | XTENSA_APPTRACE_BLOCK_ID(block_id) |
|
||||
XTENSA_APPTRACE_BLOCK_LEN(0);
|
||||
uint8_t unal_bytes[4];
|
||||
|
||||
LOG_DEBUG("Read data on target (%s)", target_name(target));
|
||||
if (xtensa->core_config->trace.reversed_mem_access)
|
||||
res = esp_xtensa_apptrace_data_reverse_read(xtensa, size, buffer, unal_bytes);
|
||||
else
|
||||
res = esp_xtensa_apptrace_data_normal_read(xtensa, size, buffer, unal_bytes);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
if (ack) {
|
||||
LOG_DEBUG("Ack block %" PRIu32 " target (%s)!", block_id, target_name(target));
|
||||
res = xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
}
|
||||
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
|
||||
res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
|
||||
if (res != ERROR_OK) {
|
||||
LOG_ERROR("Failed to exec JTAG queue!");
|
||||
return res;
|
||||
}
|
||||
if (!IS_ALIGNED(size, 4)) {
|
||||
/* copy the last unaligned bytes */
|
||||
memcpy(buffer + ALIGN_DOWN(size, 4), unal_bytes, size & 0x3UL);
|
||||
}
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int esp_xtensa_apptrace_ctrl_reg_write(struct target *target,
|
||||
uint32_t block_id,
|
||||
uint32_t len,
|
||||
bool conn,
|
||||
bool data)
|
||||
{
|
||||
struct xtensa *xtensa = target_to_xtensa(target);
|
||||
uint32_t tmp = (conn ? XTENSA_APPTRACE_HOST_CONNECT : 0) |
|
||||
(data ? XTENSA_APPTRACE_HOST_DATA : 0) | XTENSA_APPTRACE_BLOCK_ID(block_id) |
|
||||
XTENSA_APPTRACE_BLOCK_LEN(len);
|
||||
|
||||
xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp);
|
||||
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
|
||||
int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
|
||||
if (res != ERROR_OK) {
|
||||
LOG_ERROR("Failed to exec JTAG queue!");
|
||||
return res;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int esp_xtensa_apptrace_ctrl_reg_read(struct target *target,
|
||||
uint32_t *block_id,
|
||||
uint32_t *len,
|
||||
bool *conn)
|
||||
{
|
||||
struct xtensa *xtensa = target_to_xtensa(target);
|
||||
uint8_t tmp[4];
|
||||
|
||||
xtensa_queue_dbg_reg_read(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp);
|
||||
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
|
||||
int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
uint32_t val = target_buffer_get_u32(target, tmp);
|
||||
if (block_id)
|
||||
*block_id = XTENSA_APPTRACE_BLOCK_ID_GET(val);
|
||||
if (len)
|
||||
*len = XTENSA_APPTRACE_BLOCK_LEN_GET(val);
|
||||
if (conn)
|
||||
*conn = val & XTENSA_APPTRACE_HOST_CONNECT;
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int esp_xtensa_apptrace_status_reg_read(struct target *target, uint32_t *stat)
|
||||
{
|
||||
struct xtensa *xtensa = target_to_xtensa(target);
|
||||
uint8_t tmp[4];
|
||||
|
||||
xtensa_queue_dbg_reg_read(xtensa, XTENSA_APPTRACE_STAT_REG, tmp);
|
||||
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
|
||||
int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
|
||||
if (res != ERROR_OK) {
|
||||
LOG_ERROR("Failed to exec JTAG queue!");
|
||||
return res;
|
||||
}
|
||||
*stat = buf_get_u32(tmp, 0, 32);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int esp_xtensa_apptrace_status_reg_write(struct target *target, uint32_t stat)
|
||||
{
|
||||
struct xtensa *xtensa = target_to_xtensa(target);
|
||||
|
||||
xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_STAT_REG, stat);
|
||||
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
|
||||
int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
|
||||
if (res != ERROR_OK) {
|
||||
LOG_ERROR("Failed to exec JTAG queue!");
|
||||
return res;
|
||||
}
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int esp_xtensa_swdbg_activate(struct target *target, int enab)
|
||||
{
|
||||
struct xtensa *xtensa = target_to_xtensa(target);
|
||||
|
||||
xtensa_queue_dbg_reg_write(xtensa, enab ? XDMREG_DCRSET : XDMREG_DCRCLR, OCDDCR_DEBUGSWACTIVE);
|
||||
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
|
||||
int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
|
||||
if (res != ERROR_OK) {
|
||||
LOG_ERROR("%s: writing DCR failed!", target->cmd_name);
|
||||
return res;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int esp_xtensa_apptrace_leave_crit_section_start(struct target *target)
|
||||
{
|
||||
/* TODO: not sure that we need this, but it seems that we fail to leave tracing critical
|
||||
*section w/o this */
|
||||
int res = esp_xtensa_swdbg_activate(target, 1 /*enable*/);
|
||||
if (res != ERROR_OK) {
|
||||
LOG_ERROR("Failed to activate SW debug (%d)!", res);
|
||||
return res;
|
||||
}
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int esp_xtensa_apptrace_leave_crit_section_stop(struct target *target)
|
||||
{
|
||||
int res = esp_xtensa_swdbg_activate(target, 0 /*disable*/);
|
||||
if (res != ERROR_OK) {
|
||||
LOG_ERROR("Failed to activate SW debug (%d)!", res);
|
||||
return res;
|
||||
}
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int esp_xtensa_apptrace_queue_reverse_write(struct target *target, uint32_t bufs_num,
|
||||
uint32_t buf_sz[], const uint8_t *bufs[])
|
||||
{
|
||||
int res = ERROR_OK;
|
||||
uint32_t cached_bytes = 0, total_sz = 0;
|
||||
uint8_t cached_data8[sizeof(uint32_t)] = { 0 };
|
||||
uint32_t cached_data32 = 0;
|
||||
|
||||
struct xtensa *xtensa = target_to_xtensa(target);
|
||||
|
||||
for (uint32_t i = 0; i < bufs_num; i++)
|
||||
total_sz += buf_sz[i];
|
||||
if (!IS_ALIGNED(total_sz, 4)) {
|
||||
cached_bytes = sizeof(uint32_t) - (total_sz & 0x3UL);
|
||||
total_sz = ALIGN_UP(total_sz, 4);
|
||||
}
|
||||
xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, (xtensa->core_config->trace.mem_sz - total_sz) / 4);
|
||||
for (uint32_t i = bufs_num; i > 0; i--) {
|
||||
uint32_t bsz = buf_sz[i - 1];
|
||||
const uint8_t *cur_buf = &bufs[i - 1][bsz];
|
||||
uint32_t bytes_to_cache;
|
||||
/* if there are cached bytes from the previous buffer, combine them with the last
|
||||
* from the current buffer */
|
||||
if (cached_bytes) {
|
||||
if ((cached_bytes + bsz) < sizeof(uint32_t))
|
||||
bytes_to_cache = bsz;
|
||||
else
|
||||
bytes_to_cache = sizeof(uint32_t) - cached_bytes;
|
||||
memcpy(&cached_data8[sizeof(uint32_t) - cached_bytes - bytes_to_cache],
|
||||
cur_buf - bytes_to_cache,
|
||||
bytes_to_cache);
|
||||
cached_data32 = target_buffer_get_u32(target, cached_data8);
|
||||
cached_bytes += bytes_to_cache;
|
||||
if (cached_bytes < sizeof(uint32_t))
|
||||
continue;
|
||||
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
bsz -= bytes_to_cache;
|
||||
cur_buf -= bytes_to_cache;
|
||||
memset(cached_data8, 0x00, sizeof(cached_data8));
|
||||
cached_bytes = 0;
|
||||
}
|
||||
/* write full dwords */
|
||||
for (unsigned int k = bsz; k >= sizeof(uint32_t); k -= sizeof(uint32_t)) {
|
||||
uint32_t temp = target_buffer_get_u32(target, cur_buf - sizeof(uint32_t));
|
||||
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, temp);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
cur_buf -= sizeof(uint32_t);
|
||||
}
|
||||
/* if there are bytes to be cached (1..3) */
|
||||
bytes_to_cache = bsz & 0x3UL;
|
||||
if (bytes_to_cache > 0) {
|
||||
if (bytes_to_cache + cached_bytes >= sizeof(uint32_t)) {
|
||||
/* filling the cache buffer from the end to beginning */
|
||||
uint32_t to_copy = sizeof(uint32_t) - cached_bytes;
|
||||
memcpy(&cached_data8[0], cur_buf - to_copy, to_copy);
|
||||
cached_data32 = target_buffer_get_u32(target, cached_data8);
|
||||
/* write full word of cached bytes */
|
||||
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
/* cache remaining bytes */
|
||||
memset(cached_data8, 0x00, sizeof(cached_data8));
|
||||
cur_buf -= to_copy;
|
||||
to_copy = bytes_to_cache + cached_bytes - sizeof(uint32_t);
|
||||
memcpy(&cached_data8[sizeof(uint32_t) - to_copy], cur_buf - to_copy, to_copy);
|
||||
cached_bytes = to_copy;
|
||||
} else {
|
||||
/* filling the cache buffer from the end to beginning */
|
||||
memcpy(&cached_data8[sizeof(uint32_t) - cached_bytes - bytes_to_cache],
|
||||
cur_buf - bytes_to_cache,
|
||||
bytes_to_cache);
|
||||
cached_bytes += bytes_to_cache;
|
||||
}
|
||||
}
|
||||
}
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int esp_xtensa_apptrace_queue_normal_write(struct target *target, uint32_t bufs_num,
|
||||
uint32_t buf_sz[], const uint8_t *bufs[])
|
||||
{
|
||||
int res = ERROR_OK;
|
||||
uint32_t cached_bytes = 0;
|
||||
uint8_t cached_data8[4] = { 0 };
|
||||
uint32_t cached_data32 = 0;
|
||||
|
||||
struct xtensa *xtensa = target_to_xtensa(target);
|
||||
|
||||
/* | 1 | 2 | 1 | 2 | 4 |.......|
|
||||
* | 4 | 4 | 4 | */
|
||||
xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXADDR, 0);
|
||||
for (unsigned int i = 0; i < bufs_num; i++) {
|
||||
uint32_t bsz = buf_sz[i];
|
||||
const uint8_t *cur_buf = bufs[i];
|
||||
uint32_t bytes_to_cache;
|
||||
/* if there are cached bytes from the previous buffer, combine them with the last
|
||||
* from the current buffer */
|
||||
if (cached_bytes) {
|
||||
if ((cached_bytes + bsz) < sizeof(uint32_t))
|
||||
bytes_to_cache = bsz;
|
||||
else
|
||||
bytes_to_cache = sizeof(uint32_t) - cached_bytes;
|
||||
memcpy(&cached_data8[cached_bytes], cur_buf, bytes_to_cache);
|
||||
cached_bytes += bytes_to_cache;
|
||||
if (cached_bytes < sizeof(uint32_t))
|
||||
continue;
|
||||
cached_data32 = target_buffer_get_u32(target, cached_data8);
|
||||
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
bsz -= bytes_to_cache;
|
||||
cur_buf += bytes_to_cache;
|
||||
memset(cached_data8, 0x00, sizeof(cached_data8));
|
||||
cached_bytes = 0;
|
||||
}
|
||||
/* write full dwords */
|
||||
for (unsigned int k = 0; (k + sizeof(uint32_t)) <= bsz; k += sizeof(uint32_t)) {
|
||||
uint32_t temp = target_buffer_get_u32(target, cur_buf);
|
||||
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, temp);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
cur_buf += sizeof(uint32_t);
|
||||
}
|
||||
/* if there are bytes to be cached (1..3) */
|
||||
bytes_to_cache = bsz & 0x3UL;
|
||||
if (bytes_to_cache > 0) {
|
||||
if (bytes_to_cache + cached_bytes >= sizeof(uint32_t)) {
|
||||
memcpy(&cached_data8[0], cur_buf, sizeof(uint32_t) - cached_bytes);
|
||||
cached_data32 = target_buffer_get_u32(target, cached_data8);
|
||||
/* write full word of cached bytes */
|
||||
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
/* cache remaining bytes */
|
||||
memset(cached_data8, 0x00, sizeof(cached_data8));
|
||||
cur_buf += sizeof(uint32_t) - cached_bytes;
|
||||
cached_bytes = bytes_to_cache + cached_bytes - sizeof(uint32_t);
|
||||
memcpy(&cached_data8[0], cur_buf, cached_bytes);
|
||||
} else {
|
||||
memcpy(&cached_data8[cached_bytes], cur_buf, bytes_to_cache);
|
||||
cached_bytes += bytes_to_cache;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (cached_bytes) {
|
||||
/* write remaining cached bytes */
|
||||
cached_data32 = target_buffer_get_u32(target, cached_data8);
|
||||
res = xtensa_queue_dbg_reg_write(xtensa, XDMREG_TRAXDATA, cached_data32);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
}
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int esp_xtensa_apptrace_buffs_write(struct target *target,
|
||||
uint32_t bufs_num,
|
||||
uint32_t buf_sz[],
|
||||
const uint8_t *bufs[],
|
||||
uint32_t block_id,
|
||||
bool ack,
|
||||
bool data)
|
||||
{
|
||||
struct xtensa *xtensa = target_to_xtensa(target);
|
||||
int res = ERROR_OK;
|
||||
uint32_t tmp = XTENSA_APPTRACE_HOST_CONNECT |
|
||||
(data ? XTENSA_APPTRACE_HOST_DATA : 0) | XTENSA_APPTRACE_BLOCK_ID(block_id) |
|
||||
XTENSA_APPTRACE_BLOCK_LEN(0);
|
||||
|
||||
if (xtensa->core_config->trace.reversed_mem_access)
|
||||
res = esp_xtensa_apptrace_queue_reverse_write(target, bufs_num, buf_sz, bufs);
|
||||
else
|
||||
res = esp_xtensa_apptrace_queue_normal_write(target, bufs_num, buf_sz, bufs);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
if (ack) {
|
||||
LOG_DEBUG("Ack block %" PRId32 " on target (%s)!", block_id, target_name(target));
|
||||
res = xtensa_queue_dbg_reg_write(xtensa, XTENSA_APPTRACE_CTRL_REG, tmp);
|
||||
if (res != ERROR_OK)
|
||||
return res;
|
||||
}
|
||||
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
|
||||
res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
|
||||
if (res != ERROR_OK) {
|
||||
LOG_ERROR("Failed to exec JTAG queue!");
|
||||
return res;
|
||||
}
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
/***************************************************************************
|
||||
* Xtensa application tracing module for OpenOCD *
|
||||
* Copyright (C) 2017 Espressif Systems Ltd. *
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef OPENOCD_TARGET_ESP_XTENSA_APPTRACE_H
|
||||
#define OPENOCD_TARGET_ESP_XTENSA_APPTRACE_H
|
||||
|
||||
#include "esp32_apptrace.h"
|
||||
|
||||
struct esp_xtensa_apptrace_info {
|
||||
const struct esp32_apptrace_hw *hw;
|
||||
};
|
||||
|
||||
extern struct esp32_apptrace_hw esp_xtensa_apptrace_hw;
|
||||
|
||||
int esp_xtensa_apptrace_data_len_read(struct target *target, uint32_t *block_id, uint32_t *len);
|
||||
int esp_xtensa_apptrace_data_read(struct target *target,
|
||||
uint32_t size,
|
||||
uint8_t *buffer,
|
||||
uint32_t block_id,
|
||||
bool ack);
|
||||
int esp_xtensa_apptrace_ctrl_reg_read(struct target *target, uint32_t *block_id, uint32_t *len, bool *conn);
|
||||
int esp_xtensa_apptrace_ctrl_reg_write(struct target *target,
|
||||
uint32_t block_id,
|
||||
uint32_t len,
|
||||
bool conn,
|
||||
bool data);
|
||||
int esp_xtensa_apptrace_status_reg_write(struct target *target, uint32_t stat);
|
||||
int esp_xtensa_apptrace_status_reg_read(struct target *target, uint32_t *stat);
|
||||
uint32_t esp_xtensa_apptrace_block_max_size_get(struct target *target);
|
||||
uint32_t esp_xtensa_apptrace_usr_block_max_size_get(struct target *target);
|
||||
int esp_xtensa_apptrace_usr_block_write(struct target *target, uint32_t block_id, const uint8_t *data, uint32_t size);
|
||||
|
||||
#endif /* OPENOCD_TARGET_ESP_XTENSA_APPTRACE_H */
|
||||
Loading…
Reference in New Issue