Merge pull request #843 from riscv/hypervisor_translate
target/riscv: Support hypervisor address translation
This commit is contained in:
Tim Newsome
GitHub
commit
80d529cad3
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@ -98,6 +98,9 @@ enum gdb_regno {
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GDB_REGNO_MEPC = CSR_MEPC + GDB_REGNO_CSR0,
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GDB_REGNO_MCAUSE = CSR_MCAUSE + GDB_REGNO_CSR0,
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GDB_REGNO_SATP = CSR_SATP + GDB_REGNO_CSR0,
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GDB_REGNO_VSATP = CSR_VSATP + GDB_REGNO_CSR0,
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GDB_REGNO_HGATP = CSR_HGATP + GDB_REGNO_CSR0,
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GDB_REGNO_HSTATUS = CSR_HSTATUS + GDB_REGNO_CSR0,
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GDB_REGNO_MTOPI = CSR_MTOPI + GDB_REGNO_CSR0,
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GDB_REGNO_MTOPEI = CSR_MTOPEI + GDB_REGNO_CSR0,
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GDB_REGNO_CSR4095 = GDB_REGNO_CSR0 + 4095,
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@ -159,6 +159,19 @@ static const virt2phys_info_t sv32 = {
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.pa_ppn_mask = {0x3ff, 0xfff},
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};
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static const virt2phys_info_t sv32x4 = {
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.name = "Sv32x4",
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.va_bits = 34,
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.level = 2,
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.pte_shift = 2,
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.vpn_shift = {12, 22},
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.vpn_mask = {0x3ff, 0xfff},
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.pte_ppn_shift = {10, 20},
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.pte_ppn_mask = {0x3ff, 0xfff},
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.pa_ppn_shift = {12, 22},
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.pa_ppn_mask = {0x3ff, 0xfff},
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};
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static const virt2phys_info_t sv39 = {
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.name = "Sv39",
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.va_bits = 39,
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@ -172,6 +185,19 @@ static const virt2phys_info_t sv39 = {
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.pa_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
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};
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static const virt2phys_info_t sv39x4 = {
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.name = "Sv39x4",
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.va_bits = 41,
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.level = 3,
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.pte_shift = 3,
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.vpn_shift = {12, 21, 30},
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.vpn_mask = {0x1ff, 0x1ff, 0x7ff},
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.pte_ppn_shift = {10, 19, 28},
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.pte_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
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.pa_ppn_shift = {12, 21, 30},
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.pa_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
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};
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static const virt2phys_info_t sv48 = {
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.name = "Sv48",
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.va_bits = 48,
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@ -185,6 +211,19 @@ static const virt2phys_info_t sv48 = {
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.pa_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
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};
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static const virt2phys_info_t sv48x4 = {
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.name = "Sv48x4",
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.va_bits = 50,
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.level = 4,
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.pte_shift = 3,
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.vpn_shift = {12, 21, 30, 39},
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.vpn_mask = {0x1ff, 0x1ff, 0x1ff, 0x7ff},
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.pte_ppn_shift = {10, 19, 28, 37},
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.pte_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
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.pa_ppn_shift = {12, 21, 30, 39},
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.pa_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x7ffff},
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};
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static enum riscv_halt_reason riscv_halt_reason(struct target *target);
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static void riscv_info_init(struct target *target, struct riscv_info *r);
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static void riscv_invalidate_register_cache(struct target *target);
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@ -1871,6 +1910,31 @@ static int riscv_target_resume(struct target *target, int current,
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debug_execution, false);
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}
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static int riscv_effective_privilege_mode(struct target *target, int *v_mode, int *effective_mode)
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{
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riscv_reg_t priv;
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if (riscv_get_register(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Failed to read priv register.");
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return ERROR_FAIL;
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}
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*v_mode = get_field(priv, VIRT_PRIV_V);
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riscv_reg_t mstatus;
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if (riscv_get_register(target, &mstatus, GDB_REGNO_MSTATUS) != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Failed to read mstatus register.");
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return ERROR_FAIL;
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}
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if (get_field(mstatus, MSTATUS_MPRV))
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*effective_mode = get_field(mstatus, MSTATUS_MPP);
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else
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*effective_mode = get_field(priv, VIRT_PRIV_PRV);
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LOG_TARGET_DEBUG(target, "Effective mode=%d; v=%d", *effective_mode, *v_mode);
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return ERROR_OK;
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}
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static int riscv_mmu(struct target *target, int *enabled)
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{
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if (!riscv_enable_virt2phys) {
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@ -1885,14 +1949,63 @@ static int riscv_mmu(struct target *target, int *enabled)
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return ERROR_FAIL;
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}
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riscv_reg_t mstatus;
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if (riscv_get_register(target, &mstatus, GDB_REGNO_MSTATUS) != ERROR_OK) {
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LOG_ERROR("Failed to read mstatus register.");
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int effective_mode;
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int v_mode;
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if (riscv_effective_privilege_mode(target, &v_mode, &effective_mode) != ERROR_OK)
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return ERROR_FAIL;
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unsigned int xlen = riscv_xlen(target);
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if (v_mode) {
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/* vsatp and hgatp registers are considered active for the
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* purposes of the address-translation algorithm unless the
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* effective privilege mode is U and hstatus.HU=0. */
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if (effective_mode == PRV_U) {
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riscv_reg_t hstatus;
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if (riscv_get_register(target, &hstatus, GDB_REGNO_HSTATUS) != ERROR_OK) {
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LOG_ERROR("Failed to read hstatus register.");
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return ERROR_FAIL;
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}
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if (get_field(hstatus, HSTATUS_HU) == 0)
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/* In hypervisor mode regular satp translation
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* doesn't happen. */
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return ERROR_OK;
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}
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riscv_reg_t vsatp;
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if (riscv_get_register(target, &vsatp, GDB_REGNO_VSATP) != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Failed to read vsatp register; priv=0x%" PRIx64,
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priv);
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return ERROR_FAIL;
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}
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/* vsatp is identical to satp, so we can use the satp macros. */
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if (RISCV_SATP_MODE(xlen) != SATP_MODE_OFF) {
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LOG_TARGET_DEBUG(target, "VS-stage translation is enabled.");
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*enabled = 1;
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return ERROR_OK;
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}
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riscv_reg_t hgatp;
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if (riscv_get_register(target, &hgatp, GDB_REGNO_HGATP) != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Failed to read hgatp register; priv=0x%" PRIx64,
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priv);
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return ERROR_FAIL;
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}
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if (RISCV_HGATP_MODE(xlen) != HGATP_MODE_OFF) {
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LOG_TARGET_DEBUG(target, "G-stage address translation is enabled.");
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*enabled = 1;
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} else {
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LOG_TARGET_DEBUG(target, "No V-mode address translation enabled.");
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*enabled = 0;
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}
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return ERROR_OK;
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}
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if ((get_field(mstatus, MSTATUS_MPRV) ? get_field(mstatus, MSTATUS_MPP) : priv) == PRV_M) {
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LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%" PRIx64 ").", mstatus);
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/* Don't use MMU in explicit or effective M (machine) mode */
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if (effective_mode == PRV_M) {
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LOG_TARGET_DEBUG(target, "SATP/MMU ignored in Machine mode.");
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*enabled = 0;
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return ERROR_OK;
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}
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@ -1905,7 +2018,7 @@ static int riscv_mmu(struct target *target, int *enabled)
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return ERROR_OK;
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}
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if (get_field(satp, RISCV_SATP_MODE(riscv_xlen(target))) == SATP_MODE_OFF) {
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if (get_field(satp, RISCV_SATP_MODE(xlen)) == SATP_MODE_OFF) {
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LOG_DEBUG("MMU is disabled.");
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*enabled = 0;
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} else {
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@ -1916,44 +2029,19 @@ static int riscv_mmu(struct target *target, int *enabled)
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return ERROR_OK;
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}
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/* Translate address from virtual to physical, using info and ppn.
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* If extra_info is non-NULL, then translate page table accesses for the primary
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* translation using extra_info and extra_ppn. */
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static int riscv_address_translate(struct target *target,
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const virt2phys_info_t *info, target_addr_t ppn,
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const virt2phys_info_t *extra_info, target_addr_t extra_ppn,
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target_addr_t virtual, target_addr_t *physical)
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{
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RISCV_INFO(r);
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riscv_reg_t satp_value;
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int mode;
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uint64_t ppn_value;
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target_addr_t table_address;
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const virt2phys_info_t *info;
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uint64_t pte = 0;
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int i;
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unsigned int xlen = riscv_xlen(target);
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int result = riscv_get_register(target, &satp_value, GDB_REGNO_SATP);
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if (result != ERROR_OK)
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return result;
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unsigned xlen = riscv_xlen(target);
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mode = get_field(satp_value, RISCV_SATP_MODE(xlen));
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switch (mode) {
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case SATP_MODE_SV32:
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info = &sv32;
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break;
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case SATP_MODE_SV39:
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info = &sv39;
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break;
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case SATP_MODE_SV48:
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info = &sv48;
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break;
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case SATP_MODE_OFF:
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LOG_ERROR("No translation or protection." \
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" (satp: 0x%" PRIx64 ")", satp_value);
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return ERROR_FAIL;
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default:
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LOG_ERROR("The translation mode is not supported." \
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" (satp: 0x%" PRIx64 ")", satp_value);
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return ERROR_FAIL;
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}
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LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR "; mode=%s", virtual, info->name);
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LOG_TARGET_DEBUG(target, "mode=%s; ppn=0x%" TARGET_PRIxADDR "; virtual=0x%" TARGET_PRIxADDR,
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info->name, ppn, virtual);
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/* verify bits xlen-1:va_bits-1 are all equal */
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assert(xlen >= info->va_bits);
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@ -1965,14 +2053,21 @@ static int riscv_address_translate(struct target *target,
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return ERROR_FAIL;
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}
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ppn_value = get_field(satp_value, RISCV_SATP_PPN(xlen));
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table_address = ppn_value << RISCV_PGSHIFT;
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i = info->level - 1;
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uint64_t pte = 0;
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target_addr_t table_address = ppn << RISCV_PGSHIFT;
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int i = info->level - 1;
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while (i >= 0) {
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uint64_t vpn = virtual >> info->vpn_shift[i];
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vpn &= info->vpn_mask[i];
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target_addr_t pte_address = table_address +
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(vpn << info->pte_shift);
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target_addr_t pte_address = table_address + (vpn << info->pte_shift);
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if (extra_info) {
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/* Perform extra stage translation. */
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if (riscv_address_translate(target, extra_info, extra_ppn,
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NULL, 0, pte_address, &pte_address) != ERROR_OK)
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return ERROR_FAIL;
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}
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uint8_t buffer[8];
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assert(info->pte_shift <= 3);
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int retval = r->read_memory(target, pte_address,
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@ -1988,8 +2083,11 @@ static int riscv_address_translate(struct target *target,
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LOG_DEBUG("i=%d; PTE @0x%" TARGET_PRIxADDR " = 0x%" PRIx64, i,
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pte_address, pte);
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if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W)))
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if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
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LOG_TARGET_ERROR(target, "invalid PTE @0x%" TARGET_PRIxADDR ": 0x%" PRIx64
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"; mode=%s; i=%d", pte_address, pte, info->name, i);
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return ERROR_FAIL;
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}
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if ((pte & PTE_R) || (pte & PTE_W) || (pte & PTE_X)) /* Found leaf PTE. */
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break;
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@ -1997,8 +2095,8 @@ static int riscv_address_translate(struct target *target,
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i--;
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if (i < 0)
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break;
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ppn_value = pte >> PTE_PPN_SHIFT;
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table_address = ppn_value << RISCV_PGSHIFT;
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ppn = pte >> PTE_PPN_SHIFT;
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table_address = ppn << RISCV_PGSHIFT;
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}
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if (i < 0) {
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@ -2010,15 +2108,115 @@ static int riscv_address_translate(struct target *target,
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*physical = virtual & (((target_addr_t)1 << info->va_bits) - 1);
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while (i < info->level) {
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ppn_value = pte >> info->pte_ppn_shift[i];
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ppn_value &= info->pte_ppn_mask[i];
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ppn = pte >> info->pte_ppn_shift[i];
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ppn &= info->pte_ppn_mask[i];
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*physical &= ~(((target_addr_t)info->pa_ppn_mask[i]) <<
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info->pa_ppn_shift[i]);
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*physical |= (ppn_value << info->pa_ppn_shift[i]);
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*physical |= (ppn << info->pa_ppn_shift[i]);
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i++;
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}
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LOG_DEBUG("0x%" TARGET_PRIxADDR " -> 0x%" TARGET_PRIxADDR, virtual,
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*physical);
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LOG_TARGET_DEBUG(target, "mode=%s; 0x%" TARGET_PRIxADDR " -> 0x%" TARGET_PRIxADDR,
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info->name, virtual, *physical);
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return ERROR_OK;
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}
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/* Virtual to physical translation for hypervisor mode. */
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static int riscv_virt2phys_v(struct target *target, target_addr_t virtual, target_addr_t *physical)
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{
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riscv_reg_t vsatp;
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if (riscv_get_register(target, &vsatp, GDB_REGNO_VSATP) != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Failed to read vsatp register.");
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return ERROR_FAIL;
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}
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/* vsatp is identical to satp, so we can use the satp macros. */
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unsigned int xlen = riscv_xlen(target);
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int vsatp_mode = get_field(vsatp, RISCV_SATP_MODE(xlen));
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LOG_TARGET_DEBUG(target, "VS-stage translation mode: %d", vsatp_mode);
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riscv_reg_t hgatp;
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if (riscv_get_register(target, &hgatp, GDB_REGNO_HGATP) != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Failed to read hgatp register.");
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return ERROR_FAIL;
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}
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int hgatp_mode = get_field(vsatp, RISCV_HGATP_MODE(xlen));
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LOG_TARGET_DEBUG(target, "G-stage translation mode: %d", hgatp_mode);
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const virt2phys_info_t *vsatp_info;
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/* VS-stage address translation. */
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switch (vsatp_mode) {
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case SATP_MODE_SV32:
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vsatp_info = &sv32;
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break;
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case SATP_MODE_SV39:
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vsatp_info = &sv39;
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break;
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case SATP_MODE_SV48:
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vsatp_info = &sv48;
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break;
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case SATP_MODE_OFF:
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vsatp_info = NULL;
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break;
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default:
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LOG_TARGET_ERROR(target,
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"vsatp mode %d is not supported. (vsatp: 0x%" PRIx64 ")",
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vsatp_mode, vsatp);
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return ERROR_FAIL;
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}
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const virt2phys_info_t *hgatp_info;
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/* G-stage address translation. */
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switch (hgatp_mode) {
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case HGATP_MODE_SV32X4:
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hgatp_info = &sv32x4;
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break;
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case HGATP_MODE_SV39X4:
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hgatp_info = &sv39x4;
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break;
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case HGATP_MODE_SV48X4:
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hgatp_info = &sv48x4;
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break;
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case HGATP_MODE_OFF:
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hgatp_info = NULL;
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break;
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default:
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LOG_TARGET_ERROR(target,
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"hgatp mode %d is not supported. (hgatp: 0x%" PRIx64 ")",
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hgatp_mode, hgatp);
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return ERROR_FAIL;
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}
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/* For any virtual memory access, the original virtual address is
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* converted in the first stage by VS-level address translation,
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* as controlled by the vsatp register, into a guest physical
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* address. */
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target_addr_t guest_physical;
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if (vsatp_info) {
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/* When V=1, memory accesses that would normally bypass
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* address translation are subject to G- stage address
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* translation alone. This includes memory accesses made
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* in support of VS-stage address translation, such as
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* reads and writes of VS-level page tables. */
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if (riscv_address_translate(target,
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vsatp_info, get_field(vsatp, RISCV_SATP_PPN(xlen)),
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hgatp_info, get_field(hgatp, RISCV_SATP_PPN(xlen)),
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virtual, &guest_physical) != ERROR_OK)
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return ERROR_FAIL;
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} else {
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guest_physical = virtual;
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}
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/* The guest physical address is then converted in the second
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* stage by guest physical address translation, as controlled by
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* the hgatp register, into a supervisor physical address. */
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if (hgatp_info) {
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if (riscv_address_translate(target,
|
||||
hgatp_info, get_field(hgatp, RISCV_HGATP_PPN(xlen)),
|
||||
NULL, 0,
|
||||
guest_physical, physical) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
} else {
|
||||
*physical = guest_physical;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -2026,15 +2224,53 @@ static int riscv_address_translate(struct target *target,
|
|||
static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
|
||||
{
|
||||
int enabled;
|
||||
if (riscv_mmu(target, &enabled) == ERROR_OK) {
|
||||
if (!enabled)
|
||||
return ERROR_FAIL;
|
||||
if (riscv_mmu(target, &enabled) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
if (!enabled)
|
||||
return ERROR_FAIL;
|
||||
|
||||
if (riscv_address_translate(target, virtual, physical) == ERROR_OK)
|
||||
return ERROR_OK;
|
||||
|
||||
riscv_reg_t priv;
|
||||
if (riscv_get_register(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) {
|
||||
LOG_ERROR("Failed to read priv register.");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
return ERROR_FAIL;
|
||||
if (priv & VIRT_PRIV_V)
|
||||
return riscv_virt2phys_v(target, virtual, physical);
|
||||
|
||||
riscv_reg_t satp_value;
|
||||
int result = riscv_get_register(target, &satp_value, GDB_REGNO_SATP);
|
||||
if (result != ERROR_OK)
|
||||
return result;
|
||||
|
||||
unsigned int xlen = riscv_xlen(target);
|
||||
int satp_mode = get_field(satp_value, RISCV_SATP_MODE(xlen));
|
||||
const virt2phys_info_t *satp_info;
|
||||
switch (satp_mode) {
|
||||
case SATP_MODE_SV32:
|
||||
satp_info = &sv32;
|
||||
break;
|
||||
case SATP_MODE_SV39:
|
||||
satp_info = &sv39;
|
||||
break;
|
||||
case SATP_MODE_SV48:
|
||||
satp_info = &sv48;
|
||||
break;
|
||||
case SATP_MODE_OFF:
|
||||
LOG_ERROR("No translation or protection."
|
||||
" (satp: 0x%" PRIx64 ")", satp_value);
|
||||
return ERROR_FAIL;
|
||||
default:
|
||||
LOG_ERROR("The translation mode is not supported."
|
||||
" (satp: 0x%" PRIx64 ")", satp_value);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
return riscv_address_translate(target,
|
||||
satp_info, get_field(satp_value, RISCV_SATP_PPN(xlen)),
|
||||
NULL, 0,
|
||||
virtual, physical);
|
||||
}
|
||||
|
||||
static int riscv_read_phys_memory(struct target *target, target_addr_t phys_address,
|
||||
|
|
|
|||
|
|
@ -26,6 +26,8 @@ struct riscv_program;
|
|||
|
||||
#define RISCV_SATP_MODE(xlen) ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)
|
||||
#define RISCV_SATP_PPN(xlen) ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)
|
||||
#define RISCV_HGATP_MODE(xlen) ((xlen) == 32 ? HGATP32_MODE : HGATP64_MODE)
|
||||
#define RISCV_HGATP_PPN(xlen) ((xlen) == 32 ? HGATP32_PPN : HGATP64_PPN)
|
||||
#define RISCV_PGSHIFT 12
|
||||
|
||||
# define PG_MAX_LEVEL 4
|
||||
|
|
@ -287,6 +289,7 @@ typedef struct {
|
|||
const char *name;
|
||||
int level;
|
||||
unsigned va_bits;
|
||||
/* log2(PTESIZE) */
|
||||
unsigned pte_shift;
|
||||
unsigned vpn_shift[PG_MAX_LEVEL];
|
||||
unsigned vpn_mask[PG_MAX_LEVEL];
|
||||
|
|
|
|||
Loading…
Reference in New Issue