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target/arm: rename CamelCase symbols 

No major cross dependencies, mostly changes internal to each
file/function.

Change-Id: I3f0879f0f33c6badc36a0dc60229323978a7e280
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6338
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Xiang W <wxjstz@126.com>
This commit is contained in:
Antonio Borneo 2021-04-27 15:58:26 +02:00
parent 7c38f24529
commit 67cb50e26a
24 changed files with 314 additions and 314 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

92
src/target/aarch64.c
View File

@ -1259,18 +1259,18 @@ static int aarch64_set_breakpoint(struct target *target,
bpt_value = brp_list[brp_i].value;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
(uint32_t)(bpt_value & 0xFFFFFFFF));
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
+ CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
(uint32_t)(bpt_value >> 32));
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
@ -1377,12 +1377,12 @@ static int aarch64_set_context_breakpoint(struct target *target,
brp_list[brp_i].value = (breakpoint->asid);
brp_list[brp_i].control = control;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
@ -1398,11 +1398,11 @@ static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoin
int retval = ERROR_FAIL;
int brp_1 = 0; /* holds the contextID pair */
int brp_2 = 0; /* holds the IVA pair */
uint32_t control_CTX, control_IVA;
uint8_t CTX_byte_addr_select = 0x0F;
uint8_t IVA_byte_addr_select = 0x0F;
uint8_t CTX_machmode = 0x03;
uint8_t IVA_machmode = 0x01;
uint32_t control_ctx, control_iva;
uint8_t ctx_byte_addr_select = 0x0F;
uint8_t iva_byte_addr_select = 0x0F;
uint8_t ctx_machmode = 0x03;
uint8_t iva_machmode = 0x01;
struct aarch64_common *aarch64 = target_to_aarch64(target);
struct armv8_common *armv8 = &aarch64->armv8_common;
struct aarch64_brp *brp_list = aarch64->brp_list;
@ -1434,45 +1434,45 @@ static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoin
breakpoint->set = brp_1 + 1;
breakpoint->linked_brp = brp_2;
control_CTX = ((CTX_machmode & 0x7) << 20)
control_ctx = ((ctx_machmode & 0x7) << 20)
| (brp_2 << 16)
| (0 << 14)
| (CTX_byte_addr_select << 5)
| (ctx_byte_addr_select << 5)
| (3 << 1) | 1;
brp_list[brp_1].used = 1;
brp_list[brp_1].value = (breakpoint->asid);
brp_list[brp_1].control = control_CTX;
brp_list[brp_1].control = control_ctx;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_1].BRPn,
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_1].brpn,
brp_list[brp_1].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_1].BRPn,
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_1].brpn,
brp_list[brp_1].control);
if (retval != ERROR_OK)
return retval;
control_IVA = ((IVA_machmode & 0x7) << 20)
control_iva = ((iva_machmode & 0x7) << 20)
| (brp_1 << 16)
| (1 << 13)
| (IVA_byte_addr_select << 5)
| (iva_byte_addr_select << 5)
| (3 << 1) | 1;
brp_list[brp_2].used = 1;
brp_list[brp_2].value = breakpoint->address & 0xFFFFFFFFFFFFFFFC;
brp_list[brp_2].control = control_IVA;
brp_list[brp_2].control = control_iva;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_2].BRPn,
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_2].brpn,
brp_list[brp_2].value & 0xFFFFFFFF);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_2].BRPn,
+ CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_2].brpn,
brp_list[brp_2].value >> 32);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_2].BRPn,
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_2].brpn,
brp_list[brp_2].control);
if (retval != ERROR_OK)
return retval;
@ -1506,17 +1506,17 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
(uint32_t)brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
+ CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
(uint32_t)brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
@ -1530,17 +1530,17 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
brp_list[brp_j].value = 0;
brp_list[brp_j].control = 0;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_j].BRPn,
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_j].brpn,
brp_list[brp_j].control);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_j].BRPn,
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_j].brpn,
(uint32_t)brp_list[brp_j].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_j].BRPn,
+ CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_j].brpn,
(uint32_t)brp_list[brp_j].value);
if (retval != ERROR_OK)
return retval;
@ -1561,18 +1561,18 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
+ CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].brpn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
+ CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].brpn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
+ CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].brpn,
(uint32_t)brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
@ -1735,18 +1735,18 @@ static int aarch64_set_watchpoint(struct target *target,
wp_list[wp_i].control = control;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].BRPn,
+ CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].brpn,
(uint32_t)(wp_list[wp_i].value & 0xFFFFFFFF));
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].BRPn,
+ CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].brpn,
(uint32_t)(wp_list[wp_i].value >> 32));
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].BRPn,
+ CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].brpn,
control);
if (retval != ERROR_OK)
return retval;
@ -1791,18 +1791,18 @@ static int aarch64_unset_watchpoint(struct target *target,
wp_list[wp_i].value = 0;
wp_list[wp_i].control = 0;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].BRPn,
+ CPUV8_DBG_WCR_BASE + 16 * wp_list[wp_i].brpn,
wp_list[wp_i].control);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].BRPn,
+ CPUV8_DBG_WVR_BASE + 16 * wp_list[wp_i].brpn,
wp_list[wp_i].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].BRPn,
+ CPUV8_DBG_WVR_BASE + 4 + 16 * wp_list[wp_i].brpn,
(uint32_t)wp_list[wp_i].value);
if (retval != ERROR_OK)
return retval;
@ -2656,7 +2656,7 @@ static int aarch64_examine_first(struct target *target)
aarch64->brp_list[i].type = BRP_CONTEXT;
aarch64->brp_list[i].value = 0;
aarch64->brp_list[i].control = 0;
aarch64->brp_list[i].BRPn = i;
aarch64->brp_list[i].brpn = i;
}
/* Setup Watchpoint Register Pairs */
@ -2668,7 +2668,7 @@ static int aarch64_examine_first(struct target *target)
aarch64->wp_list[i].type = BRP_NORMAL;
aarch64->wp_list[i].value = 0;
aarch64->wp_list[i].control = 0;
aarch64->wp_list[i].BRPn = i;
aarch64->wp_list[i].brpn = i;
}
LOG_DEBUG("Configured %i hw breakpoints, %i watchpoints",
@ -3005,8 +3005,8 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
int cpnum;
uint32_t op1;
uint32_t op2;
uint32_t CRn;
uint32_t CRm;
uint32_t crn;
uint32_t crm;
uint32_t value;
long l;
@ -3043,7 +3043,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
"CRn", (int) l);
return JIM_ERR;
}
CRn = l;
crn = l;
retval = Jim_GetLong(interp, argv[4], &l);
if (retval != JIM_OK)
@ -3053,7 +3053,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
"CRm", (int) l);
return JIM_ERR;
}
CRm = l;
crm = l;
retval = Jim_GetLong(interp, argv[5], &l);
if (retval != JIM_OK)
@ -3074,14 +3074,14 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
value = l;
/* NOTE: parameters reordered! */
/* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
/* ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2) */
retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value);
if (retval != ERROR_OK)
return JIM_ERR;
} else {
/* NOTE: parameters reordered! */
/* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
/* ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2) */
retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value);
if (retval != ERROR_OK)
return JIM_ERR;

2
src/target/aarch64.h
View File

@ -46,7 +46,7 @@ struct aarch64_brp {
int type;
target_addr_t value;
uint32_t control;
uint8_t BRPn;
uint8_t brpn;
};
struct aarch64_common {

30
src/target/adi_v5_jtag.c
View File

@ -128,7 +128,7 @@ struct dap_cmd {
struct list_head lh;
uint8_t instr;
uint8_t reg_addr;
uint8_t RnW;
uint8_t rnw;
uint8_t *invalue;
uint8_t ack;
uint32_t memaccess_tck;
@ -153,7 +153,7 @@ static void log_dap_cmd(const char *header, struct dap_cmd *el)
LOG_DEBUG("%s: %2s %6s %5s 0x%08x 0x%08x %2s", header,
el->instr == JTAG_DP_APACC ? "AP" : "DP",
dap_reg_name(el->instr, el->reg_addr),
el->RnW == DPAP_READ ? "READ" : "WRITE",
el->rnw == DPAP_READ ? "READ" : "WRITE",
buf_get_u32(el->outvalue_buf, 0, 32),
buf_get_u32(el->invalue, 0, 32),
el->ack == JTAG_ACK_OK_FAULT ? "OK" :
@ -170,7 +170,7 @@ static int jtag_limit_queue_size(struct adiv5_dap *dap)
}
static struct dap_cmd *dap_cmd_new(struct adiv5_dap *dap, uint8_t instr,
uint8_t reg_addr, uint8_t RnW,
uint8_t reg_addr, uint8_t rnw,
uint8_t *outvalue, uint8_t *invalue,
uint32_t memaccess_tck)
{
@ -193,7 +193,7 @@ static struct dap_cmd *dap_cmd_new(struct adiv5_dap *dap, uint8_t instr,
INIT_LIST_HEAD(&cmd->lh);
cmd->instr = instr;
cmd->reg_addr = reg_addr;
cmd->RnW = RnW;
cmd->rnw = rnw;
if (outvalue != NULL)
memcpy(cmd->outvalue_buf, outvalue, 4);
cmd->invalue = (invalue != NULL) ? invalue : cmd->invalue_buf;
@ -253,7 +253,7 @@ static int adi_jtag_dp_scan_cmd(struct adiv5_dap *dap, struct dap_cmd *cmd, uint
* For APACC access with any sticky error flag set, this is discarded.
*/
cmd->fields[0].num_bits = 3;
buf_set_u32(&cmd->out_addr_buf, 0, 3, ((cmd->reg_addr >> 1) & 0x6) | (cmd->RnW & 0x1));
buf_set_u32(&cmd->out_addr_buf, 0, 3, ((cmd->reg_addr >> 1) & 0x6) | (cmd->rnw & 0x1));
cmd->fields[0].out_value = &cmd->out_addr_buf;
cmd->fields[0].in_value = (ack != NULL) ? ack : &cmd->ack;
@ -299,7 +299,7 @@ static int adi_jtag_dp_scan_cmd_sync(struct adiv5_dap *dap, struct dap_cmd *cmd,
* conversions are performed. See section 4.4.3 of the ADIv5 spec, which
* discusses operations which access these registers.
*
* Note that only one scan is performed. If RnW is set, a separate scan
* Note that only one scan is performed. If rnw is set, a separate scan
* will be needed to collect the data which was read; the "invalue" collects
* the posted result of a preceding operation, not the current one.
*
@ -307,7 +307,7 @@ static int adi_jtag_dp_scan_cmd_sync(struct adiv5_dap *dap, struct dap_cmd *cmd,
* @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
* @param reg_addr two significant bits; A[3:2]; for APACC access, the
* SELECT register has more addressing bits.
* @param RnW false iff outvalue will be written to the DP or AP
* @param rnw false iff outvalue will be written to the DP or AP
* @param outvalue points to a 32-bit (little-endian) integer
* @param invalue NULL, or points to a 32-bit (little-endian) integer
* @param ack points to where the three bit JTAG_ACK_* code will be stored
@ -315,14 +315,14 @@ static int adi_jtag_dp_scan_cmd_sync(struct adiv5_dap *dap, struct dap_cmd *cmd,
*/
static int adi_jtag_dp_scan(struct adiv5_dap *dap,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
uint8_t instr, uint8_t reg_addr, uint8_t rnw,
uint8_t *outvalue, uint8_t *invalue,
uint32_t memaccess_tck, uint8_t *ack)
{
struct dap_cmd *cmd;
int retval;
cmd = dap_cmd_new(dap, instr, reg_addr, RnW, outvalue, invalue, memaccess_tck);
cmd = dap_cmd_new(dap, instr, reg_addr, rnw, outvalue, invalue, memaccess_tck);
if (cmd != NULL)
cmd->dp_select = dap->select;
else
@ -342,7 +342,7 @@ static int adi_jtag_dp_scan(struct adiv5_dap *dap,
* must be different).
*/
static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
uint8_t instr, uint8_t reg_addr, uint8_t rnw,
uint32_t outvalue, uint32_t *invalue,
uint32_t memaccess_tck, uint8_t *ack)
{
@ -351,7 +351,7 @@ static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
buf_set_u32(out_value_buf, 0, 32, outvalue);
retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
retval = adi_jtag_dp_scan(dap, instr, reg_addr, rnw,
out_value_buf, (uint8_t *)invalue, memaccess_tck, ack);
if (retval != ERROR_OK)
return retval;
@ -377,21 +377,21 @@ static int adi_jtag_finish_read(struct adiv5_dap *dap)
}
static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
uint8_t instr, uint8_t reg_addr, uint8_t rnw,
uint32_t outvalue, uint32_t *invalue, uint32_t memaccess_tck)
{
int retval;
/* Issue the read or write */
retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
RnW, outvalue, NULL, memaccess_tck, NULL);
rnw, outvalue, NULL, memaccess_tck, NULL);
if (retval != ERROR_OK)
return retval;
/* For reads, collect posted value; RDBUFF has no other effect.
* Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
*/
if ((RnW == DPAP_READ) && (invalue != NULL)) {
if ((rnw == DPAP_READ) && (invalue != NULL)) {
retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
DP_RDBUFF, DPAP_READ, 0, invalue, 0, NULL);
if (retval != ERROR_OK)
@ -435,7 +435,7 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
*/
if (found_wait && el != list_first_entry(&dap->cmd_journal, struct dap_cmd, lh)) {
prev = list_entry(el->lh.prev, struct dap_cmd, lh);
if (prev->RnW == DPAP_READ) {
if (prev->rnw == DPAP_READ) {
log_dap_cmd("PND", prev);
/* search for the next OK transaction, it contains
* the result of the previous READ */

4
src/target/arm.h
View File

@ -231,13 +231,13 @@ struct arm {
/** Read coprocessor register. */
int (*mrc)(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
uint32_t crn, uint32_t crm,
uint32_t *value);
/** Write coprocessor register. */
int (*mcr)(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
uint32_t crn, uint32_t crm,
uint32_t value);
void *arch_info;

48
src/target/arm11.c
View File

@ -51,14 +51,14 @@ static int arm11_step(struct target *target, int current,
*/
static int arm11_check_init(struct arm11_common *arm11)
{
CHECK_RETVAL(arm11_read_DSCR(arm11));
CHECK_RETVAL(arm11_read_dscr(arm11));
if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) {
LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
LOG_DEBUG("Bringing target into debug mode");
arm11->dscr |= DSCR_HALT_DBG_MODE;
CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
CHECK_RETVAL(arm11_write_dscr(arm11, arm11->dscr));
/* add further reset initialization here */
@ -104,9 +104,9 @@ static int arm11_debug_entry(struct arm11_common *arm11)
/* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
if (arm11->is_wdtr_saved) {
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
arm11_add_debug_scan_n(arm11, 0x05, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
struct scan_field chain5_fields[3];
@ -126,7 +126,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
* but not to issue ITRs(?). The ARMv7 arch spec says it's required
* for executing instructions via ITR.
*/
CHECK_RETVAL(arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr));
CHECK_RETVAL(arm11_write_dscr(arm11, DSCR_ITR_EN | arm11->dscr));
/* From the spec:
@ -143,14 +143,14 @@ static int arm11_debug_entry(struct arm11_common *arm11)
/* mcr 15, 0, r0, cr7, cr10, {4} */
arm11_run_instr_no_data1(arm11, 0xee070f9a);
uint32_t dscr = arm11_read_DSCR(arm11);
uint32_t dscr = arm11_read_dscr(arm11);
LOG_DEBUG("DRAIN, DSCR %08x", dscr);
if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) {
arm11_run_instr_no_data1(arm11, 0xe320f000);
dscr = arm11_read_DSCR(arm11);
dscr = arm11_read_dscr(arm11);
LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
@ -242,7 +242,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
/* spec says clear wDTR and rDTR; we assume they are clear as
otherwise our programming would be sloppy */
{
CHECK_RETVAL(arm11_read_DSCR(arm11));
CHECK_RETVAL(arm11_read_dscr(arm11));
if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL)) {
/*
@ -285,23 +285,23 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
register_cache_invalidate(arm11->arm.core_cache);
/* restore DSCR */
CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
CHECK_RETVAL(arm11_write_dscr(arm11, arm11->dscr));
/* maybe restore rDTR */
if (arm11->is_rdtr_saved) {
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
arm11_add_debug_scan_n(arm11, 0x05, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
struct scan_field chain5_fields[3];
uint8_t Ready = 0; /* ignored */
uint8_t Valid = 0; /* ignored */
uint8_t ready = 0; /* ignored */
uint8_t valid = 0; /* ignored */
arm11_setup_field(arm11, 32, &arm11->saved_rdtr,
NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
arm11_setup_field(arm11, 1, &ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &valid, NULL, chain5_fields + 2);
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
chain5_fields), chain5_fields, TAP_DRPAUSE);
@ -376,14 +376,14 @@ static int arm11_halt(struct target *target)
return ERROR_OK;
}
arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
arm11_add_ir(arm11, ARM11_HALT, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
int i = 0;
while (1) {
CHECK_RETVAL(arm11_read_DSCR(arm11));
CHECK_RETVAL(arm11_read_dscr(arm11));
if (arm11->dscr & DSCR_CORE_HALTED)
break;
@ -519,13 +519,13 @@ static int arm11_resume(struct target *target, int current,
/* activate all watchpoints and breakpoints */
CHECK_RETVAL(arm11_leave_debug_state(arm11, true));
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
arm11_add_ir(arm11, ARM11_RESTART, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
int i = 0;
while (1) {
CHECK_RETVAL(arm11_read_DSCR(arm11));
CHECK_RETVAL(arm11_read_dscr(arm11));
LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
@ -661,7 +661,7 @@ static int arm11_step(struct target *target, int current,
CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
arm11_add_ir(arm11, ARM11_RESTART, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
@ -672,7 +672,7 @@ static int arm11_step(struct target *target, int current,
const uint32_t mask = DSCR_CORE_RESTARTED
| DSCR_CORE_HALTED;
CHECK_RETVAL(arm11_read_DSCR(arm11));
CHECK_RETVAL(arm11_read_dscr(arm11));
LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
if ((arm11->dscr & mask) == mask)
@ -1151,7 +1151,7 @@ static int arm11_examine(struct target *target)
/* check IDCODE */
arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
struct scan_field idcode_field;
@ -1161,9 +1161,9 @@ static int arm11_examine(struct target *target)
/* check DIDR */
arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
arm11_add_debug_scan_n(arm11, 0x00, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
struct scan_field chain0_fields[2];

186
src/target/arm11_dbgtap.c
View File

@ -132,7 +132,7 @@ static const char *arm11_ir_to_string(uint8_t ir)
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
void arm11_add_IR(struct arm11_common *arm11, uint8_t instr, tap_state_t state)
void arm11_add_ir(struct arm11_common *arm11, uint8_t instr, tap_state_t state)
{
struct jtag_tap *tap = arm11->arm.target->tap;
@ -153,7 +153,7 @@ void arm11_add_IR(struct arm11_common *arm11, uint8_t instr, tap_state_t state)
}
/** Verify data shifted out from Scan Chain Register (SCREG). */
static void arm11_in_handler_SCAN_N(uint8_t *in_value)
static void arm11_in_handler_scan_n(uint8_t *in_value)
{
/* Don't expect JTAG layer to modify bits we didn't ask it to read */
uint8_t v = *in_value & 0x1F;
@ -186,12 +186,12 @@ static void arm11_in_handler_SCAN_N(uint8_t *in_value)
* call will end in Pause-DR. The second call, due to the IR
* caching, will not go through Capture-DR when shifting in the
* new scan chain number. As a result the verification in
* arm11_in_handler_SCAN_N() must fail.
* arm11_in_handler_scan_n() must fail.
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
int arm11_add_debug_scan_n(struct arm11_common *arm11,
uint8_t chain, tap_state_t state)
{
/* Don't needlessly switch the scan chain.
@ -211,7 +211,7 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
#endif
JTAG_DEBUG("SCREG <= %d", chain);
arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT);
struct scan_field field;
@ -225,7 +225,7 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
jtag_execute_queue_noclear();
arm11_in_handler_SCAN_N(tmp);
arm11_in_handler_scan_n(tmp);
arm11->jtag_info.cur_scan_chain = chain;
@ -250,7 +250,7 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
* is properly set up. Depending on the instruction, you may also need
* to ensure that the rDTR is ready before that Run-Test/Idle state.
*/
static void arm11_add_debug_INST(struct arm11_common *arm11,
static void arm11_add_debug_inst(struct arm11_common *arm11,
uint32_t inst, uint8_t *flag, tap_state_t state)
{
JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst);
@ -273,15 +273,15 @@ static void arm11_add_debug_INST(struct arm11_common *arm11,
* command queue. It does not require the ARM11 debug TAP to be
* in any particular state.
*/
int arm11_read_DSCR(struct arm11_common *arm11)
int arm11_read_dscr(struct arm11_common *arm11)
{
int retval;
retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
retval = arm11_add_debug_scan_n(arm11, 0x01, ARM11_TAP_DEFAULT);
if (retval != ERROR_OK)
return retval;
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
uint32_t dscr;
struct scan_field chain1_field;
@ -311,14 +311,14 @@ int arm11_read_DSCR(struct arm11_common *arm11)
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
int arm11_write_DSCR(struct arm11_common *arm11, uint32_t dscr)
int arm11_write_dscr(struct arm11_common *arm11, uint32_t dscr)
{
int retval;
retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
retval = arm11_add_debug_scan_n(arm11, 0x01, ARM11_TAP_DEFAULT);
if (retval != ERROR_OK)
return retval;
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
struct scan_field chain1_field;
@ -353,7 +353,7 @@ int arm11_write_DSCR(struct arm11_common *arm11, uint32_t dscr)
*/
int arm11_run_instr_data_prepare(struct arm11_common *arm11)
{
return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
return arm11_add_debug_scan_n(arm11, 0x05, ARM11_TAP_DEFAULT);
}
/** Cleanup after ITR/DTR operations
@ -372,7 +372,7 @@ int arm11_run_instr_data_prepare(struct arm11_common *arm11)
*/
int arm11_run_instr_data_finish(struct arm11_common *arm11)
{
return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
return arm11_add_debug_scan_n(arm11, 0x00, ARM11_TAP_DEFAULT);
}
/**
@ -392,16 +392,16 @@ static
int arm11_run_instr_no_data(struct arm11_common *arm11,
uint32_t *opcode, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
while (count--) {
arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
arm11_add_debug_inst(arm11, *opcode++, NULL, TAP_IDLE);
int i = 0;
while (1) {
uint8_t flag;
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
arm11_add_debug_inst(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
@ -463,33 +463,33 @@ int arm11_run_instr_data_to_core(struct arm11_common *arm11,
uint32_t *data,
size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
arm11_add_debug_inst(arm11, opcode, NULL, TAP_DRPAUSE);
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
struct scan_field chain5_fields[3];
uint32_t Data;
uint8_t Ready;
uint8_t nRetry;
uint32_t _data;
uint8_t ready;
uint8_t n_retry;
arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
arm11_setup_field(arm11, 32, &_data, NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, &ready, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, &n_retry, chain5_fields + 2);
while (count--) {
int i = 0;
do {
Data = *data;
_data = *data;
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
chain5_fields), chain5_fields, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
JTAG_DEBUG("DTR ready %d n_retry %d", ready, n_retry);
int64_t then = 0;
@ -504,24 +504,24 @@ int arm11_run_instr_data_to_core(struct arm11_common *arm11,
}
i++;
} while (!Ready);
} while (!ready);
data++;
}
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
int i = 0;
do {
Data = 0;
_data = 0;
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
chain5_fields), chain5_fields, TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d",
(unsigned) Data, Ready, nRetry);
JTAG_DEBUG("DTR _data %08x ready %d n_retry %d",
(unsigned) _data, ready, n_retry);
int64_t then = 0;
@ -535,7 +535,7 @@ int arm11_run_instr_data_to_core(struct arm11_common *arm11,
}
i++;
} while (!Ready);
} while (!ready);
return ERROR_OK;
}
@ -557,7 +557,7 @@ int arm11_run_instr_data_to_core(struct arm11_common *arm11,
* https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html
* https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html
*/
static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = {
static const tap_state_t arm11_move_drpause_idle_drpause_with_delay[] = {
TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE,
TAP_DRSHIFT
};
@ -581,26 +581,26 @@ static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap,
chain5_fields[2].out_value = NULL;
chain5_fields[2].in_value = NULL;
uint8_t *Readies;
unsigned readiesNum = count;
unsigned bytes = sizeof(*Readies)*readiesNum;
uint8_t *readies;
unsigned readies_num = count;
unsigned bytes = sizeof(*readies)*readies_num;
Readies = malloc(bytes);
if (Readies == NULL) {
readies = malloc(bytes);
if (readies == NULL) {
LOG_ERROR("Out of memory allocating %u bytes", bytes);
return ERROR_FAIL;
}
uint8_t *ReadyPos = Readies;
uint8_t *ready_pos = readies;
while (count--) {
chain5_fields[0].out_value = (uint8_t *)(data++);
chain5_fields[1].in_value = ReadyPos++;
chain5_fields[1].in_value = ready_pos++;
if (count > 0) {
jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields,
TAP_DRPAUSE);
jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
jtag_add_pathmove(ARRAY_SIZE(arm11_move_drpause_idle_drpause_with_delay),
arm11_move_drpause_idle_drpause_with_delay);
} else
jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_IDLE);
}
@ -609,18 +609,18 @@ static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap,
if (retval == ERROR_OK) {
unsigned error_count = 0;
for (size_t i = 0; i < readiesNum; i++) {
if (Readies[i] != 1)
for (size_t i = 0; i < readies_num; i++) {
if (readies[i] != 1)
error_count++;
}
if (error_count > 0) {
LOG_ERROR("%u words out of %u not transferred",
error_count, readiesNum);
error_count, readies_num);
retval = ERROR_FAIL;
}
}
free(Readies);
free(readies);
return retval;
}
@ -649,11 +649,11 @@ int arm11_run_instr_data_to_core_noack(struct arm11_common *arm11,
uint32_t *data,
size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
arm11_add_debug_inst(arm11, opcode, NULL, TAP_DRPAUSE);
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
int retval = arm11_run_instr_data_to_core_noack_inner(arm11->arm.target->tap,
opcode,
@ -663,7 +663,7 @@ int arm11_run_instr_data_to_core_noack(struct arm11_common *arm11,
if (retval != ERROR_OK)
return retval;
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
struct scan_field chain5_fields[3];
@ -740,21 +740,21 @@ int arm11_run_instr_data_from_core(struct arm11_common *arm11,
uint32_t *data,
size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE);
arm11_add_debug_inst(arm11, opcode, NULL, TAP_IDLE);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
struct scan_field chain5_fields[3];
uint32_t Data;
uint8_t Ready;
uint8_t nRetry;
uint32_t _data;
uint8_t ready;
uint8_t n_retry;
arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
arm11_setup_field(arm11, 32, NULL, &_data, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, &ready, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, &n_retry, chain5_fields + 2);
while (count--) {
int i = 0;
@ -765,8 +765,8 @@ int arm11_run_instr_data_from_core(struct arm11_common *arm11,
CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d",
(unsigned) Data, Ready, nRetry);
JTAG_DEBUG("DTR _data %08x ready %d n_retry %d",
(unsigned) _data, ready, n_retry);
int64_t then = 0;
@ -781,9 +781,9 @@ int arm11_run_instr_data_from_core(struct arm11_common *arm11,
}
i++;
} while (!Ready);
} while (!ready);
*data++ = Data;
*data++ = _data;
}
return ERROR_OK;
@ -856,51 +856,51 @@ int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions,
{
int retval;
retval = arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
retval = arm11_add_debug_scan_n(arm11, 0x07, ARM11_TAP_DEFAULT);
if (retval != ERROR_OK)
return retval;
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
arm11_add_ir(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
struct scan_field chain7_fields[3];
uint8_t nRW;
uint32_t DataOut;
uint8_t AddressOut;
uint8_t Ready;
uint32_t DataIn;
uint8_t AddressIn;
uint8_t n_rw;
uint32_t data_out;
uint8_t address_out;
uint8_t ready;
uint32_t data_in;
uint8_t address_in;
arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2);
arm11_setup_field(arm11, 1, &n_rw, &ready, chain7_fields + 0);
arm11_setup_field(arm11, 32, &data_out, &data_in, chain7_fields + 1);
arm11_setup_field(arm11, 7, &address_out, &address_in, chain7_fields + 2);
for (size_t i = 0; i < count + 1; i++) {
if (i < count) {
nRW = actions[i].write ? 1 : 0;
DataOut = actions[i].value;
AddressOut = actions[i].address;
n_rw = actions[i].write ? 1 : 0;
data_out = actions[i].value;
address_out = actions[i].address;
} else {
nRW = 1;
DataOut = 0;
AddressOut = 0;
n_rw = 1;
data_out = 0;
address_out = 0;
}
/* Timeout here so we don't get stuck. */
int i_n = 0;
while (1) {
JTAG_DEBUG("SC7 <= c%-3d Data %08x %s",
(unsigned) AddressOut,
(unsigned) DataOut,
nRW ? "write" : "read");
(unsigned) address_out,
(unsigned) data_out,
n_rw ? "write" : "read");
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain7_fields),
chain7_fields, TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
/* 'nRW' is 'Ready' on read out */
if (Ready)
/* 'n_rw' is 'ready' on read out */
if (ready)
break;
int64_t then = 0;
@ -918,17 +918,17 @@ int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions,
i_n++;
}
if (!nRW)
JTAG_DEBUG("SC7 => Data %08x", (unsigned) DataIn);
if (!n_rw)
JTAG_DEBUG("SC7 => Data %08x", (unsigned) data_in);
if (i > 0) {
if (actions[i - 1].address != AddressIn)
if (actions[i - 1].address != address_in)
LOG_WARNING("Scan chain 7 shifted out unexpected address");
if (!actions[i - 1].write)
actions[i - 1].value = DataIn;
actions[i - 1].value = data_in;
else {
if (actions[i - 1].value != DataIn)
if (actions[i - 1].value != data_in)
LOG_WARNING("Scan chain 7 shifted out unexpected data");
}
}

8
src/target/arm11_dbgtap.h
View File

@ -27,12 +27,12 @@
void arm11_setup_field(struct arm11_common *arm11, int num_bits,
void *in_data, void *out_data, struct scan_field *field);
void arm11_add_IR(struct arm11_common *arm11,
void arm11_add_ir(struct arm11_common *arm11,
uint8_t instr, tap_state_t state);
int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
int arm11_add_debug_scan_n(struct arm11_common *arm11,
uint8_t chain, tap_state_t state);
int arm11_read_DSCR(struct arm11_common *arm11);
int arm11_write_DSCR(struct arm11_common *arm11, uint32_t dscr);
int arm11_read_dscr(struct arm11_common *arm11);
int arm11_write_dscr(struct arm11_common *arm11, uint32_t dscr);
int arm11_run_instr_data_prepare(struct arm11_common *arm11);
int arm11_run_instr_data_finish(struct arm11_common *arm11);

12
src/target/arm720t.c
View File

@ -389,11 +389,11 @@ static void arm720t_deinit_target(struct target *target)
/* FIXME remove forward decls */
static int arm720t_mrc(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
uint32_t crn, uint32_t crm,
uint32_t *value);
static int arm720t_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
uint32_t crn, uint32_t crm,
uint32_t value);
static int arm720t_init_arch_info(struct target *target,
@ -433,7 +433,7 @@ static int arm720t_target_create(struct target *target, Jim_Interp *interp)
static int arm720t_mrc(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
uint32_t crn, uint32_t crm,
uint32_t *value)
{
if (cpnum != 15) {
@ -443,14 +443,14 @@ static int arm720t_mrc(struct target *target, int cpnum,
/* read "to" r0 */
return arm720t_read_cp15(target,
ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
value);
}
static int arm720t_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
uint32_t crn, uint32_t crm,
uint32_t value)
{
if (cpnum != 15) {
@ -460,7 +460,7 @@ static int arm720t_mcr(struct target *target, int cpnum,
/* write "from" r0 */
return arm720t_write_cp15(target,
ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
value);
}

26
src/target/arm7_9_common.c
View File

@ -141,13 +141,13 @@ static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9)
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
} else if (arm7_9->sw_breakpoints_added == 2) {
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
} else {
LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
@ -210,13 +210,13 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
} else if (breakpoint->set == 2) {
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
} else {
LOG_ERROR("BUG: no hardware comparator available");
@ -484,9 +484,9 @@ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watch
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE],
watchpoint->value);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK],
0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
0xff & ~EICE_W_CTRL_NOPC & ~rw_mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE],
EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
EICE_W_CTRL_ENABLE | EICE_W_CTRL_NOPC | (watchpoint->rw & 1));
retval = jtag_execute_queue();
if (retval != ERROR_OK)
@ -503,9 +503,9 @@ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watch
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE],
watchpoint->value);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK],
0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
0xff & ~EICE_W_CTRL_NOPC & ~rw_mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE],
EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
EICE_W_CTRL_ENABLE | EICE_W_CTRL_NOPC | (watchpoint->rw & 1));
retval = jtag_execute_queue();
if (retval != ERROR_OK)
@ -933,7 +933,7 @@ int arm7_9_assert_reset(struct target *target)
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff);
}
}
@ -1212,7 +1212,7 @@ int arm7_9_halt(struct target *target)
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE],
EICE_W_CTRL_ENABLE);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK],
~EICE_W_CTRL_nOPC & 0xff);
~EICE_W_CTRL_NOPC & 0xff);
}
target->debug_reason = DBG_REASON_DBGRQ;
@ -1873,14 +1873,14 @@ void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE],
EICE_W_CTRL_ENABLE);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK],
~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
~(EICE_W_CTRL_RANGE | EICE_W_CTRL_NOPC) & 0xff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE],
current_pc);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK],
~EICE_W_CTRL_nOPC & 0xff);
~EICE_W_CTRL_NOPC & 0xff);
} else {
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
@ -1892,7 +1892,7 @@ void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE],
EICE_W_CTRL_ENABLE);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK],
~EICE_W_CTRL_nOPC & 0xff);
~EICE_W_CTRL_NOPC & 0xff);
}
}

40
src/target/arm920t.c
View File

@ -799,11 +799,11 @@ int arm920t_soft_reset_halt(struct target *target)
/* FIXME remove forward decls */
static int arm920t_mrc(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
uint32_t crn, uint32_t crm,
uint32_t *value);
static int arm920t_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
uint32_t crn, uint32_t crm,
uint32_t value);
static int arm920t_init_arch_info(struct target *target,
@ -873,7 +873,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16];
uint32_t *regs_p[16];
uint32_t C15_C_D_Ind, C15_C_I_Ind;
uint32_t c15_c_d_ind, c15_c_i_ind;
int i;
FILE *output;
int segment, index_t;
@ -933,7 +933,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
/* read current victim */
arm920t_read_cp15_physical(target,
CP15PHYS_DCACHE_IDX, &C15_C_D_Ind);
CP15PHYS_DCACHE_IDX, &c15_c_d_ind);
/* clear interpret mode */
cp15c15 &= ~0x1;
@ -992,7 +992,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
}
/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
regs[0] = 0x0 | (segment << 5) | (c15_c_d_ind << 26);
arm9tdmi_write_core_regs(target, 0x1, regs);
/* set interpret mode */
@ -1034,7 +1034,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
/* read current victim */
arm920t_read_cp15_physical(target, CP15PHYS_ICACHE_IDX,
&C15_C_I_Ind);
&c15_c_i_ind);
/* clear interpret mode */
cp15c15 &= ~0x1;
@ -1092,7 +1092,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
}
/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
regs[0] = 0x0 | (segment << 5) | (c15_c_d_ind << 26);
arm9tdmi_write_core_regs(target, 0x1, regs);
/* set interpret mode */
@ -1156,7 +1156,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
uint32_t *regs_p[16];
int i;
FILE *output;
uint32_t Dlockdown, Ilockdown;
uint32_t d_lockdown, i_lockdown;
struct arm920t_tlb_entry d_tlb[64], i_tlb[64];
int victim;
struct reg *r;
@ -1213,13 +1213,13 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
Dlockdown = regs[1];
d_lockdown = regs[1];
for (victim = 0; victim < 64; victim += 8) {
/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
* base remains unchanged, victim goes through entries 0 to 63
*/
regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
regs[1] = (d_lockdown & 0xfc000000) | (victim << 20);
arm9tdmi_write_core_regs(target, 0x2, regs);
/* set interpret mode */
@ -1256,7 +1256,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
* base remains unchanged, victim goes through entries 0 to 63
*/
regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
regs[1] = (d_lockdown & 0xfc000000) | (victim << 20);
arm9tdmi_write_core_regs(target, 0x2, regs);
/* set interpret mode */
@ -1292,7 +1292,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
}
/* restore D TLB lockdown */
regs[1] = Dlockdown;
regs[1] = d_lockdown;
arm9tdmi_write_core_regs(target, 0x2, regs);
/* Write D TLB lockdown */
@ -1319,13 +1319,13 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
Ilockdown = regs[1];
i_lockdown = regs[1];
for (victim = 0; victim < 64; victim += 8) {
/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
* base remains unchanged, victim goes through entries 0 to 63
*/
regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
regs[1] = (i_lockdown & 0xfc000000) | (victim << 20);
arm9tdmi_write_core_regs(target, 0x2, regs);
/* set interpret mode */
@ -1362,7 +1362,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
* base remains unchanged, victim goes through entries 0 to 63
*/
regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
regs[1] = (d_lockdown & 0xfc000000) | (victim << 20);
arm9tdmi_write_core_regs(target, 0x2, regs);
/* set interpret mode */
@ -1398,7 +1398,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
}
/* restore I TLB lockdown */
regs[1] = Ilockdown;
regs[1] = i_lockdown;
arm9tdmi_write_core_regs(target, 0x2, regs);
/* Write I TLB lockdown */
@ -1528,7 +1528,7 @@ COMMAND_HANDLER(arm920t_handle_cache_info_command)
static int arm920t_mrc(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
uint32_t crn, uint32_t crm,
uint32_t *value)
{
if (cpnum != 15) {
@ -1538,13 +1538,13 @@ static int arm920t_mrc(struct target *target, int cpnum,
/* read "to" r0 */
return arm920t_read_cp15_interpreted(target,
ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
0, value);
}
static int arm920t_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
uint32_t crn, uint32_t crm,
uint32_t value)
{
if (cpnum != 15) {
@ -1554,7 +1554,7 @@ static int arm920t_mcr(struct target *target, int cpnum,
/* write "from" r0 */
return arm920t_write_cp15_interpreted(target,
ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
0, value);
}

18
src/target/arm926ejs.c
View File

@ -46,15 +46,15 @@
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
#define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
#define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, crn, crm) ((opcode_1 << 11) | (opcode_2 << 8) | (crn << 4) | (crm << 0))
static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t *value)
uint32_t crn, uint32_t crm, uint32_t *value)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, crn, crm);
struct scan_field fields[4];
uint8_t address_buf[2] = {0, 0};
uint8_t nr_w_buf = 0;
@ -123,22 +123,22 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
}
static int arm926ejs_mrc(struct target *target, int cpnum, uint32_t op1,
uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
{
if (cpnum != 15) {
LOG_ERROR("Only cp15 is supported");
return ERROR_FAIL;
}
return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value);
return arm926ejs_cp15_read(target, op1, op2, crn, crm, value);
}
static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t value)
uint32_t crn, uint32_t crm, uint32_t value)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, crn, crm);
struct scan_field fields[4];
uint8_t value_buf[4];
uint8_t address_buf[2] = {0, 0};
@ -206,13 +206,13 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
}
static int arm926ejs_mcr(struct target *target, int cpnum, uint32_t op1,
uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
{
if (cpnum != 15) {
LOG_ERROR("Only cp15 is supported");
return ERROR_FAIL;
}
return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value);
return arm926ejs_cp15_write(target, op1, op2, crn, crm, value);
}
static int arm926ejs_examine_debug_reason(struct target *target)

4
src/target/arm926ejs.h
View File

@ -29,9 +29,9 @@ struct arm926ejs_common {
uint32_t common_magic;
struct armv4_5_mmu_common armv4_5_mmu;
int (*read_cp15)(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t *value);
uint32_t crn, uint32_t crm, uint32_t *value);
int (*write_cp15)(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t value);
uint32_t crn, uint32_t crm, uint32_t value);
uint32_t cp15_control_reg;
uint32_t d_fsr;
uint32_t i_fsr;

16
src/target/arm_dpm.c
View File

@ -50,7 +50,7 @@
/* Read coprocessor */
static int dpm_mrc(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
uint32_t *value)
{
struct arm *arm = target_to_arm(target);
@ -62,12 +62,12 @@ static int dpm_mrc(struct target *target, int cpnum,
return retval;
LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
(int) op1, (int) CRn,
(int) CRm, (int) op2);
(int) op1, (int) crn,
(int) crm, (int) op2);
/* read coprocessor register into R0; return via DCC */
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
value);
/* (void) */ dpm->finish(dpm);
@ -75,7 +75,7 @@ static int dpm_mrc(struct target *target, int cpnum,
}
static int dpm_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
uint32_t value)
{
struct arm *arm = target_to_arm(target);
@ -87,12 +87,12 @@ static int dpm_mcr(struct target *target, int cpnum,
return retval;
LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
(int) op1, (int) CRn,
(int) CRm, (int) op2);
(int) op1, (int) crn,
(int) crm, (int) op2);
/* read DCC into r0; then write coprocessor register from R0 */
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
value);
/* (void) */ dpm->finish(dpm);

2
src/target/arm_dpm.h
View File

@ -241,7 +241,7 @@ void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
/* OSLSR (OS Lock Status Register) bits */
#define OSLSR_OSLM0 (1 << 0)
#define OSLSR_OSLK (1 << 1)
#define OSLSR_nTT (1 << 2)
#define OSLSR_NTT (1 << 2)
#define OSLSR_OSLM1 (1 << 3)
#define OSLSR_OSLM (OSLSR_OSLM0|OSLSR_OSLM1)

20
src/target/armv4_5.c
View File

@ -1033,8 +1033,8 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
int cpnum;
uint32_t op1;
uint32_t op2;
uint32_t CRn;
uint32_t CRm;
uint32_t crn;
uint32_t crm;
uint32_t value;
long l;
@ -1071,7 +1071,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
"CRn", (int) l);
return JIM_ERR;
}
CRn = l;
crn = l;
retval = Jim_GetLong(interp, argv[4], &l);
if (retval != JIM_OK)
@ -1081,7 +1081,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
"CRm", (int) l);
return JIM_ERR;
}
CRm = l;
crm = l;
retval = Jim_GetLong(interp, argv[5], &l);
if (retval != JIM_OK)
@ -1110,14 +1110,14 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
value = l;
/* NOTE: parameters reordered! */
/* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
/* ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2) */
retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value);
if (retval != ERROR_OK)
return JIM_ERR;
} else {
/* NOTE: parameters reordered! */
/* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
/* ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2) */
retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value);
if (retval != ERROR_OK)
return JIM_ERR;
@ -1690,7 +1690,7 @@ static int arm_full_context(struct target *target)
static int arm_default_mrc(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
uint32_t crn, uint32_t crm,
uint32_t *value)
{
LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
@ -1699,7 +1699,7 @@ static int arm_default_mrc(struct target *target, int cpnum,
static int arm_default_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
uint32_t crn, uint32_t crm,
uint32_t value)
{
LOG_ERROR("%s doesn't implement MCR", target_type_name(target));

2
src/target/armv7a.c
View File

@ -50,7 +50,7 @@ static void armv7a_show_fault_registers(struct target *target)
if (retval != ERROR_OK)
return;
/* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
/* ARMV4_5_MRC(cpnum, op1, r0, crn, crm, op2) */
/* c5/c0 - {data, instruction} fault status registers */
retval = dpm->instr_read_data_r0(dpm,

2
src/target/armv8.c
View File

@ -727,7 +727,7 @@ static void armv8_show_fault_registers32(struct armv8_common *armv8)
if (retval != ERROR_OK)
return;
/* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
/* ARMV4_5_MRC(cpnum, op1, r0, crn, crm, op2) */
/* c5/c0 - {data, instruction} fault status registers */
retval = dpm->instr_read_data_r0(dpm,

16
src/target/armv8_dpm.c
View File

@ -490,7 +490,7 @@ static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
/* Read coprocessor */
static int dpmv8_mrc(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
uint32_t *value)
{
struct arm *arm = target_to_arm(target);
@ -502,12 +502,12 @@ static int dpmv8_mrc(struct target *target, int cpnum,
return retval;
LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
(int) op1, (int) CRn,
(int) CRm, (int) op2);
(int) op1, (int) crn,
(int) crm, (int) op2);
/* read coprocessor register into R0; return via DCC */
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
value);
/* (void) */ dpm->finish(dpm);
@ -515,7 +515,7 @@ static int dpmv8_mrc(struct target *target, int cpnum,
}
static int dpmv8_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
uint32_t value)
{
struct arm *arm = target_to_arm(target);
@ -527,12 +527,12 @@ static int dpmv8_mcr(struct target *target, int cpnum,
return retval;
LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
(int) op1, (int) CRn,
(int) CRm, (int) op2);
(int) op1, (int) crn,
(int) crm, (int) op2);
/* read DCC into r0; then write coprocessor register from R0 */
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
value);
/* (void) */ dpm->finish(dpm);

62
src/target/cortex_a.c
View File

@ -1294,12 +1294,12 @@ static int cortex_a_set_breakpoint(struct target *target,
brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
brp_list[brp_i].control = control;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
@ -1388,12 +1388,12 @@ static int cortex_a_set_context_breakpoint(struct target *target,
brp_list[brp_i].value = (breakpoint->asid);
brp_list[brp_i].control = control;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
@ -1409,11 +1409,11 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi
int retval = ERROR_FAIL;
int brp_1 = 0; /* holds the contextID pair */
int brp_2 = 0; /* holds the IVA pair */
uint32_t control_CTX, control_IVA;
uint8_t CTX_byte_addr_select = 0x0F;
uint8_t IVA_byte_addr_select = 0x0F;
uint8_t CTX_machmode = 0x03;
uint8_t IVA_machmode = 0x01;
uint32_t control_ctx, control_iva;
uint8_t ctx_byte_addr_select = 0x0F;
uint8_t iva_byte_addr_select = 0x0F;
uint8_t ctx_machmode = 0x03;
uint8_t iva_machmode = 0x01;
struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = &cortex_a->armv7a_common;
struct cortex_a_brp *brp_list = cortex_a->brp_list;
@ -1445,39 +1445,39 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoi
breakpoint->set = brp_1 + 1;
breakpoint->linked_brp = brp_2;
control_CTX = ((CTX_machmode & 0x7) << 20)
control_ctx = ((ctx_machmode & 0x7) << 20)
| (brp_2 << 16)
| (0 << 14)
| (CTX_byte_addr_select << 5)
| (ctx_byte_addr_select << 5)
| (3 << 1) | 1;
brp_list[brp_1].used = true;
brp_list[brp_1].value = (breakpoint->asid);
brp_list[brp_1].control = control_CTX;
brp_list[brp_1].control = control_ctx;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_1].BRPn,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_1].brpn,
brp_list[brp_1].value);
if (retval != ERROR_OK)
return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_1].BRPn,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_1].brpn,
brp_list[brp_1].control);
if (retval != ERROR_OK)
return retval;
control_IVA = ((IVA_machmode & 0x7) << 20)
control_iva = ((iva_machmode & 0x7) << 20)
| (brp_1 << 16)
| (IVA_byte_addr_select << 5)
| (iva_byte_addr_select << 5)
| (3 << 1) | 1;
brp_list[brp_2].used = true;
brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC);
brp_list[brp_2].control = control_IVA;
brp_list[brp_2].control = control_iva;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_2].BRPn,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_2].brpn,
brp_list[brp_2].value);
if (retval != ERROR_OK)
return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_2].BRPn,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_2].brpn,
brp_list[brp_2].control);
if (retval != ERROR_OK)
return retval;
@ -1511,12 +1511,12 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
@ -1530,12 +1530,12 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
brp_list[brp_j].value = 0;
brp_list[brp_j].control = 0;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_j].BRPn,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_j].brpn,
brp_list[brp_j].control);
if (retval != ERROR_OK)
return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_j].BRPn,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_j].brpn,
brp_list[brp_j].value);
if (retval != ERROR_OK)
return retval;
@ -1555,12 +1555,12 @@ static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *b
brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].brpn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
@ -1758,13 +1758,13 @@ static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *wat
wrp_list[wrp_i].control = control;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].WRPn,
+ CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn,
wrp_list[wrp_i].value);
if (retval != ERROR_OK)
return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].WRPn,
+ CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn,
wrp_list[wrp_i].control);
if (retval != ERROR_OK)
return retval;
@ -1807,12 +1807,12 @@ static int cortex_a_unset_watchpoint(struct target *target, struct watchpoint *w
wrp_list[wrp_i].value = 0;
wrp_list[wrp_i].control = 0;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].WRPn,
+ CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].wrpn,
wrp_list[wrp_i].control);
if (retval != ERROR_OK)
return retval;
retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].WRPn,
+ CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].wrpn,
wrp_list[wrp_i].value);
if (retval != ERROR_OK)
return retval;
@ -3040,7 +3040,7 @@ static int cortex_a_examine_first(struct target *target)
cortex_a->brp_list[i].type = BRP_CONTEXT;
cortex_a->brp_list[i].value = 0;
cortex_a->brp_list[i].control = 0;
cortex_a->brp_list[i].BRPn = i;
cortex_a->brp_list[i].brpn = i;
}
LOG_DEBUG("Configured %i hw breakpoints", cortex_a->brp_num);
@ -3054,7 +3054,7 @@ static int cortex_a_examine_first(struct target *target)
cortex_a->wrp_list[i].used = false;
cortex_a->wrp_list[i].value = 0;
cortex_a->wrp_list[i].control = 0;
cortex_a->wrp_list[i].WRPn = i;
cortex_a->wrp_list[i].wrpn = i;
}
LOG_DEBUG("Configured %i hw watchpoints", cortex_a->wrp_num);

4
src/target/cortex_a.h
View File

@ -68,14 +68,14 @@ struct cortex_a_brp {
int type;
uint32_t value;
uint32_t control;
uint8_t BRPn;
uint8_t brpn;
};
struct cortex_a_wrp {
bool used;
uint32_t value;
uint32_t control;
uint8_t WRPn;
uint8_t wrpn;
};
struct cortex_a_common {

6
src/target/cortex_m.h
View File

@ -150,9 +150,9 @@ struct cortex_m_part_info {
#define NVIC_AIRCR 0xE000ED0C
#define NVIC_SHCSR 0xE000ED24
#define NVIC_CFSR 0xE000ED28
#define NVIC_MMFSRb 0xE000ED28
#define NVIC_BFSRb 0xE000ED29
#define NVIC_USFSRh 0xE000ED2A
#define NVIC_MMFSRB 0xE000ED28
#define NVIC_BFSRB 0xE000ED29
#define NVIC_USFSRH 0xE000ED2A
#define NVIC_HFSR 0xE000ED2C
#define NVIC_DFSR 0xE000ED30
#define NVIC_MMFAR 0xE000ED34

6
src/target/embeddedice.h
View File

@ -69,11 +69,11 @@ enum {
EICE_W_CTRL_RANGE = 0x80,
EICE_W_CTRL_CHAIN = 0x40,
EICE_W_CTRL_EXTERN = 0x20,
EICE_W_CTRL_nTRANS = 0x10,
EICE_W_CTRL_nOPC = 0x8,
EICE_W_CTRL_NTRANS = 0x10,
EICE_W_CTRL_NOPC = 0x8,
EICE_W_CTRL_MAS = 0x6,
EICE_W_CTRL_ITBIT = 0x2,
EICE_W_CTRL_nRW = 0x1
EICE_W_CTRL_NRW = 0x1
};
enum {

8
src/target/feroceon.c
View File

@ -373,14 +373,14 @@ static void feroceon_branch_resume_thumb(struct target *target)
}
static int feroceon_read_cp15(struct target *target, uint32_t op1,
uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
uint32_t op2, uint32_t crn, uint32_t crm, uint32_t *value)
{
struct arm *arm = target->arch_info;
struct arm7_9_common *arm7_9 = arm->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int err;
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, crn, crm, op2), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
err = arm7_9_execute_sys_speed(target);
if (err != ERROR_OK)
@ -396,7 +396,7 @@ static int feroceon_read_cp15(struct target *target, uint32_t op1,
}
static int feroceon_write_cp15(struct target *target, uint32_t op1,
uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
uint32_t op2, uint32_t crn, uint32_t crm, uint32_t value)
{
struct arm *arm = target->arch_info;
struct arm7_9_common *arm7_9 = arm->arch_info;
@ -410,7 +410,7 @@ static int feroceon_write_cp15(struct target *target, uint32_t op1,
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_MCR(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_MCR(15, op1, 0, crn, crm, op2), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
return arm7_9_execute_sys_speed(target);
}

14
src/target/hla_target.c
View File

@ -41,7 +41,7 @@
#include "target_request.h"
#include <rtt/rtt.h>
#define savedDCRDR dbgbase /* FIXME: using target->dbgbase to preserve DCRDR */
#define SAVED_DCRDR dbgbase /* FIXME: using target->dbgbase to preserve DCRDR */
#define ARMV7M_SCS_DCRSR DCB_DCRSR
#define ARMV7M_SCS_DCRDR DCB_DCRDR
@ -243,7 +243,7 @@ static int adapter_debug_entry(struct target *target)
int retval;
/* preserve the DCRDR across halts */
retval = target_read_u32(target, DCB_DCRDR, &target->savedDCRDR);
retval = target_read_u32(target, DCB_DCRDR, &target->SAVED_DCRDR);
if (retval != ERROR_OK)
return retval;
@ -405,7 +405,7 @@ static int hl_deassert_reset(struct target *target)
if (jtag_reset_config & RESET_HAS_SRST)
adapter_deassert_reset();
target->savedDCRDR = 0; /* clear both DCC busy bits on initial resume */
target->SAVED_DCRDR = 0; /* clear both DCC busy bits on initial resume */
return target->reset_halt ? ERROR_OK : target_resume(target, 1, 0, 0, 0);
}
@ -481,8 +481,8 @@ static int adapter_resume(struct target *target, int current,
armv7m_restore_context(target);
/* restore savedDCRDR */
res = target_write_u32(target, DCB_DCRDR, target->savedDCRDR);
/* restore SAVED_DCRDR */
res = target_write_u32(target, DCB_DCRDR, target->SAVED_DCRDR);
if (res != ERROR_OK)
return res;
@ -564,8 +564,8 @@ static int adapter_step(struct target *target, int current,
armv7m_restore_context(target);
/* restore savedDCRDR */
res = target_write_u32(target, DCB_DCRDR, target->savedDCRDR);
/* restore SAVED_DCRDR */
res = target_write_u32(target, DCB_DCRDR, target->SAVED_DCRDR);
if (res != ERROR_OK)
return res;