interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

target/cortex_m: make reset robust again 

After merging [1] 'reset halt' does not work on not responding Cortex-M.

Relax the examined tests and try to set vector catch VC_CORERESET
if debug_ap is available.

While on it add an info about examination state to debug logs.

Fixes: [1] commit 98d9f1168c ("target: reset target examined flag if target::examine() fails")
Change-Id: Ie2e018610026180af5997d70231061a275f05c76
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6745
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tomas Vanek 2021-11-23 10:06:51 +01:00 committed by Antonio Borneo
parent 978c115dac
commit b991c416b7
1 changed files with 29 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
src/target/cortex_m.c
View File

@ -1408,8 +1408,9 @@ static int cortex_m_assert_reset(struct target *target)
struct armv7m_common *armv7m = &cortex_m->armv7m;
enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
LOG_TARGET_DEBUG(target, "target->state: %s",
target_state_name(target));
LOG_TARGET_DEBUG(target, "target->state: %s,%s examined",
target_state_name(target),
target_was_examined(target) ? "" : " not");
enum reset_types jtag_reset_config = jtag_get_reset_config();
@ -1428,24 +1429,32 @@ static int cortex_m_assert_reset(struct target *target)
bool srst_asserted = false;
if (!target_was_examined(target)) {
if (jtag_reset_config & RESET_HAS_SRST) {
adapter_assert_reset();
if (target->reset_halt)
LOG_TARGET_ERROR(target, "Target not examined, will not halt after reset!");
return ERROR_OK;
} else {
LOG_TARGET_ERROR(target, "Target not examined, reset NOT asserted!");
return ERROR_FAIL;
}
}
if ((jtag_reset_config & RESET_HAS_SRST) &&
(jtag_reset_config & RESET_SRST_NO_GATING)) {
((jtag_reset_config & RESET_SRST_NO_GATING) || !armv7m->debug_ap)) {
/* If we have no debug_ap, asserting SRST is the only thing
* we can do now */
adapter_assert_reset();
srst_asserted = true;
}
/* We need at least debug_ap to go further.
* Inform user and bail out if we don't have one. */
if (!armv7m->debug_ap) {
if (srst_asserted) {
if (target->reset_halt)
LOG_TARGET_ERROR(target, "Debug AP not available, will not halt after reset!");
/* Do not propagate error: reset was asserted, proceed to deassert! */
target->state = TARGET_RESET;
register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
return ERROR_OK;
} else {
LOG_TARGET_ERROR(target, "Debug AP not available, reset NOT asserted!");
return ERROR_FAIL;
}
}
/* Enable debug requests */
int retval = cortex_m_read_dhcsr_atomic_sticky(target);
@ -1546,7 +1555,7 @@ static int cortex_m_assert_reset(struct target *target)
if (retval != ERROR_OK)
return retval;
if (target->reset_halt) {
if (target->reset_halt && target_was_examined(target)) {
retval = target_halt(target);
if (retval != ERROR_OK)
return retval;
@ -1559,8 +1568,9 @@ static int cortex_m_deassert_reset(struct target *target)
{
struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
LOG_TARGET_DEBUG(target, "target->state: %s",
target_state_name(target));
LOG_TARGET_DEBUG(target, "target->state: %s,%s examined",
target_state_name(target),
target_was_examined(target) ? "" : " not");
/* deassert reset lines */
adapter_deassert_reset();
@ -1569,7 +1579,7 @@ static int cortex_m_deassert_reset(struct target *target)
if ((jtag_reset_config & RESET_HAS_SRST) &&
!(jtag_reset_config & RESET_SRST_NO_GATING) &&
target_was_examined(target)) {
armv7m->debug_ap) {
int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
if (retval != ERROR_OK) {