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riscv: don't export local symbols 

Symbols that are not used outside the file should not be exported
and should be declared as static.
Move the existing comments to the static declarations.

Change-Id: Idf208e3fda4b3f8df789553cf03ebf5f20d811bb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7170
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
Tested-by: jenkins
This commit is contained in:
Antonio Borneo 2022-09-06 00:20:41 +02:00
parent d112a1282e
commit 933cbd9156
2 changed files with 22 additions and 42 deletions
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35
src/target/riscv/riscv.c
View File

@ -109,30 +109,30 @@ typedef enum slot {
#define MAX_HWBPS 16
#define DRAM_CACHE_SIZE 16
uint8_t ir_dtmcontrol[4] = {DTMCONTROL};
static uint8_t ir_dtmcontrol[4] = {DTMCONTROL};
struct scan_field select_dtmcontrol = {
.in_value = NULL,
.out_value = ir_dtmcontrol
};
uint8_t ir_dbus[4] = {DBUS};
static uint8_t ir_dbus[4] = {DBUS};
struct scan_field select_dbus = {
.in_value = NULL,
.out_value = ir_dbus
};
uint8_t ir_idcode[4] = {0x1};
static uint8_t ir_idcode[4] = {0x1};
struct scan_field select_idcode = {
.in_value = NULL,
.out_value = ir_idcode
};
bscan_tunnel_type_t bscan_tunnel_type;
static bscan_tunnel_type_t bscan_tunnel_type;
int bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */
static const uint8_t bscan_zero[4] = {0};
static const uint8_t bscan_one[4] = {1};
static uint8_t ir_user4[4];
struct scan_field select_user4 = {
static struct scan_field select_user4 = {
.in_value = NULL,
.out_value = ir_user4
};
@ -256,6 +256,11 @@ static const virt2phys_info_t sv48 = {
.pa_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
};
static enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid);
static void riscv_info_init(struct target *target, struct riscv_info *r);
static void riscv_invalidate_register_cache(struct target *target);
static int riscv_step_rtos_hart(struct target *target);
static void riscv_sample_buf_maybe_add_timestamp(struct target *target, bool before)
{
RISCV_INFO(r);
@ -861,7 +866,7 @@ int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_
return ERROR_FAIL;
}
int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
static int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, breakpoint->address);
assert(breakpoint);
@ -941,7 +946,7 @@ static int remove_trigger(struct target *target, struct trigger *trigger)
return ERROR_OK;
}
int riscv_remove_breakpoint(struct target *target,
static int riscv_remove_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
if (breakpoint->type == BKPT_SOFT) {
@ -1019,7 +1024,7 @@ int riscv_remove_watchpoint(struct target *target,
* The GDB server uses this information to tell GDB what data address has
* been hit, which enables GDB to print the hit variable along with its old
* and new value. */
int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
static int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
{
struct watchpoint *wp = target->watchpoints;
@ -1462,7 +1467,7 @@ static int resume_finish(struct target *target)
* @par single_hart When true, only resume a single hart even if SMP is
* configured. This is used to run algorithms on just one hart.
*/
int riscv_resume(
static int riscv_resume(
struct target *target,
int current,
target_addr_t address,
@ -3199,7 +3204,8 @@ struct target_type riscv_target = {
/*** RISC-V Interface ***/
void riscv_info_init(struct target *target, struct riscv_info *r)
/* Initializes the shared RISC-V structure. */
static void riscv_info_init(struct target *target, struct riscv_info *r)
{
memset(r, 0, sizeof(*r));
@ -3244,7 +3250,9 @@ static int riscv_resume_go_all_harts(struct target *target)
return ERROR_OK;
}
int riscv_step_rtos_hart(struct target *target)
/* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
* then the only hart. */
static int riscv_step_rtos_hart(struct target *target)
{
RISCV_INFO(r);
if (riscv_select_current_hart(target) != ERROR_OK)
@ -3302,7 +3310,8 @@ int riscv_set_current_hartid(struct target *target, int hartid)
return ERROR_OK;
}
void riscv_invalidate_register_cache(struct target *target)
/* Invalidates the register cache. */
static void riscv_invalidate_register_cache(struct target *target)
{
LOG_DEBUG("[%d]", target->coreid);
register_cache_invalidate(target->reg_cache);
@ -3452,7 +3461,7 @@ bool riscv_is_halted(struct target *target)
return r->is_halted(target);
}
enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
static enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
{
RISCV_INFO(r);
if (riscv_set_current_hartid(target, hartid) != ERROR_OK)

29
src/target/riscv/riscv.h
View File

@ -278,19 +278,14 @@ static inline bool is_riscv(const struct riscv_info *riscv_info)
return riscv_info->common_magic == RISCV_COMMON_MAGIC;
}
extern uint8_t ir_dtmcontrol[4];
extern struct scan_field select_dtmcontrol;
extern uint8_t ir_dbus[4];
extern struct scan_field select_dbus;
extern uint8_t ir_idcode[4];
extern struct scan_field select_idcode;
extern struct scan_field select_user4;
extern struct scan_field *bscan_tunneled_select_dmi;
extern uint32_t bscan_tunneled_select_dmi_num_fields;
typedef enum { BSCAN_TUNNEL_NESTED_TAP, BSCAN_TUNNEL_DATA_REGISTER } bscan_tunnel_type_t;
extern int bscan_tunnel_ir_width;
extern bscan_tunnel_type_t bscan_tunnel_type;
uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out);
void select_dmi_via_bscan(struct target *target);
@ -300,15 +295,6 @@ int riscv_openocd_poll(struct target *target);
int riscv_halt(struct target *target);
int riscv_resume(
struct target *target,
int current,
target_addr_t address,
int handle_breakpoints,
int debug_execution,
bool single_hart
);
int riscv_openocd_step(
struct target *target,
int current,
@ -321,13 +307,6 @@ int riscv_openocd_deassert_reset(struct target *target);
/*** RISC-V Interface ***/
/* Initializes the shared RISC-V structure. */
void riscv_info_init(struct target *target, struct riscv_info *r);
/* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
* then the only hart. */
int riscv_step_rtos_hart(struct target *target);
bool riscv_supports_extension(struct target *target, char letter);
/* Returns XLEN for the given (or current) hart. */
@ -356,7 +335,6 @@ int riscv_get_register(struct target *target, riscv_reg_t *value,
/* Checks the state of the current hart -- "is_halted" checks the actual
* on-device register. */
bool riscv_is_halted(struct target *target);
enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid);
/* These helper functions let the generic program interface get target-specific
* information. */
@ -371,18 +349,11 @@ void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t
void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a);
int riscv_dmi_write_u64_bits(struct target *target);
/* Invalidates the register cache. */
void riscv_invalidate_register_cache(struct target *target);
int riscv_enumerate_triggers(struct target *target);
int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
int riscv_remove_breakpoint(struct target *target,
struct breakpoint *breakpoint);
int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
int riscv_remove_watchpoint(struct target *target,
struct watchpoint *watchpoint);
int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_wp_address);
int riscv_init_registers(struct target *target);