target/xtensa: invalidate register cache on reset
Resolves issues where registers are accessed when poll() logic is inactive or has not yet been triggered. Signed-off-by: Ian Thompson <ianst@cadence.com> Change-Id: If7a4d00938fb188b008325249627f7773c3484c5 Reviewed-on: https://review.openocd.org/c/openocd/+/7197 Tested-by: jenkins Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
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@ -959,7 +959,6 @@ int xtensa_assert_reset(struct target *target)
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struct xtensa *xtensa = target_to_xtensa(target);
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LOG_TARGET_DEBUG(target, "target_number=%i, begin", target->target_number);
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target->state = TARGET_RESET;
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xtensa_queue_pwr_reg_write(xtensa,
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XDMREG_PWRCTL,
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PWRCTL_JTAGDEBUGUSE(xtensa) | PWRCTL_DEBUGWAKEUP(xtensa) | PWRCTL_MEMWAKEUP(xtensa) |
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@ -968,8 +967,12 @@ int xtensa_assert_reset(struct target *target)
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int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
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if (res != ERROR_OK)
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return res;
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/* registers are now invalid */
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xtensa->reset_asserted = true;
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return res;
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register_cache_invalidate(xtensa->core_cache);
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target->state = TARGET_RESET;
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return ERROR_OK;
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}
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int xtensa_deassert_reset(struct target *target)
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