Commit Graph

4844 Commits

Author SHA1 Message Date
François LEGAL 55e04e3157 src/target/mips_m4k : add fast read method
Add the fast read method to speed up flash verification
after programming. Works the same as fast write already
implemented.

Signed-off-by: François LEGAL <devel@thom.fr.eu.org>
Change-Id: I74611a3542a88212f0483ec8ee368aba3d1f03c7
Reviewed-on: https://review.openocd.org/c/openocd/+/7564
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-07 21:46:36 +00:00
François LEGAL 18aacc8bf3 src/target/mips_m4k : fix condition on overlapping workspace data area
The condition to check if the workspace area (used by actual MIPS code
executed on target) and data area (sandbox to put data to be read/written
to/from flash) is wrong, thus preventing the use of FAST_* commands to
program/verify FLASH.

Signed-off-by: François LEGAL <devel@thom.fr.eu.org>
Change-Id: Ic68424b7f42d44e550433a120093db5e7980fd56
Reviewed-on: https://review.openocd.org/c/openocd/+/7563
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-04-07 21:45:18 +00:00
Tim Newsome 0c76e263e3
Merge pull request #823 from panciyan/riscv
target/riscv: leaf PTE check PTE_W missing
2023-04-07 10:05:57 -07:00
Tim Newsome 15bb3e23b8
Merge pull request #821 from en-sc/en-sc/fix-reset-mharts
target/riscv: simplify reset for rtos harts
2023-04-06 09:54:15 -07:00
Tim Newsome 52b102318b
Merge pull request #830 from zqb-all/csr_32bit
target/riscv: set some csr size to 32
2023-04-06 09:40:59 -07:00
Tim Newsome 7e36bb6158
Merge branch 'riscv' into hypervisor
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-05 10:48:56 -07:00
Evgeniy Naydanov 1c168242e9 target/riscv: simplify reset
Since the deletion of `-rtos hwthread`, there is no need to treat harts
with `-rtos` specified differently on reset.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I88a9129936b5172bb7479dfa1255e29ff460c054
2023-04-05 19:14:45 +03:00
Tim Newsome c6ba4166e4
Merge pull request #816 from riscv/from_upstream
Merge up to commit '1293ddd65713d6551775b67169387622ada477c1' from upstream
2023-04-05 08:47:27 -07:00
Tim Newsome 2dc14117a7
Merge pull request #819 from zqb-all/fix_size_assert
target/riscv: support log memory access128
2023-04-04 11:05:52 -07:00
Mark Zhuang e284aa066e target/riscv: set some csr size to 32
Change-Id: I4703b7b8ad492b14dc8d188ebb8f645c568fd515
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-04-03 23:53:14 +08:00
Tim Newsome 38cf11abab
Merge pull request #824 from riscv/aia
target/riscv: AIA regs, check for H not V
2023-03-29 13:52:34 -07:00
Tim Newsome 4fdcc14e26 target/riscv: Set hypervisor bits.
No other attempt is made at doing anything hypervisor-specific. Are
other things necessary?

Change-Id: Ib65f114888840cf0878f9bfe028c9a42b436aa3f
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-29 13:40:39 -07:00
Antonio Borneo e9a7221b68 target: rewrite command 'target smp' as COMMAND_HANDLER
This also fixes an incorrect return ERROR_xx from a jim command,
propagated from return value of rtos_smp_init().

Change-Id: Icf4893c00aabd8fadd60077c5e8a2e926f687518
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7511
Tested-by: jenkins
2023-03-25 18:16:02 +00:00
Antonio Borneo 12b405a4ac target: rewrite command 'target names' as COMMAND_HANDLER
Print one entry per line.
While there add the mandatory 'usage' field.

Change-Id: Ia832684817f3bdbfa4cb943cd97e3f9fb2605902
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7510
Tested-by: jenkins
2023-03-25 18:15:53 +00:00
Antonio Borneo d9d698103e target: rewrite command 'target types' as COMMAND_HANDLER
Print one entry per line.
While there add the mandatory 'usage' field.

Change-Id: I135556e12154e33fdbd0f71d89f6fe37c69813b7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7509
Tested-by: jenkins
2023-03-25 18:15:43 +00:00
Antonio Borneo 26f457896c target: rewrite command 'target current' as COMMAND_HANDLER
While there add the mandatory 'usage' field.

Change-Id: I3e5b826ca58f7ade30a443ada0cb4a9cd9ea35c2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7508
Tested-by: jenkins
2023-03-25 18:15:33 +00:00
Antonio Borneo 583efa68f7 target: rewrite command 'arp_halt_gdb' as COMMAND_HANDLER
While there add the mandatory 'usage' field.

Change-Id: I5389881dac25877dc32930ec36ee546e48ecc14d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7507
Tested-by: jenkins
2023-03-25 18:15:23 +00:00
Antonio Borneo 2dda0e37d9 target: rewrite command 'examine_deferred' as COMMAND_HANDLER
Check for empty command line, add the mandatory 'usage' field.

Change-Id: I9c3606242ec3dda9026fe19222162a110e618bff
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7506
Tested-by: jenkins
2023-03-25 18:15:14 +00:00
Antonio Borneo cca64798f8 target: rewrite command 'was_examined' as COMMAND_HANDLER
Check for empty command line, add the mandatory 'usage' field.

Change-Id: I3f59448458fe01268bf5f4293aea5adcbd6d8279
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7505
Tested-by: jenkins
2023-03-25 18:15:03 +00:00
Antonio Borneo 113ba58231 target: rewrite command 'target curstate' as COMMAND_HANDLER
While there, add the mandatory 'usage' field.

Change-Id: Ibfda6f56a1450e2eb9ad3092d756de0778f4a092
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7504
Tested-by: jenkins
2023-03-25 18:14:52 +00:00
Antonio Borneo 584986ab1c target: rewrite command 'read_memory' as COMMAND_HANDLER
While there, fix typo on 'exceeds'.
In a following patch, the output could be formatted and split in N
values per line to make it easier to read by humans.

Change-Id: I295111a80934393011e46311f6cf6c13f2bdc0a3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7503
Tested-by: jenkins
2023-03-25 18:14:40 +00:00
Antonio Borneo 6f8c27dcfc target: arm_tpiu_swo: rewrite command 'tpiu init' as COMMAND_HANDLER
Change-Id: Iaaccfc62dd85267066a152c434f254d1b9a0c4f1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7502
Tested-by: jenkins
2023-03-25 18:14:30 +00:00
Antonio Borneo 90ddac12e3 target: arm_tpiu_swo: rewrite command 'tpiu names' as COMMAND_HANDLER
While there, format in a human readable way the output list by
using one line per tpiu name.

Change-Id: I937c92b6c1e92509cf8aa96be1517a51bc363600
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7501
Tested-by: jenkins
2023-03-25 18:14:18 +00:00
Antonio Borneo 5d39a8852a target: arm_tpiu_swo: rewrite command 'tpiu enable' as COMMAND_HANDLER
Change-Id: Ia600948b99a229ef0490b7f576df62f880db8546
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7500
Tested-by: jenkins
2023-03-25 18:14:07 +00:00
Antonio Borneo 8fa6db6e8e target: arm_tpiu_swo: rewrite command 'tpiu disable' as COMMAND_HANDLER
Change-Id: I689482f898bde2afa2881b2f311676a6b98abb9a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7499
Tested-by: jenkins
2023-03-25 18:13:56 +00:00
Antonio Borneo f76e67a440 target: arm_dap: rewrite command 'dap names' as COMMAND_HANDLER
While there, format in a human readable way the output list by
using one line per dap name.

Change-Id: I24a47350105b90db15808c61790f05d807120739
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7498
Tested-by: jenkins
2023-03-25 18:13:46 +00:00
Antonio Borneo 5da4ef25c8 target: cti: rewrite command 'cti names' as COMMAND_HANDLER
While there, format in a human readable way the output list by
using one line per cti name.

Change-Id: I6d4870ee512fe7e6935d73355c2377ad805ccc3b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7492
Tested-by: jenkins
2023-03-25 18:12:20 +00:00
Antonio Borneo c4f2337d02 target: armv4_5: rewrite commands 'arm mcr/mrc' as COMMAND_HANDLER
While there, add a check for target halted and check the number of
parameters accordingly to the command name.

Change-Id: I9e8bb109c35039561997d14782fac682267aee65
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7491
Tested-by: jenkins
2023-03-25 18:12:02 +00:00
Antonio Borneo 21e6252965 target: aarch64: rewrite commands 'aarch64 mcr/mrc' as COMMAND_HANDLER
This also fixes an incorrect return ERROR_TARGET_NOT_HALTED from a
jim command.

Change-Id: I99a02a21bedb64e60944e295c7cf24356e07be60
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7490
Tested-by: jenkins
2023-03-25 18:11:26 +00:00
Tomas Vanek 415715d91a target/adi_v5_jtag: fix endianness error in transaction replay
The code for JTAG WAIT recovery did not handle DP_SELECT
endianness.

While on it, mark missing ADIv6 DP SELECT1 handling as TODO.

Change-Id: I44f3bc8fc9fd2483c0293b6d4f2c51a60ca01873
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7540
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-03-25 18:07:51 +00:00
Tomas Vanek 6ecd99ff9b target/adi_v5_swd: update comment about SWD capability
The multidrop SWD is also supported.

Change-Id: I9fefc54fc9d40a75194285cd6e0f10c5c347d9b6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7537
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-03-25 18:07:04 +00:00
Erhan Kurubas faeae51d7f target/espressif: check common_magic instead of gdb_arch string
The value returned by target_get_gdb_arch() is something specific for GDB.
There could be several variants of the same CPU.
If we start implementing all the variants, checking the string value,
could become incorrect.
It's better to check for xtensa->common_magic == XTENSA_COMMON_MAGIC

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I20f3fdced176c3b9ab00f889743161ecad7280f9
Reviewed-on: https://review.openocd.org/c/openocd/+/7536
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-03-25 18:06:36 +00:00
Mark Zhuang dfce1d2708 target/riscv: [NFC] rename variables named read/write
read/write is system function

Change-Id: I75db4dd5a1c60e9cff8a58a863a887beffc37cab
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-03-25 21:18:12 +08:00
Mark Zhuang 4cccda353c target/riscv: support log memory access128
Change-Id: I6b22c97f81fac26703b66d3dbd8b6d41aaea4875
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-03-25 20:31:42 +08:00
Tim Newsome 5bc9c207eb target/riscv: Don't ignore maskmax for icount.
Icount triggers don't have a maskmax field at all. This is a cut and
paste error.

Change-Id: I001b3d41bf683599706dba713f7be475e8dd1668
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-24 13:41:06 -07:00
Tim Newsome 194a90186c target/riscv: AIA regs, check for H not V
Change-Id: Iac37b79dc737fd64a21dce83b3ef36f1a8aae118
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-24 09:21:48 -07:00
panciyan 1479eca38f target/riscv: leaf PTE check PTE_W missing
When permission bits R, W, and X in PTE all three are zero,
the PTE is a pointter to the next level of the page table;
otherwise, it is a leaf PTE. Here PTE_W is missed.

Change-Id: I82a4cc4e64280f0fcad75b20e51b617520aff29b
Signed-off-by: panciyan <panciyan@eswincomputing.com>
2023-03-23 02:45:42 +00:00
Tim Newsome d744207943
Merge pull request #815 from riscv/s_aia
target/riscv: Expose S?aia CSRs if they're on the target.
2023-03-20 08:45:13 -07:00
Ian Thompson 904d58c208 target/xtensa: add NX support
- Manual integration of NX support from xt0.2 release
- No new clang static analysis warnings

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I95b51ccc83e56c0d4dbf09e01969ed6a4a93d497
Reviewed-on: https://review.openocd.org/c/openocd/+/7356
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-03-18 21:56:50 +00:00
Peter Collingbourne 047b1a8fc2 target/image: zero-initialize ELF segments up to p_memsz
We were previously not zero-initializing ELF segments between p_filesz
and p_memsz (aka BSS). However, this may be necessary depending on the
user's application. Therefore, start doing so.

Change-Id: I5a743390069583aca7ee276f53afeccf2cac0855
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7513
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-03-18 21:52:02 +00:00
Tim Newsome 2cd3436002 Fix build.
Change-Id: I89de7dc21d7958531ec9619905d3d8c4f54a3acf
2023-03-16 18:08:25 -07:00
Tim Newsome 868ebdd89c Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstream
This includes
https://sourceforge.net/p/openocd/mailman/message/37710818/, which
should fix #814.

Conflicts:
	.travis.yml
	contrib/loaders/flash/stm32/stm32f1x.S
	contrib/loaders/flash/stm32/stm32f2x.S
	doc/openocd.texi
	src/rtos/FreeRTOS.c
	src/server/gdb_server.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h
	src/target/riscv/riscv_semihosting.c
	tcl/target/esp_common.cfg
	tcl/target/gd32vf103.cfg
	tools/scripts/checkpatch.pl

Change-Id: I1986c13298ca0dafbe3aecaf1b0b35626525e4eb
2023-03-16 18:02:35 -07:00
Tim Newsome 3387015af0
Merge pull request #800 from en-sc/en-sc/try-all-trigs-in-maybe-add-trig
Try all triggers in maybe_add_trigger_t*
2023-03-16 16:58:12 -07:00
Tim Newsome 2c760b6317 Expose S?aia CSRs if they're on the target.
Untested, because I don't have a target that implements this.

Change-Id: Iff82c124e7caf8e8960a9da62d8e727afb2c6b8a
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-16 15:37:06 -07:00
Tim Newsome eb8cabf821 Update encoding.h.
Change-Id: I1b6d2cac86ec485310761b73370fb2667ebb3bbd
2023-03-16 11:27:06 -07:00
Tim Newsome 750f7b4bc3
Merge pull request #812 from XuHangHub/riscv
target/riscv: fix the bug of using S2 register in read_memory_progbuf
2023-03-15 09:29:03 -07:00
Evgeniy Naydanov 55a576037e Try all triggers in maybe_add_trigger_t2 and _t6
It is possible for triggers of the same type to support different match
field values, so it is needed to try all the triggers, not just the
first one.

Fixes issue #788.

Signed-off-by: Evgeniy Naydanov evgeniy.naydanov@syntacore.com
Change-Id: I4c9fbc98bae7259377456d9ad8e770232724a592
2023-03-15 13:05:33 +03:00
Hang Xu 2370d78249 target/riscv: fix the bug of using S2 register in read_memory_progbuf
We should avoid using x16~x31 register in program buffer because there
are no such general purpose registers in RVE(Embedded) extension.
For targets that support rvE, when the parameter increment=0
and count>1 of the read_memory_progbuf function, openocd will cause
an error due to the use of the s2 register.
For example:
{Command} {riscv repeat_read} count address [size=4]

Change-Id: I8b74dcc15cd00a400f2f1354c577a82132394435
Signed-off-by: Hang Xu <xuhang@eswincomputing.com>
2023-03-12 04:01:05 +00:00
Tim Newsome dcb0b5b976 target/riscv: Remove unused address_in variable.
Change-Id: Iead46b543a3b866f36b4d61a8824b6335dab276a
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-10 10:58:46 -08:00
Tim Newsome 4f97898889 Merge commit 'd1b882f2c014258be5397067e45848fa5465b78b' into from_upstream
Conflicts:
	doc/openocd.texi
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c

Change-Id: I8cd557a10c3d5beeaed05ecc05d4c325a9ee7e70
2023-02-28 10:54:48 -08:00
Tim Newsome 87f9e590b9
Merge pull request #799 from riscv/icount
Add `riscv icount` command.
2023-02-16 10:16:30 -08:00
Anatoly Parshintsev da5d2748e6
target/riscv: hide_csrs configuration option (#787)
* target/riscv: hide_csrs configuration option

This option allows users to mark certain CSRs as hidden so they could be
expluded from *reg* output and target.xml

Change-Id: Iddf8456cd3901f572f8590329ebba5229974d24a

* Update doc/openocd.texi

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>

---------

Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2023-02-15 09:53:37 -08:00
Jan Matyas 872ebb14ca
Add command "exec_progbuf" (#795)
* Add command "exec_progbuf"

Command "exec_progbuf" allows to execute a user-specified sequence
of instructions using the program buffer.

Change-Id: If3b9614129d0b6fcbc33fade29d3d60b35e52f98
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

* Updated the doc:

- Minor reword and reorder of the sentences.
- Added information about C-instructions in progbuf.
- Fixed a typo (per the review).
- Added examples.

Change-Id: I88c9a3ff3c6b60614be7eafd3a6f21be722a77b7
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

* Cosmetic changes

Change-Id: I7135c9f435f640e189c7d7922a2702814dfd595f
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

---------

Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Co-authored-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-15 09:53:03 -08:00
Tim Newsome fb3376b7f0 Add `riscv icount` command.
Also refactor shared code for clearing itrigger/etrigger/icount.

Change-Id: Iac2e756332c89d2ed43435391e3c097abc825255
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-15 09:31:44 -08:00
Tim Newsome a57fc5e78c
Merge pull request #794 from riscv/fix-fence-instruction
Fix opcode for the "fence" instruction
2023-02-14 10:51:13 -08:00
Tim Newsome 2b4826cd32
Merge pull request #797 from riscv/Zve32
If XLEN=64 and vsew=64 fails, fall back to vsew=32.
2023-02-10 12:36:48 -08:00
Tim Newsome f4f3ce7db7 Don't reuse a single riscv_program.
Because riscv_program_exec() tries to add an instruction every time
through.

This would cause an error accessing vector registers where VL > 14(?).

Change-Id: Ie676ca8c9be786b46aa2a4b4028ac8b27f7a4b40
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-10 11:51:21 -08:00
Tim Newsome abb918685f If XLEN=64 and vsew=64 fails, fall back to vsew=32.
This should make vector accesses work on 64-bit harts that implement
Zve32*. There doesn't appear to be any way to easily determine what vsew
values are allowed, so try and notice the failure.

Change-Id: Ide0722d0d67da402a4fbe88163830094e46beb84
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-10 11:51:17 -08:00
Parshintsev Anatoly 5845f3b71c CSR_MCOUNTEREN should not exist if U-mode is not supported
Change-Id: I1a2420fb88bd3ee37f6a539992e8dc119fdd6e0e
2023-02-10 02:08:40 +03:00
Tim Newsome 344e8bd263 Print out debug value after the assignment is made.
Change-Id: I6ba1064c09f48eba97d84ea9db5ff44d82b9d004
2023-02-08 11:02:51 -08:00
Tim Newsome 91552c7999 Move yes_no_maybe_t into riscv.h.
Change-Id: I5bbdc1af3147e05e25612bf496f409111248c979
2023-02-08 11:02:20 -08:00
Antonio Borneo 4a79372b6e target: arc: rewrite command 'arc add-reg' as COMMAND_HANDLER
While there, fix some coding style error and remove the now unused
function jim_arc_read_reg_name_field() and the macro
JIM_CHECK_RETVAL().

Change-Id: I140b4b929978b2936f2310e0b7d1735ba726c517
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7426
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
2023-02-03 22:48:48 +00:00
Antonio Borneo 85f3b10a69 target: arc: rewrite command 'arc add-reg-type-struct' as COMMAND_HANDLER
Use a COMMAND_HELPER() to avoid memory leaks when the helper
COMMAND_PARSE_NUMBER() returns due to an error.

While there:
- fix potential SIGSEGV due to dereference 'type' before checking
  it's not NULL;
- fix an incorrect NUL byte termination while copying to
  type->data_type.id and to bitfields[cur_field].name;
- fix some coding style error;
- remove the now unused function jim_arc_read_reg_type_field().

Change-Id: I7158fd93b5d4742f11654b8ae4a7abd409ad06e2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7425
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
2023-02-03 22:48:26 +00:00
Antonio Borneo 92ef27494c target: arc: rewrite command 'arc add-reg-type-flags' as COMMAND_HANDLER
Use a COMMAND_HELPER() to avoid memory leaks when the helper
COMMAND_PARSE_NUMBER() returns due to an error.

While there:
- fix potential SIGSEGV due to dereference 'type' before checking
  it's not NULL;
- fix an incorrect NUL byte termination while copying to
  type->data_type.id and to bitfields[cur_field].name;
- fix some coding style error.

Change-Id: Ide4cbc829871a6a523026ccc0d3100dadc2afd06
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7424
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
2023-02-03 22:48:15 +00:00
Antonio Borneo 18bafdce61 target: arc: fix error handling in command 'arc set-reg-exists'
The command is specified through COMMAND_HANDLER. It should not
return JIM_OK / JIM_ERR.

Change-Id: I56666414d49b0298ecc23ec7ef30c77e1e27afa8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7413
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
2023-02-03 22:47:30 +00:00
Antonio Borneo da76ba610b target: arc: rewrite command 'arc num-actionpoints' as COMMAND_HANDLER
Also drop arc_cmd_jim_get_uint32() that is now unused.

Change-Id: Ic26c3f008376db3f01215bf736fca736dd1c1a4f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7412
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
2023-02-03 22:47:17 +00:00
Antonio Borneo 996d6f383d target: arc: rewrite command 'arc get-reg-field' as COMMAND_HANDLER
This also fixes several incorrect return ERROR_xxx from a jim
command.

Change-Id: I34fe3552d3dc344eac67bf504c5d5709b707fdfd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7411
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
2023-02-03 22:47:01 +00:00
Antonio Borneo f0cb5b0272 target: arc: rewrite command 'arc jtag set-core-reg' as COMMAND_HANDLER
This also fixes an incorrect return ERROR_OK from a jim command.

Change-Id: I72a522645f62b99b313573c8bad6d4f674c5ae53
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7410
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
2023-02-03 22:46:46 +00:00
Antonio Borneo 16af56f600 target: arc: rewrite command 'arc jtag get-core-reg' as COMMAND_HANDLER
This also fixes an incorrect return ERROR_OK from a jim command.

Change-Id: I1f9cf5d1dfa38b8a06042b5f54209e6ee2fc4e0e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7409
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
2023-02-03 22:46:31 +00:00
Antonio Borneo 551d85b123 target: arc: rewrite command 'arc jtag set-aux-reg' as COMMAND_HANDLER
This also fixes an incorrect return ERROR_OK from a jim command.

Change-Id: Iab9bc7c25181341a632f608a8ef2d8b0bea72520
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7408
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
2023-02-03 22:46:19 +00:00
Antonio Borneo 700cdbfac4 target: arc: rewrite command 'arc jtag get-aux-reg' as COMMAND_HANDLER
This also fixes an incorrect return ERROR_OK from a jim command.

Change-Id: I3c51355e7e05965327ce819a3114e370f2de5249
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7407
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
2023-02-03 22:45:56 +00:00
Jan Matyas 2c96555c73 Fix opcode for the "fence" instruction
OpenOCD currently uses improper "fence" instruction:
"FENCE" opcode with empty predecessor and successor sets.

Such instruction has no effect and is reserved for future use
as a HINT instruction (RISC-V Unprivileged ISA spec V20191213,
section 2.9).

This patch fixes it by using the proper "fence rw,rw"
instruction.

Change-Id: Ia2a66059009153efef27279410850ddfd73dae38
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-01 14:59:33 +01:00
Marian Buschsieweke 6e67f1473a helper: Add generic little endian CRC32 function
This generalizes the little endian CRC32 function used in the OR1K
target and moves it to a common helper, so that other places do not need
to reinvent the wheel. It is directly used in the OR1K target.

Change-Id: I0e55340281a5bfd80669bb1994f3a96fecc1248a
Signed-off-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7415
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-21 22:57:33 +00:00
Boris-Chengbiao Zhou 11ee500bff target/armv7m: Rename xPSR to xpsr
The org.gnu.gdb.arm.m-system GDB feature defines the name in lowercase
letters.[1] Not adhering to the definition can cause issues with tools
interacting with the GDB which expect the correct casing.

[1]: https://sourceware.org/gdb/onlinedocs/gdb/ARM-Features.html

Change-Id: I0b6584a78f86b053947d79686baad5dac3ec4a00
Signed-off-by: Boris-Chengbiao Zhou <bobo1239@web.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7292
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:01:03 +00:00
Antonio Borneo f2fc23e16b riscv: drop deprecated command 'riscv test_sba_config_reg'
Change-Id: I51c1b1cb3de8cb86ee38280fa3f035f6f7a63dbc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7272
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
Tested-by: jenkins
2023-01-15 14:56:59 +00:00
Antonio Borneo 27edeb7757 riscv: drop deprecated command 'riscv set_prefer_sba'
Change-Id: I546efe4e1a6b673b26cfb4a74b5c3809fecda49c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7271
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
2023-01-15 14:56:50 +00:00
Tomas Vanek 59763653c6 target/cortex_m: add SMP support for Cortex-M
Cortex-M support for SMP multicore targets.

This SMP implementation unlike older ones does not act
on the first halted target found. It polls targets
until a SMP group is finished and stores eventual
'halted' events instead of emitting them. As soon as polling
of a group is done, poll proceeds with SMP related tasks.
This approach improves detection of a reason why debug
stopped - a correct reason is detected for all targets,
not only for the first found.
Drawback: SMP target group should be defined in the same
order as the targets were defined.

Obsolete gdb 'J' packet/smp_gdb command core switching is not implemented,
use with rtos hwthread.

Only one core is resumed if debug_execution is requested.

Some ideas taken from Graham Sanderson's [4936]
and src/target/aarch64.c

Added error checking of armv7m_restore_context().

Change-Id: I60f5b79e74b624dc2b5835ff10e38ac2ccb23792
Link: [4936]: target/cortex_m: Add smp support for Cortex M | https://review.openocd.org/c/openocd/+/4936
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7239
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 14:54:50 +00:00
Tomas Vanek 083100fca3 target/armv7m: check error in armv7m_restore_context()
Return error if arm.write_core_reg() fails.

Change-Id: Ide8f5aa5958532b202dc9f5e13d3250a706d832d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7238
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 14:54:27 +00:00
Koudai Iwahori d0436b0cda armv8: Add support of pointer authentication
When pointer authentication is enabled, some upper bits of the link
register (LR[63:VA_SIZE]) are used to store a signature. Therefore, GDB
need to remove the signature to get backtraces.
GDB has support of pointer authentication. When pointer authenticaion is
enabled, GDB requests 8-bytes mask to the target to remove the
signature. mask[63:VA_SIZE] should be all set and mask[VA_SIZE-1:0]
should be all cleared. GDB removes the signature by addr&~mask or
addr|mask.
I added a feature to provide the mask for pointer authentication.

Signed-off-by: Koudai Iwahori <koudai@google.com>
Change-Id: I56fbbf9cc23619b6536ecd326f350c8bf137f322
Reviewed-on: https://review.openocd.org/c/openocd/+/7248
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 14:51:44 +00:00
Erhan Kurubas 0708ccead4 target/xtensa: remove needless target_was_examined check
In any case flag will be set as examined.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I5177ee656f726a807269e2f4725223f50e49e855
Reviewed-on: https://review.openocd.org/c/openocd/+/7231
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 14:47:59 +00:00
Antonio Borneo da34e36cdb nds32: drop it, together with aice adapter driver
The target nds32 and its companion adapter aice have not received
any real improvement since 2013.
It has been hard to keep them aligned during the evolution of
OpenOCD code, with no way for maintainers to really check if they
are still working.
No real documentation is present for them in OpenOCD.
The nds32 code triggers ~50 errors/warnings with scan-build.

The arch nds32 has been dropped from Linux kernel v5.18-rc1.

For all the reasons above, this code has been deprecated with
commit 2e5df83de7 ("nds32: deprecate it, together with aice
adapter driver") and tagged to be dropped before v0.13.0.

Let it r.i.p. in OpenOCD git history.

While there, drop from checkpatch list the camelcase symbols that
where only used in this code.

Change-Id: Ide52a217f2228e9da2f1cc5036c48f3536f26952
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7382
Tested-by: jenkins
2023-01-15 14:46:36 +00:00
Marcin Niestroj 7dd5b6a464 rtt: fix corner-cases of finding control block
This patch fixes two corner-cases of finding RTT control block.

The first one is when there was a partial match (even single byte) at
the end of loaded buffer (uint8_t buf[1024]), but this was not part of
full match. In that case `cb_offset` was not updated correctly and the
returned `*address` was lower by the legth of the partial match. In case
of searched 'SEGGER RTT' (the default control block ID) string, it was
enough to match `buf[1023] == 'S'`, which is quite likely to happen, and
the `*address` was offset by 1 (e.g. it was 0x20000fff instead of
0x20010000).

Updating (or even maintaining) `cb_offset` is not needed, as start
address of control block can be calculated based on memory address that
was loaded into `uint8_t buf[1024]`, the offset within this buffer and
the length of expected string.

The second issue is when control block is prepended with a byte that
matches first ID character, e.g. there is `SEGGER RTT` control block ID
is prepended by another `S`, making memory contents be `SSEGGER RTT`. In
that case there was no match found.

Fix that issue by making sure that tested byte is always compared with
first byte of expected control block ID.

While at it, change names of local variables to better describe their
meaning.

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Change-Id: I12aa6e202bf12bedcbb888ab595751a2a2518a24
Reviewed-on: https://review.openocd.org/c/openocd/+/7429
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-11 17:02:25 +00:00
Parshintsev Anatoly 71e3d0aecb target/riscv: added support for missing VCSR register
Change-Id: I0ce7b9e76c613400916c46fad0f19984ea4b482e
2023-01-10 17:41:13 +03:00
Tim Newsome 43ea20dfbb
Merge pull request #777 from riscv/itrigger
target/riscv: Add `riscv` `itrigger` and `etrigger` commands.
2023-01-04 10:31:55 -08:00
Tim Newsome 5a72150604
target/riscv: Remove `riscv test_sba_config_reg` command. (#780)
This command is supposed to be a start at a compliance test for system
bus access. It doesn't pass against spike because it doesn't handle all
cases where the interface might be busy. It's not documented. As far as
I know nobody uses it.

So delete 400 lines of code instead of trying to fix it.

Change-Id: Ib94f2acb95a48f7c07d4f44206ff7373b03857f3
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-03 10:54:33 -08:00
Tim Newsome d2ebfc8770 target/riscv: Use unsigned int for trigger indexes.
Change-Id: I1f7cf3a5c8b86f3d6825f45a67ff05822ea67d28
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-03 10:08:18 -08:00
Tim Newsome 9efa7775d4 target/riscv: Read back tdata2 in set_trigger()
Change-Id: I2a9271c66565a4c93de3322e14be8b75577ed1b6
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-03 10:06:12 -08:00
Tim Newsome 6c027e0df4 target/riscv: Add `riscv etrigger` command.
Change-Id: I7982231c5067b82e4ddb2999bca51dba06ccac7a
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-02 13:54:45 -08:00
Tim Newsome 0b022a349e target/riscv: Add `riscv itrigger` command.
This lets the user set an itrigger trigger, which doesn't fit in the
normal breakpoint abstraction.

This implementation only allows control of a single itrigger. Hardware
could support more than one, and that may be useful to catch different
interrupts in different execution modes. But it would make the code/UI
more complex and it feels like an unlikely use case.

Change-Id: I76c88636ee73d4bd298b2bd1435cb5d052e86c91
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-02 13:54:35 -08:00
Tim Newsome 2258a59a0f target/riscv: Use macros for trigger types.
Change-Id: I6ced3fb5a22bff4694fbceb8cf91f6cf6ce37ebf
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-12-27 12:54:12 -08:00
Antonio Borneo 77c281d2df cortex_m: handle armv8m cores without security extension
Cores armv8m, e.g. Cortex-M33, can be instantiated without the
optional Security Extension.
In this case, the secure registers are not present and when GDB
try accessing them it triggers a set of errors.

For armv8m cores without security extension, don't provide to GDB
the description of the secure registers.

Change-Id: I254478a4cf883e85b786df3f62c726b2f40d88d9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7402
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-12-18 21:52:41 +00:00
Antonio Borneo 2b6fe8f1ab target: fix assert in 'monitor profile' on constant PC
When target is stopped in WFI/WFE or is in an infinite loop, the
sampled PC will always return the same value.
Command 'profile' requires that distance between min and max PC
should be at least 2, which is not the case for constant PC, and
incorrectly enforces the check through as assert().

Move the code that reads the optional parameters 'start' and 'end'
and check the gap 'end - start' before running the profile.
For self-computed min and max, increase max (or decrease min) to
match the required constraint.
Drop the assert().

Change-Id: I2be8df8568ce8c889923888c492e4f7ce354b16b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: https://sourceforge.net/p/openocd/tickets/370/
Reviewed-on: https://review.openocd.org/c/openocd/+/7400
Tested-by: jenkins
2022-12-17 09:32:34 +00:00
Antonio Borneo a51ac964c6 target: fix unsigned computation in 'monitor profile'
The implementation of command 'monitor profile' has few
issues:
- the address_space is a signed int, so cannot wrap-around on
  space over INT_MAX;
- max address is incremented without check for overflow;
- assert() used on errors instead of returning error codes;
- only handles 32 bits PC;
- output file created and left empty on error.

This patch fixes the first two issues, as a wider fix would be too
invasive and should be postponed in a following series.

Change-Id: Id8ead3f6db0fd5730682a0d1638f11836d06a632
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: https://sourceforge.net/p/openocd/tickets/370/
Reviewed-on: https://review.openocd.org/c/openocd/+/7394
Tested-by: jenkins
2022-12-17 09:32:09 +00:00
Antonio Borneo a6b0221952 target: cortex_a: fix clang error core.CallAndMessage
Clang complains about the variable 'orig_dfsr' that can be used
uninitialized both in cortex_a_read_cpu_memory() and in
cortex_a_write_cpu_memory().

The issue is caused by an incorrect error path that used to jump
through 'goto out'. The code after the label 'out' is specific to
handle the case of an error during memory R/W; it is incorrect to
jump there to handle an error during the initialization that
precedes the memory R/W.

Replace the 'goto out' with 'return retval'.
Remove the label 'out' that is now unused.

Change-Id: Ib4b140221d1c1b63419de109579bde8b63fc2e8c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7393
Tested-by: jenkins
2022-12-17 09:31:29 +00:00
Antonio Borneo c6fe10de75 arm_adi_v5: fix SIGSEGV due to failing re-examine
Commit 35a503b08d ("arm_adi_v5: add ap refcount and add get/put
around ap use") modifies the examine functions of mem_ap, cortex_m,
cortex_a and aarch64 by calling dap_put_ap() and then looking again
for the mem-ap and calling dap_get_ap().
This causes an issue if the system is irresponsive and the examine
fails and left the AP pointer to NULL. If the system was already
examined the NULL pointer will cause a SIGSEGV.

Commit b6dad912b8 ("target/cortex_m: prevent segmentation fault
in cortex_m_poll()") proposes a fix for one specific case and only
on cortex_m.

Modify all the examine functions by skipping look-up for the AP if
it was already set in a previous examine; the target's AP is not
supposed to change during runtime.

Remove the partial fix for cortex_m as it is not needed anymore.

Change-Id: I806ec3b1b02fcc76e141c8dd3a65044febbf0a8c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 35a503b08d ("arm_adi_v5: add ap refcount and add get/put around ap use")
Reviewed-on: https://review.openocd.org/c/openocd/+/7392
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-12-17 09:30:45 +00:00
Nima Palizban 2278878a05 src/target/mips_m4k.c: set missing flag in set_watchpoint
Without the fix, will see "Can not find free FP Comparator" error log

Change-Id: Id0d91cc02b7055e44d27507f9c05ccd48ff49838
Signed-off-by: Nima Palizban <n.palizban@gmail.com>
Fixes: fb43f1ff4e (target: Rework 'set' variable of break-/watchpoints)
Reviewed-on: https://review.openocd.org/c/openocd/+/7389
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-12-17 09:29:32 +00:00
Evgeniy Naydanov 04887d3b68 Fix jim_target_smp for smp rtos target
If multiple targets are specified as -rtos <rtos_type>, the
rtos_update_threads was called only if the last target was specified as
rtos, which is inconsistent with other checks of whether or not smp target
is an rtos one.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: Ie52bc6b6c8f841d31b9590fcbc44e985d3cba0eb
Reviewed-on: https://review.openocd.org/c/openocd/+/7244
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-12-03 09:27:00 +00:00
Dolu1990 b337b0cfb4
riscv/run_algorithm : Add support for memory parameters (#773)
* riscv/run_algorithm : Add support for memory parameters

Change-Id: I5045a3843dcd96edb0cf8cc54bbd41969e3260a6
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>

* riscv/run_algorithm : better parameter handeling

Change-Id: If3da8b83f784ef7b13ca83e98bc629e2219cc632
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>

* riscv/run_algorithm : Better mem param error reporting

Change-Id: I09f99ca117f7e5373b23cad0f69d9d5b2a77e61d
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>

Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>
2022-12-02 09:38:40 -08:00
Tim Newsome 86e84d3f6d target/riscv: Set target->state in riscv013_halt_go()
Then also set it when we resume in examine(), which doesn't use the full
abstractions because not all required data structures are filled out
yet.

Hopefully fixes #749.

Change-Id: I0c6ab16da1f035ca2fbdb9f7be1462d44ddce3a0
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-29 09:24:24 -08:00
Tim Newsome 2d7dc3f5f5 target/riscv: Fix small riscv013_halt_go() bug
Exit the loop when no harts are running, instead of when at least one
hart has halted.

Change-Id: Ia69b626bf1fee4034bd5ccc800a651bfe0e53685
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23 13:00:01 -08:00
Tim Newsome 69222be761 target/riscv: RISCV_HALT_BREAKPOINT -> RISCV_HALT_EBREAK
Simple rename to make code slightly more clear.

Change-Id: I959f83164c55de064d902d4e5bcd49333cef5c91
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23 13:00:01 -08:00
Tim Newsome bf15b00315 target/riscv: Set correct target->state in riscv013_halt_go()
It used to set all states to halted, but that's not right for harts that
are now unavailable. (It might be possible to call poll() at the right
time instead of duplicating some of its code, but I didn't see an easy
way to do that. The real requirement is that target->state is set to
TARGET_UNAVAILABLE before TARGET_EVENT_HALTED is is sent in
halt_finish(), because that's what triggers hwthread_update_threads(),
which must know about unavailable harts so they can be hidden from gdb.

Change-Id: I0a0bbdd4ec9ff8c9898e04045b84e1d2512c9336
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23 12:59:58 -08:00
Tim Newsome b1f3a75819 target/riscv: Don't resume unavailable harts.
Change-Id: I30a2e9ec6c1b99fb92ab1a160ddb63682167c6d8
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome d3bffe3d86 target/riscv: Share single-target and SMP resume code.
Change-Id: I416d8cc4c8c5ca0337c1f7e392b6b4fa3d75757f
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome ad93fda7e8 target/riscv: Make poll() use TARGET_UNAVAILABLE.
Change-Id: I7052dd08581f0ce6a05cd8319e9bec0086296fc3
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:47 -08:00
Tim Newsome e5f9024bb0 target/riscv: Refactor riscv_openocd_poll()
There used to be entirely separate code paths depending on whether we're
in SMP mode or not. Now they're both the same.

Change-Id: I8f46295e4bc005f441af0c03d4f608c53b8a6586
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21 10:26:21 -08:00
Tim Newsome 5a48975118 target/riscv: Error when hart becomes unavailable during resume
Change-Id: I731e6178b2b08b65206614b0dc2a0d993c149cc3
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21 10:26:21 -08:00
Tim Newsome cc5e78172a
Merge pull request #769 from riscv/0.11
Revive 0.11 debug spec support
2022-11-21 09:26:38 -08:00
Tim Newsome f1e20767bc target/riscv: 0.11, call handle_halt() after step
This ensures that we populate the register cache and set target->state.
Some RISC-V changes had upset the balance.

Change-Id: I47fbf8ebd8fe39fa5b752212080f87e3b7e6e5e5
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-17 11:41:27 -08:00
Tim Newsome e16d7a5611 target/riscv: Ignore maskmax when reading back tdata1
We don't correctly write it, so we shouldn't expect it to read back the
same value. Fixes hardware breakpoints on mcontrol triggers.

Change-Id: Ie5e445060ec9c8887af933fd8887e57308330f09
2022-11-17 11:41:24 -08:00
Tim Newsome bec0fe2236
target/riscv: Don't always read on DMI batch write (#768)
Indicate to the JTAG driver that it does not need
to read and return the DR register value after scanning the
JTAG chain.

riscv_batch_run(), calls jtag_add_dr_scan() to schedule a
DR scan operation. Eventually, this will result in the JTAG
driver performing a JTAG scan to write to or read from DR.
The decision on whether to write to and/or read from DR
register is determined by the second parameter to
jtag_add_dr_scan(), i.e. a "struct scan_field".
Of particular interest here is if
batch->fields[i]->in_value is not NULL, the JTAG developer
must return the DR value collected from the JTAG  scan
operation.

When creating the DR scan operation instruction with
riscv_batch_add_dmi_write(), batch->fields[i]->in_value points
to a location in batch->data_in buffer,
meaning batch->field[i]->in_value is not NULL, and the JTAG
developer must therefore read and return the DR value collected.
The returning of the DR value is redundant in a write
operation.

This patch set batch->fields[i]->in_value to NULL to indicate
the DR value need not be returned. This allows the JTAG
developer to optimize away any code associated with returning
the DR value.

Normally, the extra work to return the DR value is negligible.
However, in one usecase it introduces significant delays
In this use case a JTAG driver forwards
all JTAG scan to a server on a network. If the server has to
return the DR value, it has to perform the JTAG scan before
replying to the JTAG driver, and only then the JTAG driver
can send the next JTAG scan operation. However, if there is
no need to return the DR value, the server can
acknowledge the JTAG operation request immediately,thus
signalling  to the JTAG driver that it is free to send the next
JTAG scan operation. At the same time of receiving the second
JTAG operation the server will process the original JTAG scan.
This saves time and mitigates network delay. Also, not having
to include the DR value in resulting in smaller reply packet
from server to JTAG driver and save on network traffic.

This doubles download speeds to spike using remote bitbang.

Change-Id: Ibb37c3e32af0cc7006b22b8c4e1f31ed29c21d0f
Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Ooi, Cinly <cinly.ooi@intel.com>
2022-11-17 11:34:27 -08:00
Tim Newsome fc210e8689 target/riscv: Ignore debug_execution in 0.11 resume
It's only used to change what callback events are generated, and there
are none anyway. (That's probably a bug, but since 0.11 is so rare I'm
not going to worry about it.)

Fixes #757.

Change-Id: I5b5df3a9bec927fb0368304229533e2875a83f6b
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-17 09:49:28 -08:00
Evgeniy Naydanov 8ae41e86e1
Fix breackpoint_add for rtos swbp (#734)
breakpoint_add should use rtos only if request is done by gdb.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I779d1a905c6a3640869dca162e3cc001919e8f42

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2022-11-16 11:03:43 -08:00
Tomas Vanek 9d925776b4 target/armv7m: fix feature name of ARMv8M security extension regs
gdb requires this feature to enable stack unwinding of secure/nonsecure
interstate calls and exceptions on an ARMv8M target with
the security extension.

Tested on STM32L5 (Cortex-M33).

Change-Id: Ib09780c011afbc095b352074068597559ad14fcd
Link: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=ae7e2f45aa4798be449f282bbf75ad41e73f055e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7265
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-15 21:39:19 +00:00
Tomas Vanek 6939187853 target/armv7m: prevent saving and restoring non existent regs
armv7m_start_algorithm() saves register values to arch_info->context.
armv7m_wait_algorithm() restores register values from arch_info->context.
Exclude registers with flag exist = false from both loops.

While on it refactor the register restore: introduce 'struct reg' pointer
and dereference it instead of numerous accesses by a full path
from armv7m pointer.

Change-Id: I1600084db84809ee13bcf8e7828b79f8c9ff9077
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7276
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-15 21:30:07 +00:00
Evgeniy Naydanov dc49ed8ae2
Workaround for fp register access in case fp unit is disabled (#766)
On some boards there is a HW bug: if fp unit is disabled (fs in mstatus
set to 0), accessing any fp register results in a hang (any abstract
command timeouts, untill the board is rebooted).

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I0c0d1033889f15dcc326c4078bf9cbb5a8558565

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2022-11-15 08:52:13 -08:00
Antonio Borneo 5fc4882b80 dsp5680xx: fix clang error core.UndefinedBinaryOperatorResult
Clang get confused by initializing the array uint16_t lock_word[],
casting it to (uint8_t *), then accessing the second element of
the uint8_t pointer.

  src/target/dsp5680xx.c:2046:41: warning: The left operand of '<<'
    is a garbage value [core.UndefinedBinaryOperatorResult]
        uint16_t tmp = (buffer[0] | (buffer[1] << 8));
                                     ~~~~~~~~~ ^
Fix it by replacing the array with a single uint16_t.

The code is still depending on host endianness; no fix for this is
proposed.

Change-Id: I16dfd60cab117dd145aeecf10d9593574ff233a2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7302
Tested-by: jenkins
2022-11-11 20:11:22 +00:00
Antonio Borneo 0946e80407 esirisc_jtag: fix clang error core.VLASize
The function esirisc_jtag_recv() can be called with argument
num_in_fields = 0, for example as consequence of calling
esirisc_jtag_continue().
In this case, num_in_bytes is zero and the allocation of the
variable-length array 'r' requires size zero.

  src/target/esirisc_jtag.c:133:2: warning: Declared variable-length
    array (VLA) has zero size [core.VLASize]
        uint8_t r[num_in_bytes * 2];
        ^~~~~~~~~ ~~~~~~~~~~~~~~~~

Fix it by forcing size one when num_in_bytes is zero.

Change-Id: Id764c7b5ec4f5b3c18c7da650bbff39fc98ed049
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7301
Tested-by: jenkins
2022-11-11 20:11:03 +00:00
Antonio Borneo 7a09635735 openrisc: fix clang error core.CallAndMessage
Clang assumes that size could assume a value that is not 1 nor 2
nor 4. In such condition the buffer in t is allocated (size != 1)
and not initialized. This triggers an error:
  src/target/openrisc/or1k_du_adv.c:655:14: warning: 2nd function
    call argument is an uninitialized value [core.CallAndMessage]
                crc_calc = adbg_compute_crc(crc_calc, data[i], 8);
                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Add the default case to cover other values of size.

After this fix, clang still complains on the same line, this time
misunderstanding the limits of the loop and considering that
buf_bswap16() only swaps the first 16 bits, thus passing not
initialized value data[2] to adbg_compute_crc()

Replace malloc() with calloc() to silent it.

Change-Id: I358d7fb2ebefd69255670641bd435b770762a301
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7300
Tested-by: jenkins
2022-11-11 20:10:41 +00:00
Tim Newsome f59bb72fde
target/riscv: Use vlenb to check whether vector registers exist (#762)
E.g. the Zve* vector extensions have all the same registers as the full
V extension, but leaves misa.V clear.

Change-Id: Ib08c3612c52bb3a6b074d9431e3396c8f2f0ff27
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-10 10:27:46 -08:00
Tim Newsome 88a629c017
riscv/target: Replace is_halted() with get_hart_state() (#756)
Prep work for handling unavailable harts.

Change-Id: I9c00ed4cdad8edeaa5a13fbec7f88f40d8af9028
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-10 10:27:04 -08:00
Xiang W 61f183fb25
Use match field for trigger (#725)
* Use match field for trigger

The watchpoint cannot capture all data modifications only through the
trigger of ANY SIZE and EQUAL, and an error will occur. This patch
accommodates watchpoints by adding more types of matches

Change-Id: I5c3c908dbd49ca47755b06f5cdbe451be3a81c8b
Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Change-Id: I3670347c4b00bf508373f7cc2f4950cbc09d6e2a
Signed-off-by: Xiang W <wxjstz@126.com>

* Add variable type trigger support

Change-Id: I60922c5f98574040b9a160e2aa0355871a581fe1
Signed-off-by: Xiang W <wxjstz@126.com>

* remove trailing whitespace

Change-Id: I168812e12b459ae3c4b3017c27a9b897e65d9f84
Signed-off-by: Xiang W <wxjstz@126.com>

* update triggers enumerate

Change-Id: I23a66afb0f772934b8911b522d0e4f116917519f
Signed-off-by: Xiang W <wxjstz@126.com>

Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-11-09 14:48:31 -08:00
Tim Newsome ae3ad22311
target/riscv: Deal with DMI busy in sample_memory_bus_v1() (#758)
* target/riscv: Deal with DMI busy in sample_memory_bus_v1()

Change-Id: I810a4c4b7f02cb40ea99b7a500dce23c1bbd9231
Signed-off-by: Tim Newsome <tim@sifive.com>

* Comment code more clearly.

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

* Remove extra tab

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-11-09 14:39:19 -08:00
Dolu1990 70980e7f57
Fix dm->current_hartid corruption on hartsellen discovery (#754)
* target/riscv Fix dm->current_hartid corruption on hartsellen discovery

Change-Id: Iec969df2675b608365eda2c3a83a4185752430f2
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>

* target/riscv Ensure HART_INDEX_DIRTY does not have side effects

Change-Id: Ie89c94d97cd4f15c1be0327fddff75beea6ae027
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>

Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
2022-11-01 09:51:33 -07:00
Tim Newsome fad123a16b
target: Add TARGET_UNAVAILABLE state. (#752)
This is added for future RISC-V changes. The RISC-V debug interface can
explicitly tell a debugger when a hart is unavailable. This is used for
instance when that hart is powered down (or yet to be powered up out of
reset).

Change-Id: I8a062d59eea1e5b3c788281a75159592db024683
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-27 15:21:31 -07:00
Erhan Kurubas 535de48ca6 target/xtensa: remove redundant call for `TARGET_EVENT_HALTED`
`xtensa_do_step` is invoked from `xtensa_prepare_resume` to silently
step over BP/WP before resuming.
For example; in the case of WPs (DEBUGCAUSE_DB), in the current
implementation `xtensa_do_step` will generate one more
`TARGET_EVENT_HALTED` after the original one caused by WP itself.

This patch moves the halted event cb call after
the step is done successfully.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9048e14fb316dc124847a42cfaefb1f76b5ce53e
Reviewed-on: https://review.openocd.org/c/openocd/+/7274
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-21 18:16:23 +00:00
Antonio Borneo b8735bbf7e doc: fix riscv commands
- Fix the declaration of riscv command 'set_mem_access'.
- Remove non existing riscv command 'set_scratch_ram'.
- Add riscv commands 'info', 'reset_delays'; copy the description
  from the 'help' text.
- Don't add riscv commands 'set_prefer_sba' and 'test_sba_config_reg'
  as they are marked as deprecated.
- Ensure that 'test_sba_config_reg' prints a deprecation warning
  when used.

Change-Id: I39dc3aec4e7f13b69ac19685f1b593790acdde83
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7268
Reviewed-by: Tim Newsome <tim@sifive.com>
Tested-by: jenkins
2022-10-21 18:14:46 +00:00
Tim Newsome 9eb07f258e
target/riscv: Correctly set target->state in deassert_reset (#750)
* target/riscv: Correctly set target->state in deassert_reset

This bug didn't lead to problems, but it would with some upcoming
changes.

Change-Id: I552acbae9977150c4c9e573f8852033bc80fcebb
Signed-off-by: Tim Newsome <tim@sifive.com>

* Keep debug_reason in sync with state

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-10-21 09:16:54 -07:00
Erhan Kurubas 3b8333bd3f target/xtensa: fill register number field in the cache
Currently 'number' field is zero in the register cache and
this causes an issue on `rtos get_thread_reg_list` calls.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Iaef11e01f55d012969bbc1933f82847d5e02fec5
Reviewed-on: https://review.openocd.org/c/openocd/+/7246
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-15 15:58:44 +00:00
Erhan Kurubas 2d5d8a5a62 target/esp32s2: check xtensa_poll return value
Although scan build couldn't catch, return value overwritten
without checking.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I02b10002b03640604315047e8a8a639824724c16
Reviewed-on: https://review.openocd.org/c/openocd/+/7247
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-15 15:57:57 +00:00
Anatoly Parshintsev fe5c7d7a35
[riscv] step operation handler should respect handle_breakpoints parameter (#741)
* [riscv] step operation handler should respect handle_breakpoints parameter

When step operation is requested the OpenOCD frontend (like gdb server
or TCL server) has an option to control how existing breakpoints are
handled upon step.

Some OpenOCD frontends (like gdbserver) may choose to disable special
handling of existing breakpoints - thus handle_breakpoints is set to 0,
while others (like TCL server) expect target handler to temporary
disable the matching breakpoint to allow the step operation to complete
successfully.

In the current implementation handle_breakpoints parameter was ignored
by target-specific handler. Thus, the following sequence of commands:

```
halt
bp <current_pc> 4
step
```

Resulted in *step* operation to not change PC because of bp match.

This commit addresses this issue.

* Adjusted calls to logging facilities (addressed review comments)

Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>

Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Co-authored-by: Tim Newsome <tim@sifive.com>
2022-10-14 09:40:16 -07:00
Tim Newsome a50b280558
Properly track selecting multiple harts at once. (#743)
* Properly track selecting multiple harts at once.

use_hasel is a bit of a hack.

Change-Id: Ia589ebc16bca32038d915df9988361b88e940917
Signed-off-by: Tim Newsome <tim@sifive.com>

* Clarifying comment.

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

* Rename set_hartsel to set_dmcontrol_hartsel

Change-Id: Iab28531281aa6fc604ec7d34974ed444ea9ea850

* Make set_dmcontrol_hartsel() more idiomatic.

Change-Id: I56a885043c515359e33b9c8a03aed637c81d1486

* Use constant for multiple harts instead of -1.

Change-Id: Iefeaf74202f2b4918d21f15f7ff7ca514175b8fb
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-10-12 08:57:00 -07:00
Tim Newsome 4270857a76 target/riscv: Clean up halt_go for multiple harts.
Also add an early exit for if any harts are unavailable.

Change-Id: I0875d4d213c9faf87b219d8d57e440881366c8f8
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-11 13:57:55 -07:00
Tomas Vanek dc6cad855d target: re-examine before arp_waitstate in ocd_process_reset_inner
arp_waitstate will not work on not-examined state

Change-Id: I56c3e1c7e63af108e4ed1dbacebb567f9bf46264
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7230
Tested-by: jenkins
Reviewed-by: Erwan Gouriou
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 08:53:51 +00:00
Tomas Vanek 1f84f34850 target/hla_target: try to re-examine under reset in hl_assert_reset()
An application often idling in real sleep mode may make a Cortex-M target
hard to access as CPU clock are gated and debug requests are responded
by WAIT ack.

Try to examine the target under reset as the last resort.

Change-Id: I7c3de39fb1e6c23b76e2a0a85ab75f23aac94c4d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7229
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 08:52:45 +00:00
Tomas Vanek f65d1da013 target/cortex_m: try to re-examine under reset in cortex_m_assert_reset()
An application often idling in real sleep mode may make a Cortex-M target
hard to access as CPU clock are gated and debug requests are responded
by WAIT ack.

Try to examine the target under reset as the last resort.

Change-Id: Ife875a966a838c37dde987bc584ad0a1f4d020d6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7228
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 08:49:52 +00:00
Tomas Vanek b991c416b7 target/cortex_m: make reset robust again
After merging [1] 'reset halt' does not work on not responding Cortex-M.

Relax the examined tests and try to set vector catch VC_CORERESET
if debug_ap is available.

While on it add an info about examination state to debug logs.

Fixes: [1] commit 98d9f1168c ("target: reset target examined flag if target::examine() fails")
Change-Id: Ie2e018610026180af5997d70231061a275f05c76
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6745
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 08:46:12 +00:00
Daniel Goehring a69b382efd target/adiv5: 64-bit TAR setup bugfix
For 64-bit TAR setup, if 'tar_valid == false' perform the upper 32-bit
write even if the cached copy matches the upper TAR value to be written.

Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Change-Id: I320377dc90a9d1d7b64cbb281b2527e56c7621ee
Reviewed-on: https://review.openocd.org/c/openocd/+/7245
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2022-10-08 07:55:35 +00:00
Erhan Kurubas cff2cf373f target/xtensa: pass correct buffer on read memory retry
Read values must be at albuff so that can be copied to buffer
on function exit.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I74a533e8f12f1002ca06a98a7c7cd928552b4cc5
Reviewed-on: https://review.openocd.org/c/openocd/+/7226
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 07:53:12 +00:00
Erhan Kurubas 10b08d5ac5 target/xtensa: rename pc and ps macro names
Actually they are the base of epc and eps

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I4f43b9609a9929399fb5d3fa0203efc8a98e94c9
Reviewed-on: https://review.openocd.org/c/openocd/+/7227
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 07:52:49 +00:00
Tomas Vanek 48507e3b10 target/armv7m: show target name in 'halted' message
Change-Id: I13e9a33677632d52122585203252fc4ef0c52a2a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7237
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08 07:47:09 +00:00
Tomas Vanek bced97cce9 target/armv7m: prevent storing invalid register
armv7m_start_algorithm() stored all non-debug execution
registers from register cache without checking validity.

Check if the register cache is valid.
Try to read from CPU if not valid.
Issue a warning if register read fails.

Change-Id: I365f86d65243230cf521b13909575e5986a87a50
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7240
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
2022-10-08 07:46:16 +00:00
Dmitry Ryzhov 01ae0f2122 Fix incorrect braces caused by #732 2022-10-07 16:34:59 +03:00
Tim Newsome 0f12a01007 riscv: Minor formatting cleanup.
Change-Id: I0256fd047d8369ca7b327172225a9d1f827673c5
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-05 10:23:45 -07:00
Tim Newsome 84365e65e5 Remove riscv_info_t.current_hartid
This was used to track which hart a given operation must apply to. But
we already have a target associated with each operation, and from there
we can find the desired hart id. dm013_info_t already tracks
current_hartid (meaning which hart ID is currently selected by the DM).

This makes the code simpler to understand. Also it turns out we don't
need to make sure the correct hart ID is currently selected because
there are only a few real entry points.

Change-Id: Ibe8d5e156523397f245edd6ec0a5df3239b717bf
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-30 10:21:38 -07:00
Tim Newsome 550a66e720
Use LOG_TARGET_FOO() functions in more places. (#731)
Change-Id: Id2266dbfb6209bf0676f28e7383a12705ce2a70e
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-29 15:09:49 -07:00
Tim Newsome 23df83e830
Merge pull request #727 from riscv/poll_backoff
Make poll backoff time based.
2022-09-27 10:13:12 -07:00
Tim Newsome e53fd14f50
Merge pull request #733 from en-sc/en-sc/remove-erroneous-debuglog
Remove incorrect debug_log in wait_for_idle
2022-09-27 10:00:40 -07:00
Tomas Vanek 5f14140953 target/adi_v5_swd: suppress reconnect in swd_multidrop_select()
swd_multidrop_select() uses its own retry loop.
If select fails, do_reconnect flag remains set on exit and causes
useless reconnect.

Clear do_reconnect flag in retry loop.

Change-Id: Ie06d6967d7f4a977774c8530bb8d4b3e5ab4f62c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7217
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Tested-by: jenkins
2022-09-27 08:29:00 +00:00
Tomas Vanek b2f6b23117 target/adi_v5_swd: fix SWD multidrop
Implementation of ADI v6 introduced banking of DP reg 0.
The accompanying change preventing DP SELECT write before
DP IDR read during connect was added to swd_connect_single() only.
Unchanged swd_connect_multidrop() / swd_multidrop_select_inner()
was broken as it emited DP SELECT and put DP to protocol error state.

Copy dap->select handling to swd_multidrop_select_inner().

Fixes: 72fb88613f (adiv6: add low level swd transport)

Change-Id: I514cd6d9ae2ba97ce3657b459df22638c278a0b1
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7213
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
2022-09-27 08:28:44 +00:00
Evgeniy Naydanov fb7c8b310a Remove incorrect debug_log in wait_for_idle
According to RISC-V External Debug Support Version 0.13.2 (paragraph
3.12.6), cmderr field contains a valid value only if busy is 0, so it is
incorrect to analize it on timeout.
2022-09-26 13:52:53 +03:00
Evgeniy Naydanov 137141249b Propagate error code in register_read/write_direct
In some cases error code returned by riscv_program_insert was ignored
2022-09-26 13:37:45 +03:00
Daniel Goehring 1293ddd657 target/target: read_memory 64-bit bugfix
Increase "value_buf" size so it can hold a 64-bit number represented
as a string. Previous size could only hold a 32-bit number string.

Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Change-Id: If6fbc875236e6ddc59522fbc25db0129eb60ee27
Reviewed-on: https://review.openocd.org/c/openocd/+/7221
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-23 21:26:44 +00:00
Ian Thompson 53d17e7901 target/xtensa: fix final clang analyzer warning
Reworked xtensa_read_memory() logic to always allocate
and initialize working buffer with sufficient padding.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: Ia9ab53336537adebf99f8156f481ca8279a7cd5d
Reviewed-on: https://review.openocd.org/c/openocd/+/7211
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2022-09-23 21:25:34 +00:00
Antonio Borneo 44ed26a1db target/riscv: fix use of uninitialized value
Scan-build reports:
	Logic error: Uninitialized argument value
	riscv.c:2688 2nd function call argument is an uninitialized value

This is a real error cause by running the command "riscv
authdata_write" without arguments. In such case 'value' is not
initialized and is passed to and used by r->authdata_write().

Reorganize the code to:
- detect the correct amount or command's arguments;
- drop the LOG_ERROR() on ERROR_COMMAND_SYNTAX_ERROR;
- drop the 'else' after 'return'.

Change-Id: I62e031220593b8308bc674b753e15d16d4c5c9ac
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7210
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
2022-09-23 21:25:08 +00:00
Antonio Borneo fd2a44ab55 target/riscv: fix undefined operation
Scan-build reports:
	Logic error: Result of operation is garbage or undefined
	riscv.c:1614 The result of the left shift is undefined due
		to shifting by '4294967281', which is greater or
		equal to the width of type 'target_addr_t'

This is a false warning due to clang that considers the impossible
case of 32 bits hart (xlen = 32) in SATP_MODE_SV48 mode
(info->va_bits = 48).
Under such case:
	riscv.c:1614 ... ((target_addr_t)1 << (xlen - (info->va_bits - 1))) ...
the shift amount wraps around the unsigned type and assumes the
value 4294967281 (0xfffffff1).

Use assert() to prevent clang from complaining.

Change-Id: I08fdd2a806c350d061641e28cf15a51b397db099
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7209
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
2022-09-23 21:24:49 +00:00
Antonio Borneo aff48a6a31 target/riscv: fix dead assignment
Scan-build reports:
	Unused code: Dead nested assignment
	riscv.c:459 Although the value stored to 'ir_user4_raw' is
		used in the enclosing expression, the value is
		never actually read from 'ir_user4_raw'

This is caused by the value reassigned in 'ir_user4_raw':
	riscv.c:459 ir_user4[3] = (uint8_t)(ir_user4_raw >>= 8);
but never used.

Drop the DIY conversion in favor of h_u32_to_le() that does not
reassign the input value.

Change-Id: Ifad29f4c46d4a2d0a2f5a5c4104d768cc3db2794
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7208
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
2022-09-23 21:24:41 +00:00
Antonio Borneo ea9089944e target/riscv: fix unused initialization
Scan-build reports:
	Unused code: Dead assignment
	riscv.c:716 Value stored to 'result' is never read

Remove the initialization of variable 'result'.

Change-Id: Ied67bb4fcfa5bace186522074247ead43a5d5cd5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7207
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
2022-09-23 21:24:34 +00:00
Antonio Borneo aa57890554 target/riscv-013: fix unused initialization
Scan-build reports:
	Unused code: Dead initialization
	riscv-013.c:2362 Value stored to 'control' during its
		initialization is never read

Remove the initialization of variable 'control'.

Change-Id: I548f8175530b9a2aa4c1788549d6467bf9824584
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7206
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
2022-09-23 21:22:42 +00:00
Antonio Borneo 8db6dff333 target/riscv-013: fix unchecked return code
Scan-build complains about variable 'sbcs_orig' that can be used
not initialized.
	Logic error: Assigned value is garbage or undefined
	riscv-013.c:4468 Assigned value is garbage or undefined
This is caused by not checking the return value of the call
	riscv-013.c:4466 dmi_read(target, &sbcs_orig, DM_SBCS);
In fact when dmi_read() returns error, the variable 'sbcs_orig' is
not assigned.

Check the returned value.

Change-Id: Ia9032a0229aa243138f95f4e13f765726a4ceae9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7205
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
2022-09-23 21:22:31 +00:00
Antonio Borneo 8683526af7 target/dsp563xx: fix scan-build warning
Scan-build triggers a warning:
	Unix API: Allocator sizeof operand mismatch
	dsp563xx.c:2143 Result of 'calloc' is converted to a pointer
		of type 'uint8_t', which is incompatible with sizeof
		 operand type 'uint32_t'

It's a false positive because calloc() is properly used in this
case, as the uint8_t array is used in blocks of 4 elements to read
or write uint32_t values.

Either
	calloc(sizeof(uint32_t), count);
and
	malloc(count * sizeof(uint32_t));
keep triggering the same warning.

Drop the warning by using the constant '4' as size of uint32_t, as
already used few lines below.

Change-Id: I5bb1ece177774eefdc5d9cd049338f8f2be87cd7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7203
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2022-09-23 21:22:09 +00:00
Tim Newsome 3c5be531df Don't use const on temporary variable.
It's not part of OpenOCD style:
https://review.openocd.org/c/openocd/+/6319/5..10/src/target/aarch64.c#b1500

Change-Id: Ifb612a942507ca5ed8cac3e3ec59e0e14b0298ed
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-22 09:59:15 -07:00
Tim Newsome b7738370b7 Make large if() more readable.
Change-Id: Ie43400387ab9f290e744ebaa09786612237e6c7e
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-19 09:48:09 -07:00
Tim Newsome fa1abc63d2
Add explanatory comment.
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-19 09:44:10 -07:00
Tim Newsome 89746e111b
Fix comment indent.
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-19 09:43:51 -07:00
Antonio Borneo 382148e4dd openocd: fix SPDX tag format for files .c
With the old checkpatch we cannot use the correct format for the
SPDX tags in the file .c, in fact the C99 comments are not allowed
and we had to use the block comment.

With the new checkpatch, let's switch to the correct SPDX format.

Change created automatically through the command:
	sed -i \
	's,^/\* *\(SPDX-License-Identifier: .*[^ ]\) *\*/$,// \1,' \
	$(find src/ contrib/ -name \*.c)

Change-Id: I6da16506baa7af718947562505dd49606d124171
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7153
Tested-by: jenkins
2022-09-18 08:22:01 +00:00
Ian Thompson 61d0757acf target/xtensa: invalidate register cache on reset
Resolves issues where registers are accessed when poll() logic is inactive or has not yet been triggered.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: If7a4d00938fb188b008325249627f7773c3484c5
Reviewed-on: https://review.openocd.org/c/openocd/+/7197
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-18 08:12:02 +00:00
Ian Thompson 27e7f5df5f target/xtensa: fix clang analyzer warning
Reworked xtensa_queue_exec_ins_wide() logic to properly handle endian issues while executing arbitrary instructions.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I5752dd254ce8b8822886ffc7edecaa242a93cce8
Reviewed-on: https://review.openocd.org/c/openocd/+/7198
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-18 08:05:47 +00:00
Ian Thompson 4279b23fca target/xtensa: populate PS correctly during fetch
Read PS from EPS[debuglevel] during fetch such that it reflects the correct value when read via telnet (not just via gdb_server).

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I8504f68989bc6d5fe451a8cb69d01c86f4ec0100
Reviewed-on: https://review.openocd.org/c/openocd/+/7195
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-17 20:57:26 +00:00
Tim Newsome 4004db5d3a Make polling_interval unsigned.
Hopefully fixes win32 build.

Change-Id: I13d6d475f03bada96b2eb943f2c16df05413d34f
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-16 16:52:11 -07:00
Tim Newsome 639e68a621 Make poll backoff time based.
Requested in https://review.openocd.org/c/openocd/+/6964.
I'm making the change here so I have a chance to test it properly before
pushing it upstream.

A nice effect of this change is that we avoid some unnecessary polling
early on when gdb is connecting and we would poll once every time we
send gdb a qXfer packet.

Change-Id: I4bdb9f05839e8c1e01ff6dde49d6589595418095
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-16 15:19:21 -07:00
Antonio Borneo cec3b62328 mips64: remove empty mips_mips64_soft_reset_halt()
The method soft_reset_halt is optional; no need to add an
empty function.

Remove mips_mips64_soft_reset_halt() and move the TODO comment
in struct target_type.

Change-Id: Id541a75e7a08645568961d59b73a120c2238701f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7184
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-09-13 22:19:13 +00:00
Ian Thompson 58bd387219 target/xtensa: fully initialize buffers for PWRSTAT read
Read buffer is sized for 32-bit APB version of PWRSTAT/PWRCTL registers. Initialize to zero so 8-bit JTAG register mirrors are accurate.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I81310649fa7180893d0188aab3c8a14315aaea0a
Reviewed-on: https://review.openocd.org/c/openocd/+/7183
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-13 22:18:57 +00:00
Antonio Borneo 5d6be673c3 target: don't export local symbols
Symbols that are not used outside the file should not be exported
and should be declared as static.

Change-Id: Icbe7f7bce287b903edec9dc9db3370722c51fbd5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7173
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-09-13 22:13:58 +00:00
Antonio Borneo 933cbd9156 riscv: don't export local symbols
Symbols that are not used outside the file should not be exported
and should be declared as static.
Move the existing comments to the static declarations.

Change-Id: Idf208e3fda4b3f8df789553cf03ebf5f20d811bb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7170
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
Tested-by: jenkins
2022-09-13 22:12:29 +00:00
Antonio Borneo 07d84bca32 target: make local symbols static
Symbols that are not exported should be declared as static.

Change-Id: I2475524f4c14520e3163572560f4a9f276356ed5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7168
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-09-13 22:11:46 +00:00
Antonio Borneo a21489e9b9 xtensa: make local symbols static
Symbols that are not exported should be declared as static.

Change-Id: Ieb627f7f896e4663b0d5b18c4ab1853b39d23d03
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7167
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Tested-by: jenkins
2022-09-13 22:10:57 +00:00
Antonio Borneo 8310a238dc riscv: make local symbols static
Symbols that are not exported should be declared as static.

Change-Id: Ie3bd17535c8cb2a0fec5d3bedfe7de3e0a702613
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7166
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
2022-09-13 22:10:42 +00:00
Ian Thompson abe5f015c5 target/xtensa: fix step state transition
For some configurations, notably on DAP systems, resolve issue where single-stepping does not always transition into the HALTED state.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I053f4eaffad8c3228878ba87580ada640e4bd2fe
Reviewed-on: https://review.openocd.org/c/openocd/+/7150
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-13 22:09:02 +00:00
Ian Thompson b2b514be5b target/xtensa: enable DAP/SWD for generic xtensa
- Enable ADIv5 DAP systems via JTAG or SWD transport
- Select correct PWRCTL/PWRSTAT bits for XDM/APB

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I5894210c804f85075da868d0cfc6fb20b589d99f
Reviewed-on: https://review.openocd.org/c/openocd/+/7144
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-13 22:08:14 +00:00
Antonio Borneo 0c6e0bb82b openocd: remove CamelCase symbols *xPSR*
We have left the camelcase symbols *xPSR* for some time, to avoid
any conflict with possibly pending patches in gerrit.
With the approaching v0.12.0-rc1, it's time to revisit it.
The patches in gerrit that conflict with this rename are all not
merge-able due to conflicts or due to negative review.

Drop these CamelCase symbols.

Change-Id: Ifbac4c1df9cc55994e024971a2aaebeed2ea4ed3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7155
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-09-13 22:03:02 +00:00
Antonio Borneo de5c32fe23 openocd: remove recently added CamelCase symbols
Without the help of checkpatch, some CamelCase symbol passed
through the filter of maintainer's review.

Drop them.

Change-Id: If5fb07b2ffb89e853dd2a61f20d4134aa6e20d24
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 48f267d4ad ("flash/stm32l4x: avoid using magic numbers for device ids")
Fixes: 5ab74bde06 ("semihosting: User defined operation, Tcl command exec on host")
Reviewed-on: https://review.openocd.org/c/openocd/+/7154
Tested-by: jenkins
2022-09-13 22:02:33 +00:00
Tim Newsome 8832d4be97 Add error message when dmstatus read times out.
Otherwise OpenOCD simply doesn't work without giving any indication why.

Change-Id: I21703fc1a0d9bed2f59da95f8a8395fe139484a4
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-13 10:18:39 -07:00
Tim Newsome 911d68ef25
Don't read dmcontrol to set hartsel (#723)
* Don't read dmcontrol to set hartsel

We already know what dmcontrol should be. This addresses a long-standing
TODO. In a toy test, this reduced the number of scans by 10+%. (Most of
those are probably in poll(), so don't actually affect perceived
performance.)

Change-Id: I18e5ca391f0f5fb35f30d44dfef834e5a66aee20
Signed-off-by: Tim Newsome <tim@sifive.com>

* Make code easier to read

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-09-09 09:57:39 -07:00
Ian Thompson de99836cf6 target/xtensa: virtualize XDM registers
Use indirect enum IDs to access XDM registers in preparation for supporting both NAR (JTAG) and APB (DAP).  No new clang static analysis warnings.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I0b742fe4661ff3cf609454b8650493d141a1e1ff
Reviewed-on: https://review.openocd.org/c/openocd/+/7143
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-08 09:32:23 +00:00
Erhan Kurubas bea4d65903 target/espressif: add semihosting support
ARM semihosting + some custom syscalls implemented for
Espressif chips (ESP32, ESP32-S2, ESP32-S3)

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ic8174cf1cd344fa16d619b7b8405c9650e869443
Reviewed-on: https://review.openocd.org/c/openocd/+/7074
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-03 21:27:17 +00:00
iysheng 7dc4be3157 target/arm: Add support with identify STAR-MC1
Tested with an PLUS-F5270 board which uses the MM32F5277E9PV.

Signed-off-by: iysheng <iyysheng@gmail.com>
Change-Id: Icb75ae8337fdc6fa60e39d3d74dd8bc163707bdd
Reviewed-on: https://review.openocd.org/c/openocd/+/7136
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-03 21:26:20 +00:00
Tim Newsome a527112dae target/riscv: Update with latest encoding from riscv-opcodes
This gets us a clearly labeled BSD-3-Clause header, which should be
compatible with OpenOCD and Fedora, and also make it clear what the
license actually is.

See https://github.com/riscv/riscv-openocd/pull/710,
https://github.com/riscv/riscv-openocd/pull/713, and
https://github.com/riscv/riscv-openocd/pull/717.

Change-Id: I992b4f3bb230edb9f281e2278dd41c712098ed4c
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7084
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-27 16:21:15 +00:00
Ian Thompson d93ac5482a target/xtensa: fix clang analyzer warnings
Scan-build of target/xtensa/ has no clang analyzer warnings from xtensa source files.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I11a125c923ece9a6fd0d9ee1698f742f88ee5cab
Reviewed-on: https://review.openocd.org/c/openocd/+/7141
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-27 16:20:44 +00:00
Tim Newsome 7c0ca4dd53
Add copyright line to encoding.h. (#718)
Hopefully this will be the final version.

Change-Id: Ib2f8cd6f613c5e0f8e8bf7a16c3edbf2d9b439b2
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-08-25 11:04:46 -07:00
Tim Newsome 7a16947969
encoding.h license changed to BSD-3-Clause (#717)
See https://github.com/riscv/riscv-opcodes/pull/139

Change-Id: I77ae5ab369e6cde26ad44d177dcae38c0fbe08ef
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-08-22 08:56:44 -07:00
Erhan Kurubas f77c919cf4 target/xtensa: fix clang analyzer warnings and gcc12 build errors
Fix Unused code	Dead assignment at line 657
Fix Memory error Double free at line 2851
Fix Memory error Memory leak at line 2530
Fix error: 'a3' may be used uninitialized at line 758
Fix error: '%04x' directive writing between 4 and 8 bytes
into a region of size 5 at line 2471

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I0382a622bc7c4108a335fd741816577e79240397
Reviewed-on: https://review.openocd.org/c/openocd/+/7137
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-21 22:04:07 +00:00
Ian Thompson ce5ca9f7ba target: add generic Xtensa LX support
Generic Xtensa LX support extends the original Espressif/Xtensa
patch-set to support arbitrary Xtensa configurations, as defined in
a core-specific .cfg file.  Not yet fully-featured.  Additional
functionality to be added:
- Xtensa NX support
- DAP/SWD support
- File-IO support
- Generic Xtensa multi-core support

Valgrind-clean, no new Clang analyzer warnings

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I08e7bf8fa57c25b5d0cb75a1aa7a2ac13a380c52
Reviewed-on: https://review.openocd.org/c/openocd/+/7055
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-20 15:38:41 +00:00
Erhan Kurubas c271958850 target/semihosting: drop type casting from semihosting->result
Also used type helper (PRId64) to specify format of int64_t

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I594863eab594aff621c26fefcc69a1872e9730ee
Reviewed-on: https://review.openocd.org/c/openocd/+/7111
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-20 15:27:46 +00:00
Tim Newsome fb523552d2
Update encoding.h again. (#713)
Now we get the license comment on the first line, which is required.

Change-Id: I54414db3c89ee6027e159ce9348459bc923b8595
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-08-18 10:10:49 -07:00
Erhan Kurubas 9cd714cd14 target/espressif: remove author lines from esp32xx and xtensa files
Some files have author info some doesn't. For the consistency we removed all.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ie6f1ec012302e3a954c75c5106f12820722cb715
Reviewed-on: https://review.openocd.org/c/openocd/+/7104
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-15 13:27:10 +00:00
Tomas Vanek 3adbec9aab target/cortex_m: supress historical reset detection
The S_RESET_ST sticky bit is reset after DHCSR read.
It is set at power-on reset and keeps active until the debuger reads DHCSR.

Ignore S_RESET_ST at the very first read after OpenOCD start
and suppress possibly misleading message "external reset detected"
if we cannot guarantee the reset happened recently.

While on it add a TODO comment.

Change-Id: I15217c2ca6f69ac97aff8be86bce67cba94a42cd
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7109
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-15 13:23:57 +00:00
Ian Thompson 48db36f436 gdb_server: custom target-specific GDB queries
Provide a customizable hook for handling target-specific GDB queries

Valgrind-clean, no new Clang analyzer warnings

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I684a259ed29f3651cbce668101cff421e522f79e
Reviewed-on: https://review.openocd.org/c/openocd/+/7082
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-15 13:23:05 +00:00
Antonio Borneo 0d56f379b5 target: add API to temporarily mask target polling
The same flag 'jtag_poll' is currently used as local data for the
command 'poll' and to temporarily mask the target polling.
This can cause unexpected behavior if the command 'poll' is
executed while polling is temporarily masked.

Add a new flag 'jtag_poll_en' to hold the temporarily mask
condition and keep 'jtag_poll' for the 'poll' command only.

While there, change the initial assignment of 'jtag_poll' using
the proper boolean value.

Change-Id: I18dcf7c65b07aefadf046caaa2fcd2d74fa6fbae
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7009
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2022-08-15 13:22:06 +00:00
Tim Newsome 81aa5fd6b4 target/riscv: Update debug_defines.h.
This one doesn't have the license in there, which means now it's
acceptable to GPLv2 again.

See https://github.com/riscv/riscv-openocd/pull/711

Change-Id: I8ba27801172ffa955470d2627fa656cad282ee99
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7087
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-15 13:18:16 +00:00
Tomas Vanek 0e1fe03f4b target/arm: do not expose 'arm reg', 'arm mcr/mrc' commands on Cortex-M
Tcl commands 'arm reg', 'arm mcr/mrc' do not work on M-profile based devices.
Isolate them from 'arm core_state' and 'arm disassemble' and do not chain
them from armv7m_command_handlers.

Change-Id: I2c6befdf82575e95cf05ed158ab5e6faa1a182c3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7101
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2022-08-14 14:43:48 +00:00
Tomas Vanek dee7b7d821 target/arm: make 'arm core_state' command compatible with Cortex-M
Tcl command 'arm core_state' was exposed even on Cortex-M devices.
However it returned message "Unsupported Command" without error status
on such device.

Set the only possible arm->core_state ARM_STATE_THUMB in armv7m init.
Block setting core_state to arm on Cortex-M.

Change-Id: I9525553ac8863a6cf77bbacbcd57e354b6cfe1ca
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7100
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2022-08-14 14:43:04 +00:00
Tomas Vanek b6dad912b8 target/cortex_m: prevent segmentation fault in cortex_m_poll()
If a Cortex-M MCU become unresponsive during a debug session and
re-examination fails to find MEM-AP, debug_ap pointer is set to NULL.

Eventual call of cortex_m_poll() dereferences debug_ap.

Check debug_ap validity at the begin of cortex_m_poll().

Change-Id: I9519f48760c91a48a9e5e8c34634d247098cb14a
Fixes: 35a503b08d (arm_adi_v5: add ap refcount and add get/put around ap use)
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7108
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-14 12:11:26 +00:00
Tomas Vanek cae0c8b32b target: move parent target structs just after common_magic
Just a cosmetic refactoring.

Change-Id: I7fbc05324e346fafc98d1b42691d33d3d8fbd04e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7003
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2022-08-14 12:10:14 +00:00
Tomas Vanek ea49b2b2a2 target/aarch64: fix duplicate common magic
AARCH64_COMMON_MAGIC was same as CORTEX_A_COMMON_MAGIC, probably copy pasta.
Define unique AARCH64_COMMON_MAGIC

Change-Id: Ie30e0028453a1fce5624ecad9bf73d5ac3791281
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6997
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-14 12:03:23 +00:00
Tomas Vanek 8f299c6aec target: consolidate existing target/algo common_magic
Unify common_magic type to unsigned int
Move common_magic to be the first member of the struct
Add unsigned specifier to xxx_COMMON_MAGIC #defines

Change-Id: If961d33232698529514ba3720e04418baf6dc6fe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6996
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-14 12:02:38 +00:00
Tomas Vanek 2aaa991a50 target: fix unaligned return of target_get_working_area_avail()
The working area allocation routines use 4 byte word alignment.
In the corner case the size of the working area is not aligned,
target_alloc_working_area() of size = target_get_working_area_avail()
will fail because the size gets aligned up and does not fit to the area
which size is aligned down.

Align down the result of target_get_working_area_avail() to cope with that
corner case.

While on it use fancy ALIGN_... macros instead of bitwise and operator.

Change-Id: Ia2a1e861c401c2c78fe6323379a3776fb4f47b06
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7096
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-08 20:51:52 +00:00
Tomas Vanek b5dd6faf8d target/cortex_a: remove unused CORTEX_A15_COMMON_MAGIC
Change-Id: I7dddc6cb7b0ee8aec7164998f1124b522e899f3d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reported-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7099
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-08-08 19:59:22 +00:00
Evgeniy Naydanov 52177592f9
Fix overflow issue in write_memory_progbuf (#714)
If range's upper bound was equal to 2^64 or the range was wrapping around 0
(which is perfectly legal), writes were not performed due to riscv_addr_t
overflow.
2022-08-01 08:46:36 -07:00
Tomas Vanek 1d8bc131a6 target/riscv: add common magic
Add common_magic member to struct riscv_info.
Introduce is_riscv() helper.

Change-Id: I1af05988ad869342ba5dc6d4d0ba0ec6a8bf7bc7
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6999
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
2022-08-01 08:58:02 +00:00
Tomas Vanek 82e76262a1 target/riscv: use struct riscv_info instead of typedef riscv_info_t
Make the main RISC-V structure more compliant with OpenOCD coding style.
Other typedefs remains as is.

Change-Id: I5657ad28fea8108fd66ab27b2dfe1c868dc5805b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6998
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
2022-08-01 08:57:41 +00:00
Ben Bender 2c6571b9b1 arm_adi_v5: Adding Nuvoton NPCX quirk
We found that the NPCX has an issue with the byte lanes so that non byte
aligned writes aren't working. To overcome this, for byte accesses we
copy the byte to be written to all of the byte lanes.

doc: Document command nu_npcx_quirks

Signed-off-by: benjbender <benjbender@gmail.com>
[Andreas Fritiofson: Squashed commits]
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Change-Id: I9ef63bf692f4e68f57459e1ec33f3abcbf533cd2
Reviewed-on: https://review.openocd.org/c/openocd/+/6630
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-07-30 08:49:47 +00:00
Tim Newsome 793def24c5
Properly set dmcs2.grouptype. (#712)
In #697 this had gotten inverted.

Change-Id: Id86e2cfee0d15c1f05846c1fd5ac83dde26575a2
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-07-25 15:54:49 -07:00
Erhan Kurubas 49cf334e98 target/semihosting: export semihosting_common_handlers[] from header file
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I4add0c1dc7888497ee90fd02754607a16434b66f
Reviewed-on: https://review.openocd.org/c/openocd/+/7075
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-07-23 14:00:26 +00:00
Antonio Borneo 057e566097 openocd: src/target: replace the GPL-2.0-or-later license tag
Replace the FSF boilerplate with the SPDX tag.

The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.

Change-Id: I255ad17235ff1e01bf0aa4deed4d944e1d693ddb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7071
Tested-by: jenkins
2022-07-23 13:58:51 +00:00
Antonio Borneo c3d3487d61 openocd: src: fix incorrect SPDX tags
The SPDX tag is aimed at machine handling and it's thus expected
to be placed in the first line in specific format.

Move the SPDX tag to the first line and fix it where needed.

The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.

Change-Id: Ie9a05f530009d482a4116eebd147fd7e1ee3d41e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7066
Tested-by: jenkins
2022-07-23 13:16:09 +00:00
Antonio Borneo 5635fbc25a openocd: src: replace the incomplete GPL-2.0-or-later license tag
Few files have the FSF boilerplate without the latest statement on
where to get the GPL license.

Manually replace the FSF boilerplate with the SPDX tag.
While there, reorganize the copyright statement.

The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.

Change-Id: I0c908d01c010e24f9c7e94885e7fbed4ecf26a86
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7063
Tested-by: jenkins
2022-07-23 13:15:24 +00:00
Antonio Borneo db0d4dbc3f openocd: src: add GPL license tag on files that miss it
Some file miss completely the license tag.

Add the SPDX tag, using the same GPL-2.0-or-later license of the
OpenOCD project.

The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.

Change-Id: I1fb51e722232d14f050458a820c3041de3dc9138
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7058
Tested-by: jenkins
2022-07-23 13:13:39 +00:00
Antonio Borneo dba88e0238 openocd: src: remove duplicated GPL license tag
SPDX tag is replacing the FSF boilerplate.
For files that have both, remove the FSF boilerplate and keep only
the SPDX tag.

Change-Id: I04c4764d13d4ca92453f30ed16aeae53cd4c3fc8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7057
Tested-by: jenkins
2022-07-23 13:07:57 +00:00
Antonio Borneo 96202cda19 openocd: build: add SPDX tag
Add the SPDX tag to makefiles, configuration scripts and tcl files
present in the folders under src/

Change-Id: I1e4552aafe46ef4893d510da9d732c5f181784a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7051
Tested-by: jenkins
2022-07-23 13:06:38 +00:00
Tim Newsome 969f112321
Update debug_defines.h. (#711)
This one doesn't have the license in there, which means now it's
acceptable to GPLv2 again.

Change-Id: I8ba27801172ffa955470d2627fa656cad282ee99
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-07-18 09:20:22 -07:00
Tim Newsome aaf0620479
Update with latest encoding from riscv-opcodes (#710)
This gets us the new license header, which was requested upstream.

Change-Id: I992b4f3bb230edb9f281e2278dd41c712098ed4c
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-07-08 13:02:13 -07:00
Pavel Kirienko 5e96b012af semihosting: fix return value of SYS_READ and SYS_WRITE
ARM/RISC-V semihosting calls SYS_READ/SYS_WRITE require
inversion of the result value as described in
"Semihosting for AArch32 and AArch64". Prior to
this patch, this was done correctly only if
(semihosting->is_fileio==false).

This patch has been tested with STM32F446.

Change-Id: I1b34c8d8393f7dfa66ee6539904a2eaf8f9154b0
Signed-off-by: Pavel Kirienko <pavel.kirienko@gmail.com>
Fixes: https://sourceforge.net/p/openocd/tickets/232/
Reviewed-on: https://review.openocd.org/c/openocd/+/6803
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-07-02 08:28:30 +00:00
Antonio Borneo b7125c369c target: esp_xtensa_smp: fix clang report
The variable 'smp_break' is only set and used in case of smp.
But clang cannot track if 'target->smp' get modified between the
set and the use of 'smp_break', so it consider possible to use
'smp_break' uninitialized.

Initialize 'smp_break' to silent clang.

Change-Id: Ifa25a84fe9ffa25b8b58d7920ec77994c3b7ebfe
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 77287b8d47 ("target: add Espressif ESP32 basic support")
Reviewed-on: https://review.openocd.org/c/openocd/+/7050
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Tested-by: jenkins
2022-07-02 08:27:31 +00:00
Erhan Kurubas 06c3240155 semihosting: move semihosting_result_t from riscv.h to the semihosting_common.h
These enum values are useful for the arch level semihosting call handlers.
Currently riscv uses them, we also need similar return codes for the xtensa.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I8f63749cc203c59b07862f33edf3c393cd7e33a9
Reviewed-on: https://review.openocd.org/c/openocd/+/7039
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-07-02 08:27:12 +00:00
Antonio Borneo 717b99164a semihosting: remove comparison with NULL
Commit b9526f1401 ("semihosting: permit redirection of
semihosting I/O to TCP") introduces a new comparison with NULL.

Remove it.

Change-Id: Ice4333c50d16f7592f0ff86b1640217fa42e34f6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: b9526f1401 ("semihosting: permit redirection of semihosting I/O to TCP")
Reviewed-on: https://review.openocd.org/c/openocd/+/7031
Tested-by: jenkins
2022-06-24 21:50:41 +00:00
Antonio Borneo e4f5ce5d3e aarch64: fix handling of 'reset halt'
Commit 6c0151623c ("aarch64: add support for "reset halt"")
introduces the register setting to halt at reset vector, but:
- does not consider the case 'srst_pulls_trst' that makes useless
  setting the registers as they will be erased by the pulled trst;
- does not clean sticky errors in case of 'srst_gates_jtag'.

Avoid any register initialization on 'srst_pulls_trst' and move
the cleaning of sticky errors in the common block.

Change-Id: I6f839f06f7b091e234ede31ec18096e51f017bcd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 6c0151623c ("aarch64: add support for "reset halt"")
Reviewed-on: https://review.openocd.org/c/openocd/+/7034
Tested-by: jenkins
Reviewed-by: Christian Hoff <christian.hoff@advantest.com>
2022-06-24 21:49:25 +00:00
Erhan Kurubas 334a187e64 semihosting: add custom user command handler
Custom user syscalls can be handled with target events in the TCL scripts.
This patch gives another opportunity to handle custom syscalls in the c files.
Besides that some utility functions are also exported for the custom handlers.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ice13d527540a0de0b2a8abda912ae3dcff3834b7
Reviewed-on: https://review.openocd.org/c/openocd/+/6889
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-24 21:47:43 +00:00
Erhan Kurubas af9daf4433 esp32s2: convert counted timeout to timeval_ms
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Id685408281478cec0e7e886dbedb3b8972c7b652
Reviewed-on: https://review.openocd.org/c/openocd/+/7020
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Ian Thompson <ianst@cadence.com>
2022-06-24 21:47:07 +00:00
Erhan Kurubas 2053120ba1 target: add Espressif ESP32-S3 basic support
ESP32-S3 is a dual core Xtensa SoC
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I44e17088030c96a9be9809f6579a4f16dbfc5794
Reviewed-on: https://review.openocd.org/c/openocd/+/6990
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-24 21:46:42 +00:00
Erhan Kurubas 77287b8d47 target: add Espressif ESP32 basic support
ESP32 is a dual core Xtensa SoC
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I76fb184aa38ab9f4e30290c038b5ff8850060750
Reviewed-on: https://review.openocd.org/c/openocd/+/6989
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-24 21:46:07 +00:00
Antonio Borneo c28ae626a2 arm_adi_v5: parse ROM tables behind SoC-600 APv1 adapter
Arm "CoreSight System-on-Chip SoC-600" specification describes a
bridge "Access Port v1 adapter" aimed to "connect a legacy Access
Port (AP) ... into an CoreSight Architecture v3 system".

A ROM table can be located in the "legacy" part of the system,
on the legacy AP behind the APv1 adapter.

For the purpose of scanning the ROM tables, consider an ADIv6
SoC-600 APv1 adapter as an ADIv5 AP.

Change-Id: I97d42fb77013c1251fb68d0caa4274086bf38a70
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6827
Tested-by: jenkins
2022-06-24 21:39:39 +00:00
Antonio Borneo 1842cf69a9 adiv6: stay in same AP during dap_lookup_cs_component()
Configuration file can specify, as target's debug AP, an AP that
contains a ROM table that points, in turn, to other APs.
Current code in cortex_a and aarch64 is not able to handle a
return from dap_lookup_cs_component() that points to another AP.

While it could be interesting to specify 'root' as target's debug
AP, drop any found value if it's not in the starting AP.

Change-Id: Id206e4fa7a29e9402c8e2393026817b410bbb8bd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6826
Tested-by: jenkins
2022-06-24 21:39:16 +00:00
Antonio Borneo 9f0ac0e6bb adiv6: add support for ROM tables in AP
ADIv6 adds AP that only contain a ROM table in the AP itself, that
can point to other AP containing either another AP level ROM table
or a MEM-AP to be parsed as usual.

Add support for parsing AP level ROM tables.

Change-Id: Ic25863b16463b8a6adc3b15e26db7fdca858d6df
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6467
Tested-by: jenkins
2022-06-24 21:38:52 +00:00
Antonio Borneo b987a419b4 adiv6: prepare for AP level ROM tables
ADIv6 adds AP that only contain a ROM table in the AP itself, that
can point to other AP containing either another AP level ROM table
or a MEM-AP to be parsed as usual.

To handle recursive AP access, reorganize the code to:
- pass the depth==0 from the command 'dap info';
- print the AP number as first line, adding proper indentation on
  depth>0;
- align the following print with proper indentation.

Change-Id: I5b811810c807fc51b307bd60f67817d9de2aa095
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6466
Tested-by: jenkins
2022-06-24 21:38:30 +00:00
Antonio Borneo 8c1d518232 arm_adi_v5: add option 'root' to 'dap info' command
On ADIv6 the system root ROM table is found by reading the DAP DP
registers BASEPTR0 and BASEPTR1.

Add option 'root' to the commands 'dap info' to let it retrieve
the system root ROM table's AP from DAP DP, then use such AP for
following dump.

Change-Id: I1789457a005faa3870c5d14f763378d2f6a5f095
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6462
Tested-by: jenkins
2022-06-24 21:38:08 +00:00
Antonio Borneo 3f4bc6ce7f adiv6: use struct adiv5_ap->ap_num to contain the AP base address
ADIv5 DAP can only have 256 AP, while ADIv6 can provide till
2**40 (1,099,511,627,776) AP per DAP.

Reuse the field ap_num in struct adiv5_ap, currently used on ADIv5
to hold the ADIv5 AP number (apsel), to contain the ADIv6 AP base
address.

Convert struct adiv5_ap->ap_num to 64 bit and initialize it to
DP_APSEL_INVALID for unused AP.
Restrict dap_find_get_ap() to ADIv5 only. To be enhanced.
On ADIv6, let dap_get_ap() return an already allocated AP, or
allocate and return an unused AP.
Add function is_ap_num_valid() and use it.

Change-Id: Ib2fe8c7ec0d08393cd91c29fdac5d632dfc1e438
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6461
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Tested-by: jenkins
2022-06-24 21:37:44 +00:00
Antonio Borneo 72fb88613f adiv6: add low level swd transport
During enter in SWD read DP_DPIDR without selecting the register
bank through DP_SELECT_DPBANK.
Handle the different format of DP_SELECT register.

Change-Id: Iea1b8eb6ec94177e16a430d5885595a38e833eeb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6697
Tested-by: jenkins
2022-06-24 21:37:21 +00:00
Kevin Burke 62058c0a32 adi_v5_jtag: extend memaccess_tck to every AP access
ADIv5 reports:
	Accessing AP registers or debug resources in connected
	device through an AP can be subjected to other variable
	response delays in the system. A debugger that can adapt
	to these delays and avoid wasting WAIT scans operates more
	efficiently and provides higher maximum data throughput.

The existing code in OpenOCD uses extra tck only for accessing
resources through an AP.

Extend the use of extra tck also for accessing an AP register.

Split from change https://review.openocd.org/6077/

Change-Id: I2082362e098d09f4ba0668e01f5196afc965c8f3
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6460
Tested-by: jenkins
2022-06-24 21:37:00 +00:00
Kevin Burke 8f8fb0fa79 adiv6: add low level jtag transport
swd and dap-direct are not implemented yet

Split from change https://review.openocd.org/6077/

Change-Id: I6d73d8adf6a6090001c5d4771325fb1d63c45e3c
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6459
Tested-by: jenkins
2022-06-24 21:35:46 +00:00
Antonio Borneo edb575800a adi_v5_jtag: clear sticky overrun error
By accessing invalid AP in JTAG mode, it's possible to trigger the
error:
	JTAG-DP STICKY ERROR
After that the sticky error is never cleared and the whole DAP
gets not anymore accessible.

Clean-up the sticky error once detected.

Change-Id: I8b07263b30f9e46645f0c29084b8f1626e241f45
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6430
Tested-by: jenkins
2022-06-24 21:35:27 +00:00
Kevin Burke 513aba1930 adiv6: read ROM Table address size
Required for parsing ADIv6 ROM tables.

Split from change https://review.openocd.org/6077/

Change-Id: I849543b7b4a4455b10bd9fc7da38a37849d71700
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6458
Tested-by: jenkins
2022-06-24 21:35:08 +00:00
Kevin Burke a6e4aabc66 adiv6: re-organize mem_ap registers definition
ADIv5 MEM-AP registers are a subset of ADIv6 MEM-AP registers and
are located at different offset.

To prepare for introducing ADIv6, add 'struct adiv5_dap *' as
argument to ADIv5 registers macro.
Check the ADI version and use the proper address.
Both adapter drivers rshim and stlink are ADIv5 only, so let them
use the ADIv5 macros only.

Split from change https://review.openocd.org/6077/

Change-Id: Ib861ddcdab74637b2082cc9f2612dea0007d77b1
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6457
Tested-by: jenkins
2022-06-24 21:34:51 +00:00
Kevin Burke 1fe82f9f1d adiv6: add dap flags -adiv5 and -adiv6
Add flags to 'dap create' command and set the field adi_version
in struct adiv5_dap.

Actually only ADIv5 is functional. Other patches are needed to get
ADIv6 working.

Split from change https://review.openocd.org/6077/

Change-Id: I63d3902f99a7f139c15ee4e07c19eae9ed4534b9
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6456
Tested-by: jenkins
2022-06-24 21:34:30 +00:00
Antonio Borneo 35a503b08d arm_adi_v5: add ap refcount and add get/put around ap use
While an ADIv5 DAP can only have 256 AP, ADIv6 can provide till
2**40 (1,099,511,627,776) AP per DAP.
The actual trivial code implementation for ADIv5 (that uses an
array of 256 ap in the struct adiv5_dap) cannot be extended as-is
to handle ADIv6.

The simple array of 256 AP can be reused as a dynamic storage for
ADIv6 ap:
- the ADIv5 AP number is replaced by the ADIv6 base address;
- the index of the array (equal to ADIv5 AP number) has no link to
  any ADIv6 property;
- the ADIv6 base_address has to be searched in the array of AP.

The 256 elements in the AP array should be enough for any device
available today. In future it can be easily increased, if needed.

To efficiently use the 256 elements in the AP array, the code
should associate one element of the array to an ADIv6 AP (through
the AP base address), then cancel the association when the AP is
not anymore needed. This is important to avoid saturating the AP
array while exploring the device through 'dap apreg' commands.

Add a reference counter in the struct adiv5_ap to track how many
times the struct has been associated with the same base address.
Introduce the function dap_get_ap() to associate and return the
struct, and dap_put_ap() to release the struct. For the moment the
code covers ADIv5 only, so the association is through the index.
Use the two functions above and dap_find_get_ap() throughout the
code.
Check the return value of dap_get_ap(). It is always not NULL in
the current ADIv5-only implementation, but can be NULL for ADIv6
when there are no more available AP in the array.
Instrument dap_queue_ap_read() and dap_queue_ap_write() to log an
error message if the AP has reference counter zero, meaning that
the AP has not been 'get' yet. This helps identifying AP used
without get/put, e.g. code missed by this patch, or merged later.
Instrument dap_cleanup_all() to log an error message if an AP has
reference counter not zero at openocd exit, meaning that the AP
has not been 'put' yet.

Change-Id: I98316eb42b9f3d9c9bbbb6c73b1091b53f629092
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6455
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Tested-by: jenkins
2022-06-24 21:33:23 +00:00
Jan Matyas 6d359afde4
Fix: Prevent segfault in riscv_invalidate_register_cache for non-examined targets. (#692)
The segfault could be triggered if:

- At least one target failed to get examined (therefore does not have the
  register cache set up yet),

- and "reset" TCL command was issued, which internally tries to
  invalidate the register cache.

Minor cleanup: "registers_initialized" member removed from riscv_info_t
because it is not used anywhere.

Change-Id: I6288c0d4343ef6a330fb2a6b49d388e7eafa32a2
Signed-off-by: Jan Matyas <matyas@codasip.com>
2022-06-16 09:58:45 -07:00
Tim Newsome d85a4e8098
Remove unused code. (#707)
Change-Id: I3961a62c0c51200ff3241265d9ea3e69492bdc4e
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-06-15 10:22:19 -07:00
Erhan Kurubas 480d4e1772 semihosting: fix accessing memory outside the bounds of the fn array
There is an accsess to wrong index, when arm semihosting_basedir
command not used or basedir set to empty string.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I3afa049d74b30496f5c03ba4ef67431784f81bdc
Fixes: ce5027ab01 ("semihosting: add semihosting_basedir command")
Reviewed-on: https://review.openocd.org/c/openocd/+/7005
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-10 21:56:47 +00:00
Antonio Borneo 7cc79a8d62 arm_adi_v5: check for calloc() return value
In function adiv5_jim_configure() check that calloc() returns a
valid allocated memory pointer.

Change-Id: I97287e168834693900341add9d9eb9a5f38c55b4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7014
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-06-10 21:54:55 +00:00
Antonio Borneo 95135b39cc arm_adi_v5: fix scan-build warning [3/3]
While scan-build complains that dap_p or ap_num_p could be NULL,
the current code never passes NULL pointers.
Add an assert() to silent scan-build and prevent any further use
of the function with incorrect parameters.

Change-Id: I656810dddcea61e85d85b13efb114f7607ef837c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7012
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-06-10 21:54:29 +00:00
Antonio Borneo aee7c70a1a arm_adi_v5: fix scan-build warning [2/3]
Commit d01b3d69ec ("arm_adi_v5: separate ROM table parsing from
command output [3/3]") introduces a new scan-build warning because
removing one return in case of error causes using uninitialized
values.

Add back the return on error.

Change-Id: I10ddc548b756d34aaccc0511f091b4caa5ec271a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: d01b3d69ec ("arm_adi_v5: separate ROM table parsing from command output [3/3]")
Reviewed-on: https://review.openocd.org/c/openocd/+/7011
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-06-10 21:54:17 +00:00
Antonio Borneo 63e22d5fb9 arm_adi_v5: fix scan-build warning [1/3]
Commit 21f7885d1c ("arm_adi_v5: separate ROM table parsing from
command output [1/3]") introduces a new scan-build warning because
continues the execution even when dap_get_debugbase() returns
error. The value of 'apid' can be uninitialized:

	5th function call argument is an uninitialized value

Check the return value and quit on error.
While there, remove the useless initialization of 'dbgbase' that
was apparently required for the same problem.

Change-Id: Iade26a152925ee0f1bf114ed829b94f7ed5b254f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 21f7885d1c ("arm_adi_v5: separate ROM table parsing from command output [1/3]")
Reviewed-on: https://review.openocd.org/c/openocd/+/7010
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-06-10 21:54:01 +00:00
Tomas Vanek 7e9e5dca07 target/riscv: drop unused variable registers_initialized
Change-Id: If7bfe38ac273ce9e54003e003807e128cced1568
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6995
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-04 08:20:09 +00:00
Erhan Kurubas 78c87f5e81 target: add Espressif ESP32-S2 basic support
ESP32-S2 is a single core Xtensa chip.
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I2fb32978e801af5aa21616c581691406ad7cd6bb
Reviewed-on: https://review.openocd.org/c/openocd/+/6940
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2022-06-04 08:18:44 +00:00
Tarek BOCHKATI b470b664ca cortex_a: get rid of not needed log messages
when using semi-hosting with cortex_a this LOG_INFO pollutes openocd
console, so just reduce the log level of this message.

Change-Id: I91aa70492f4e361b25a0e5517d0cf73f2f8ed599
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://gerrit.st.com/c/stm32ide/official/openocd/+/248225
Tested-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6993
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-03 23:46:21 +00:00
Tomas Vanek cc8b491856 flash/nor/core, target: don't ask for working mem if no target algo
The command 'flash erase_check' showed the message
'Running slow fallback erase check - add working memory'
even in the case the target didn't implement blank_check_memory.

Change return code of target_blank_check_memory() in this case
and sense it in default_flash_blank_check() and show a message
without a request for working memory.

Change-Id: I7cf9bf77742964b4f377c9ce48ca689e57d0882f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6765
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
2022-05-29 15:47:21 +00:00
Tim Newsome bce93f6d51 Give each SMP group a unique number.
This helps e.g. if there are 8 cores, and cores 0--3 are in one SMP
group while 4--7 are in another group. (And there are 2 gdb instances
connected, one debugging the first group, and one the second.)

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I7b6c9382eadf964529105eaf0411a42d48768668
Reviewed-on: https://review.openocd.org/c/openocd/+/6979
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-05-27 22:52:35 +00:00
Tim Newsome 5c34da1415
Use new debug_defines.h (#703)
* Update debug_defines from the spec.

Now it includes constants for field values, so use them instead of
duplicating that here.

Change-Id: I2fca6e89f25123c39d4bf483b8244e47aefb0f88

* Remove unused #defines

Change-Id: Id20351851c9ed2c3aa82ccf8c04b604bef11692a

* Use debug spec constants in a few more places

Change-Id: Ic4578729c89e3c6a26a72772e1635c5345bd6a52
Signed-off-by: Tim Newsome <tim@sifive.com>

* Use macros for trigger action types.

Which were added with the very latest debug_defines.h.

Change-Id: I47f73e11d2ec529c720f2e1df05f7b0d3026e43a
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-05-25 10:08:43 -07:00
Erhan Kurubas ce5027ab01 semihosting: add semihosting_basedir command
This command allows users to set base working directory for the
semihosting I/O operations.Default is the current OpenOCD directory.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I80c5979e4c96d66cccdd12cc6fcd5f353e5c6b4d
Reviewed-on: https://review.openocd.org/c/openocd/+/6888
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-05-21 09:01:56 +00:00
Tomas Vanek 0f11f951e7 target: fix clang static analyzer warning
Removes Warning:	line 6482, column 12
1st function call argument is an uninitialized value

Use target ptr directly as checked in previous lines instead of
dereferencing head->target

Change-Id: I6804b776fd493af71f3098d702f9cdc7acb50151
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6970
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-05-21 09:00:05 +00:00
Tim Newsome 0fada02494
Correctly set target->smp. (#701)
This was broken by #684. Thanks to Jan for noticing.

Change-Id: I6ce115a6a333b93d7edb3ee44daae3f618d092e6
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-05-18 09:40:22 -07:00
Tomas Vanek 7d2ea186cf target/riscv: fix 'reset run' after 'reset halt'
'reset halt' does not clear DM_DMCONTROL_HALTREQ at deassert_reset().
If hw reset line is configured e.g. 'reset_config srst_only'
the folowing 'reset run' halts:

 > gd32v.cpu curstate
 running

 > reset halt
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 halted

 > reset
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 halted <<<<---- wrong!!!

 > reset
 JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
 > gd32v.cpu curstate
 running

Clear DM_DMCONTROL_HALTREQ when acking reset.

Change-Id: Iae0454b425e81e64774b9785bb5ba1d4564d940b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6961
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
2022-05-18 09:03:41 +00:00
Tim Newsome 6047fedc63
Change set_haltgroup() to more general set_group() (#697)
* Change set_haltgroup() to more general set_group()

Change-Id: Ib91a252ac63604e54b756f70c549ccd47241fd10
Signed-off-by: Tim Newsome <tim@sifive.com>

* Properly use enum.

Change-Id: I0edef6053fac388db38a22fe7557623fa93ec705
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>

* Style changes suggested in review.

Change-Id: I29e83d3dbef09cb971ec0355aff733191a6e4679
Signed-off-by: Tim Newsome <tim@sifive.com>

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-05-16 10:17:04 -07:00
wzgpeter a408bdc8db
fix: semihosting_fileio display the unsupported info (#699)
the abnormal info display below:
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0
semihosting: unsupported call 0

the PC did not plus 4 before resume, which cause this
abnormal info popup.

Change-Id: I15c1e7426f1925e78f607c566976f9352216506f
Signed-off-by: Wu Zhigang <zhigang.wu@starfivetech.com>

Co-authored-by: Wu Zhigang <zhigang.wu@starfivetech.com>
2022-05-16 09:57:22 -07:00
Antonio Borneo 99293ebd15 aarch64: don't wait for smp targets halted in deassert reset
The function target_type::deassert_reset() is called for every
target after reset is deasserted. If the target fails to get
halted, we log a warning and issue a halt request for the target
itself.

Current code calls the generic target_halt() that:
- extends the halt to all the targets in the SMP node;
- waits for targets to halt.
This breaks the logic of running target_type::deassert_reset()
per target. Plus, waiting for targets to halt delays the call of
target_type::deassert_reset() for the next targets.

Replace the call to target_halt() with the aarch64 specific
function to halt the single target. Pass the parameter HALT_LAZY
to prevent the wait for target halted.
Similar solution is already implemented for cortex_a.

Change-Id: I446dc03cb91524c6d388db485bc2388177af77b6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6947
Tested-by: jenkins
2022-05-14 08:57:36 +00:00
Antonio Borneo a47d1f1b79 arm_adi_v5: add support for 64bit Class 0x9 ROM tables
Arm documentation does not explicitly report the order of the two
32bit words that compose the 64bit value. But both ADIv5 and ADIv6
specify that only little-endian is supported (ADIv5.2 obsoletes
the big-endian support). This change reads the 64bit value in
little-endian.

Detect the 64bit content and use it.

Change-Id: I723ec099c7e8c70c1f9a568e32ea867fcbf1f1db
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6465
Tested-by: jenkins
2022-05-14 08:56:37 +00:00
Antonio Borneo d74f11dcd4 arm_adi_v5: replace dap_lookup_cs_component()
With the generic function for ROM table walk-through, reimplement
dap_lookup_cs_component().

Catch the code CORESIGHT_COMPONENT_FOUND and halt the search.
While there, drop two macros in arm_coresight.h, now unused.

Change-Id: I589ef7ae8a651d0c422ce7d0b4ed913713a8217e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6824
Tested-by: jenkins
2022-05-14 08:55:52 +00:00
Antonio Borneo 613f1c6abb arm_adi_v5: let dap_lookup_cs_component() to get AP dbgbase
Simplify the code in cortex_a and aarch64 by moving the call to
dap_get_debugbase() inside dap_lookup_cs_component().

This has the further effects:
- dap_get_debugbase() is not referenced outside arm_adi_v5.c and
  becomes static;
- dap_lookup_cs_component() looses one parameter;
- the coreid parameter 'idx' is passed as value;
- the caller in aarch64 don't have and don't print the irrelevant
  value of AP register APID;
- fixes the debug message in the caller in aarch64 to print the
  coreid value instead of always zero.

Change-Id: Ic7f0f643fdf067c059c8f2455a02ff18a3fed054
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6823
Tested-by: jenkins
2022-05-14 08:55:33 +00:00
Antonio Borneo 7351330a0f arm_adi_v5: abstract actions during ROM table parsing
Now all the actions (build command output) of command "dap info"
are decoupled from the ROM walk-through.
Pass the actions as a generic parameter to ROM walk-through code.
Put as private data every information that is only required by the
actions and not by the ROM walk-through.

Change-Id: I3b6ad112ea21296458c94aebbf91bf65bf6657a7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6822
Tested-by: jenkins
2022-05-14 08:54:53 +00:00
Antonio Borneo d01b3d69ec arm_adi_v5: separate ROM table parsing from command output [3/3]
This change only targets the output of rtp_rom_loop().

Change-Id: If9ac013798923428c3b897a969887e98b6935a2b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6821
Tested-by: jenkins
2022-05-14 08:54:36 +00:00
Antonio Borneo c83b94b2c8 arm_adi_v5: separate ROM table parsing from command output [2/3]
This change only targets the output of rtp_cs_component().
To easily propagate the coordinates of the CoreSight component,
add them in the struct that holds the register values.
While there, define a macro for the max depth of ROM tables.

Change-Id: I75e5ef4f9419da3192123aebcd61471c2af9374f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6820
Tested-by: jenkins
2022-05-14 08:54:25 +00:00
Antonio Borneo 21f7885d1c arm_adi_v5: separate ROM table parsing from command output [1/3]
In OpenOCD arm_adi_v5 we have already two implementations of code
for parsing the ADIv5 ROM table:
- in the commands "dap info" and "$dap_name info";
- in the function dap_lookup_cs_component().
Adding support for ADIv6 requires extending both implementations.

Moreover, current code does not handle few aspects of the ROM
parsing, e.g. the "Power Domain IDs".
To add such extensions both implementations should be touched.

I plan to add a command to parses (again) the ROM table and dump a
simple prototype of a configuration script for the target, useful
while analysing a new target.

Keeping aligned all these implementation would be too complex.

With focus to "dap info" command, decouple the part of code to
walk-through the ROM table from the code that creates the command
output.
The idea is to keep a single implementation for the walk-through
code, while parametrizing the output code to handle the generation
of a configuration script or the result of the function
dap_lookup_cs_component().

This change only targets the output of MEM-AP header
Further changes will target other parts of the code.

While there, add a message if MEM-AP is not accessible.

Change-Id: I112f637edfdb8688afb4e631297f6536da9604f1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6819
Tested-by: jenkins
2022-05-14 08:54:02 +00:00
Antonio Borneo a73adb5241 arm_adi_v5: handle faulting entry in ROM table
ARM IHI0031F "Arm Debug Interface Architecture Specification"
chapter C2.6.1 "BASE, Debug Base Address register" reports:
	A debugger must handle the following situations as
	non-fatal errors:
	- ...
	- An entry in the ROM Table points to a faulting location.
	- ...
	Typically, a debugger issues a warning if it encounters
	one of these situations. However, Arm recommends that it
	continues operating. An example of an implementation that
	might cause errors of this type is a system with static
	base address or ROM Table entries that enable entire
	subsystems to be disabled, for example by a tie-off input,
	packaging choice, fuse, or similar.

Don't halt ROM table parsing if one entry causes an error; log the
error condition and continue to next entry.
Not sure if we have to send an ABORT before continuing.

Change-Id: I94fdb5b175bfb07dde378149421582b7e7cd5b09
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6818
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2022-05-14 08:53:35 +00:00
Antonio Borneo d4335071b8 arm_adi_v5: report sysmem on class 0x9 ROM tables
As Class 0x1 ROM table, also Class 0x9 ROM tables encodes a flag
for system memory access.

Detect the flag in rtp_cs_component() and dump the same message
for both type of ROM tables.
Extend rtp_read_cs_regs() to read ARM_CS_C9_DEVID.

Change-Id: Ic85d1ea068ed706ceedfd65076ff4c96d04e9792
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6817
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2022-05-14 08:52:30 +00:00
Antonio Borneo 209cb38aa1 arm_adi_v5: split ROM table loop from generic coresight
During ROM table parsing, each ROM table entry points to a
CoreSight component that can, in turn, be another ROM table.

Split the specific code for ROM table handling from the generic
CoreSight code.
Log an error if a ROM table entry cannot be read.

Change-Id: I5ad106a99b9c21ddb48b5b162ae87101e4f49878
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6816
Tested-by: jenkins
2022-05-14 08:51:07 +00:00
Antonio Borneo c3f6e21d5c arm_adi_v5: rework dap_read_part_id()
Rework dap_read_part_id() while preparing for reorganizing the
'ROM Table Parsing' (RTP):
- rename it with 'rtp' prefix;
- extends it to read other CoreSight registers, thus improving the
  overall speed by queuing more reads;
- reduce the list of arguments by using a struct;
- reorder the reads by increasing offset, potentially gaining
  speed using MEM_AP_REG_BDx and/or auto-increment;
- log a debug message in case of read error.

Change-Id: I6544ac7740b808a6c0fbacf97ac00b97f5bd3832
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6815
Tested-by: jenkins
2022-05-14 08:50:41 +00:00
Florian Fainelli 1fd2a6c7f5 arm_adi_v5: add support for display Class 0x9 ROM tables
ADI v5.1 and v6.0 permit the definition of CoreSight components (class 9
ROM entries).

dap_rom_display() is refactored a bit such that we always end up with
attempting to parse the ROM contents using the appropriate upper limit
for class 1 and 9 ROM types.

Change-Id: I4ba497b3807f1f11f06186eb6e61959ea3540c59
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6359
Tested-by: jenkins
2022-05-14 08:48:10 +00:00
Antonio Borneo fed329feec arm_adi_v5: describe Class 0x9 Device Architecture register
Use the list of values from ARM IHI0029E to decode and print the
Device Architecture register.
Add attribute 'unused' to the function, not used yet.

Change-Id: I7b1dd204bd1db671578c588372b667e23611876c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6463
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2022-05-14 08:43:51 +00:00
Antonio Borneo a785ca315b adi_v5_jtag: reduce verbosity on persistent WAIT
In case of AP not responding, e.g. not clocked, the first WAIT
reply is logged as:
	DAP transaction stalled (WAIT) - slowing down
then OpenOCD retries the transaction few times, until it timeouts.
At each retry it prints the message:
	DAP transaction stalled during replay (WAIT) - resending
Depending on JTAG speed and transport latency, the amount of log
messages can be quite annoying and not relevant.
The last printed line is at timeout:
	Timeout during WAIT recovery

Reduce the verbosity.

Change-Id: I5a7a337527c98b2450de59066b13713511c2894f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6814
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2022-05-14 08:43:30 +00:00
Antonio Borneo d796f5929c arm_coresight: define ARM_CS_CIDR_CLASS()
Right now it has a single use but it will soon be used more.

Change-Id: I9a819c65df467fc859e4b5251035a17ed33daa35
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6813
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2022-05-14 08:42:29 +00:00
Tomas Vanek 4c1919c566 target: document possibly unreachable target in deinit_target()
Change-Id: I95ff3d200bb2c8f5bc43a34c92726d9c47f8c172
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6953
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-05-07 11:04:45 +00:00
Antonio Borneo 7819834ace target: fix build with jimtcl 0.79
In jimtcl 0.80 the prototype of Jim_DictPairs() has changed.
The only code in OpenOCD that uses Jim_DictPairs() has been merged
recently and it only uses the current jimtcl syntax.

To allow compiling OpenOCD master branch with older versions of
jimtcl, detect the version of jimtcl and use the appropriate
syntax.

Change-Id: I6fc78303b6a4db064a97f326c46119f4568e88f3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: dullfire@yahoo.com
Reviewed-on: https://review.openocd.org/c/openocd/+/6948
Tested-by: jenkins
2022-05-07 11:04:18 +00:00
Antonio Borneo b4f8d99c8d smp: deprecate legacy SMP core switching support
The deprecation was already in the documentation since v0.11.0
through commit 85ba2dc4c6 ("rtos/hwthread: add hardware-thread
pseudo rtos") but OpenOCD was not informing the user printing a
runtime message.

Remove the deprecated method from the documentation and print a
deprecated message at runtime.
There is no reliable way to print the same message in GDB console,
so we have to rely on user noticing it in the OpenOCD log.
Target is to remove the functionality after v0.12.0.

Change-Id: Idd2d9e3b6eccc92dcf0432c3c7de2f8a0fcabe9f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6862
Tested-by: jenkins
2022-05-07 11:00:00 +00:00
Tim Newsome 9460f43dc3 Merge branch 'master' into from_upstream
Conflicts:
	tcl/target/gd32vf103.cfg

I kept our version, except I changed the flash device as happened in
mainline. Once this file settles down in mainline, we can copy it
wholesale into this fork.

Change-Id: I4c5b21fec0734b5e08eba392883e006a46386b1c
2022-05-03 13:41:55 -07:00
Tim Newsome b6dddfacc0
Merge pull request #694 from riscv/trigger_hit
Look at trigger hit bits to see which trigger was hit.
2022-05-02 09:40:07 -07:00
fatalc 12d1ad0c75 target/disassembler: update capstone include path to <capstone.h>
on macos (homebrew base) `pkg-config --cflags capstone` output with
`-I/opt/homebrew/Cellar/capstone/4.0.2/include/capstone`
gcc not find headers on parent "include" path,
causes build error `fatal error: 'capstone/capstone.h' file not found`
it's ok to change to <capstone.h> for all platforms.

Signed-off-by: fatalc <cnfatal@gmail.com>
Change-Id: Ia2e2058024d4fc1a57a8b4ea847c664d74f67efb
Reviewed-on: https://review.openocd.org/c/openocd/+/6946
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-04-30 17:53:30 +00:00
Marc Schink 8789513fa9 target/arm_cti: Fix error handling in 'cti create'
Handle JIM_CONTINUE return value of adiv5_jim_mem_ap_spot_configure(),
otherwise OpenOCD silently quits when an unknown option is provided.

Change-Id: I9b1351c0911e74999d8dd1260ede9760088510d7
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6944
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-04-30 17:52:40 +00:00
Tim Newsome 1979ad5594 If we know which trigger hit, don't disassemble.
Change-Id: I1d7b6ffa91b0557e2e74e544e4b35033ed3e3553
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-04-30 09:59:46 -07:00
Tim Newsome 73199226df Report some triggers as hardware breakpoints.
Instead of reporting them all as watchpoints.

Change-Id: If43d282a168f64f8fed6f659bcebbe2ef72f23e9
2022-04-27 13:01:14 -07:00
Tim Newsome d67a5bf064 During polling, check which trigger has `hit` set.
Change-Id: If226810ed930e5d7a2bab277a9f5b0f3ded86ffa
2022-04-27 13:00:47 -07:00
Tim Newsome 68e41dc1c8 Remove empty line.
Change-Id: Id00bfd73363e60e109b339e86d620c1ed7d5198a
2022-04-27 12:59:43 -07:00
Tim Newsome edcfcab890 Add trigger_hit field to riscv_info
Change-Id: If4e1b5c37da4ab9301d91f41ba4789662b677a29
2022-04-27 12:58:57 -07:00
Tim Newsome a6f3212684 Create riscv_hit_trigger_hit_bit() function.
This goes through the triggers OpenOCD set to find out if one of them
has the hit bit set.

Change-Id: I5b9f1c19273c7d40392a0cc278277ca6c94d2eae
2022-04-27 12:58:09 -07:00
Tim Newsome dc320d26f0 Small code cleanup.
Change-Id: I563b7c62494987287b13d9ed52a923e6f49a64be
2022-04-27 12:46:09 -07:00
Tim Newsome e8b05455e2 Make watchpoint.unique_id a uint32_t
Now it matches breakpoint.unique_id.

Change-Id: I06f24b2cede2ee56bdeac8666b5235f923b18659
2022-04-27 12:41:13 -07:00
Tim Newsome bd266161ca Fix typo in comment.
Change-Id: If847aaedc704857f30220da8d6af703f1b57ad1d
2022-04-27 10:48:10 -07:00
Jan Matyas a213397323 target/image: fix - p_flags field in ELF64 segment headers is 64 bits wide
Fixed the reading of p_flags in ELF64 segment headers - that field
is 64 bits wide.

Change-Id: I053ca57d36efb54b7c638484acd6c7a2fbcbd05a
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6927
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-04-23 09:26:15 +00:00
Dolu1990 9d737af351
riscv: Add a option to specify the JTAG TAP tunnel IR (#690)
* riscv: Add a option to specify the JTAG TAP IR used to access the bscan tunnel.

Change-Id: Ice8798823313e2177e75473e62b06e7da74bbba2
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>

* risc-v: Add litex doc about the set_bscan_tunnel_ir command

Change-Id: I1237213f32886d20fc7d60d5ca1e2124953eaeda
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>

* risc-v: remove tunnel ir length assert when ir is set by the user

Change-Id: I2b33fc6205f37461ff1bd15601b460a2467ea32b
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>

* Open riscv: Add a option to specify the JTAG TAP tunnel IR

Typo

Co-authored-by: Tim Newsome <tim@sifive.com>

* riscv: Add a option to specify the JTAG TAP tunnel IR

typo

Co-authored-by: Tim Newsome <tim@sifive.com>

Co-authored-by: Tim Newsome <tim@sifive.com>
2022-04-20 10:16:47 -07:00
Tim Newsome b7fdcd5e85 Fix build.
Change-Id: Ied627f264a46e64f82a81b54e70daac2ebc0b708
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-04-11 11:21:30 -07:00
Tim Newsome 00d7c7994a Merge branch 'master' into from_upstream
Conflicts:
	src/server/server.c
	src/target/breakpoints.c
	src/target/semihosting_common.c
	src/target/target.c

Change-Id: I48bd3608c688c69d8aac0667fc46e2de5466a9f1
2022-04-11 11:13:20 -07:00
Dolu1990 78b56e25c2
riscv: Increase batch allocation size to improve transfer speed. (#689)
Change-Id: I4cd1479f4d2f7b63cd594f5cef9d6b3d877d9015
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
2022-04-11 07:58:35 -07:00
Antonio Borneo 3fa695be24 openocd: include config.h in every file .c
Including config.h as first is required for every C file.
Add it to the C files that still miss it.

Change-Id: I1a210e7d3a854958a85a290b086ad8a9f5176425
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6856
Tested-by: jenkins
2022-03-26 13:32:57 +00:00
Antonio Borneo 00d4699d0b arm_tpiu_swo: fix autodetection of SWO pin frequency
While the documentation reports that SWO pin frequency can be
omitted to let the adapter autodetect the value, the code wrongly
drops an error when pin frequency is not specified.

Don't require the pin frequency to be set at "enable", but verify
that the adapter has properly changes it to a valid value.

Change-Id: I3dfbe3256e8887ef4f03512769b06381cdc9db0d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Karl Palsson <karlp@tweak.net.au>
Fixes: 184724d14e ("arm_tpiu_swo: add support for independent TPIU and SWO")
Reviewed-on: https://review.openocd.org/c/openocd/+/6310
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
2022-03-26 13:23:40 +00:00
Antonio Borneo 2cafa8be73 semihosting: fix mode flags for local host open()
Commit dbbac5f11d ("semihosting: use open mode flags from GDB,
not from sys/stat.h") fixes the conversion of the mode flags from
ARM semihosting encoding for SEMIHOSTING_SYS_OPEN to GDB mapping
for open().
Doing this, it breaks the conversion to local host's OS mapping
for open().

Split the conversion array to one for GDB and one for local host.
The local host conversion array is taken directly from the old
code.

Change-Id: I385321ddd32c3ac5cf6da3f1ce9eff76b05dd527
Fixes: dbbac5f11d ("semihosting: use open mode flags from GDB, not from sys/stat.h")
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6870
Tested-by: jenkins
2022-03-26 13:21:19 +00:00
Jan Matyas 0a70e59cb8
Fix: Set proper debug_reason in deassert_reset() (#687)
* Fix checkpatch workflow: ignore changes in .github/

Ignore changes in .github/ directory when running checkpatch.

Checkpatch emits false alarms on substrings "CC:" found in *.yml
workflow files, apparently thinking it is a "Cc:" signature in
commit message.

Change-Id: Id977d5a8838797e4676758066af4825651c41a87

* Fix: Set proper debug_reason in deassert_reset()

The issue was visible for example when user's .cfg file ended
with "reset halt" command:

In such case, the hart would remain halted but the debug_reason would not be
updated and may retain an incorrect value, e.g. DBG_REASON_NOTHALTED.
In such cases, gdb_last_signal() would provide an incorrect reply to GDB.

Change-Id: Ie6f050295fb5cbe9db38b189c4bc385662acf5b4
Signed-off-by: Jan Matyas <matyas@codasip.com>

* Fix checkpatch workflow: add 'apt-get update'

Change-Id: Ic5843ec86d16a187d01970a3253caade3d13b7ab
Signed-off-by: Jan Matyas <matyas@codasip.com>
2022-03-23 09:47:57 -07:00
Antonio Borneo 92c4e634d7 breakpoints: fix build on -fno-inline
Some configuration of GCC could default to -fno-inline, causing
the build to fail after commit fb43f1ff4e ("target: Rework 'set'
variable of break-/watchpoints").

Switch the new inline functions to 'static inline', as it's widely
used in the rest of the code.

Change-Id: I8bf31045a137bd34ed825f4b2a9338eb3c70046d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: fb43f1ff4e ("target: Rework 'set' variable of break-/watchpoints")
Reviewed-on: https://review.openocd.org/c/openocd/+/6881
Tested-by: jenkins
2022-03-19 11:35:32 +00:00
Marc Schink fb43f1ff4e target: Rework 'set' variable of break-/watchpoints
The 'set' variable name suggests a boolean data type which determines
whether a breakpoint (or watchpoint) is active. However, it is also
used to store the number of the breakpoint.

This encoding leads to inconsistent value assignments: boolean and
integer values are mixed. Also, associated hardware comparator
numbers, which are usually numbered from 0, cannot be used directly.
An additional offset is required to store the comparator numbers.

In order to make the code more readable and the value assignment more
consistent, change the variable name to 'is_set', its data type to 'bool'
and introduce a dedicated variable for the break-/watchpoint
number.

In order to make the review easier, the data types of various related
variables (e.g. number of breakpoints) are not changed.

While at it, fix a few coding style issues.

Change-Id: I2193f5639247cce6b80580d4c1c6afee916aeb82
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6319
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-19 09:14:39 +00:00
Tarek BOCHKATI b9526f1401 semihosting: permit redirection of semihosting I/O to TCP
This command permits the usage of a TCP port to perform debug and stdio
operations:
 - debug : READC, WRITEC and WRITE0
 - stdio : READ, WRITE

This will permit the separation of semihosting message from OpenOCD log,
and separate semihosting messages per core.

syntax: arm semihosting_redirect (disable | tcp <port> [debug|stdio|all])

this allows to select which operations to be performed via TCP (debug,
stdio or all (default)).

Note: for stdio operations, only I/O from/to ':tt' file descriptors are
redirected.

tested using netcat on ubuntu

Change-Id: I37053463667ba109d52429d4f98bc98d0ede298d
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5562
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-19 09:11:05 +00:00
Antonio Borneo 99c77806fe server: change prototype of add_service()
To easily add new methods to a service, pass all the methods
through a struct.
While there, drop the typedef for the methods and add currently
unused new methods to support keep-alive and connections during
keep-alive.

No change in functionality.

Change-Id: I2b5e7140db95021f6e7201e9d631ee340c60b453
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6838
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2022-03-19 09:05:27 +00:00
Marc Schink e370e06b72 target: Deprecate 'array2mem' and 'mem2array''
Replace 'mem2array' and 'array2mem' with a Tcl wrapper that
internally uses 'read_memory' and 'write_memory'.

The target-specific 'mem2array' and 'array2mem' functions
remain for now.

Change-Id: If24c22a76ac72d4c26916a95f7f17902b41b6d9e
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6308
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12 09:48:00 +00:00
Marc Schink 38183dc856 target/tcl: Add 'read_memory' and 'write_memory'
These functions are meant as replacement for 'mem2array' and
'array2mem'.

The main benefits of these new functions are:

 * They do not use Tcl arrays but lists which makes it easier
   to parse (generate) the data. See the Python Tcl RPC code
   in contrib as a negative example.

 * They do not operate on Tcl variables but instead return (accept)
   the Tcl list directly. This makes the C and Tcl code base
   smaller and cleaner.

 * The code is slightly more performant when reading / writing
   large amount of data. Tested with a simple Python Tcl RPC
   benchmark.

Change-Id: Ibd6ece3360c0d002abaadc37f078b10a8bb606f8
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6307
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12 09:47:42 +00:00
Tarek BOCHKATI 4906176c77 cortex_m: use LOG_TARGET_XXX
Change-Id: I8be0f67442644031e6e8df3090d81af195caf82b
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6672
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12 09:33:35 +00:00
Marc Schink 2586fec922 target/arm_tpiu: Fix usage of 'tpiu create'
Change-Id: I1ffad65a9e6d76f4d7fbbe249d8af3beb7e7692b
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6860
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-05 13:24:18 +00:00
Marc Schink 4a4ca07da7 target/arm_tpiu: Fix 'tpiu create' parameter check
The current implementation crashes when executing 'tpiu create'
without an object name due to an invalid memory access. Pass 'argv'
instead 'goi.argv' to fix the problem.

While at it, match the style of the error message to the style used for
other Tcl commands. Especially, make the 'name' parameter mandatory.

Change-Id: Ib2b233f8556934af61608ae93d6405585c2c40b7
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6329
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2022-03-05 13:23:33 +00:00
Marc Schink 29e2a74516 target/arm_tpiu: Make error message easier to understand
Change-Id: Idddc31e34a67641c32d041c89d01fe2126ec5ddb
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6328
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-05 13:23:00 +00:00
Marc Schink e8e62c5aca target/tcl: Add get_reg function
Change-Id: Id1be9554d1df2c07cec3161a0fd3a586fdf18246
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/5312
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-05 13:21:24 +00:00
Marc Schink da73280101 target/tcl: Add set_reg function
Change-Id: I97a01b93046cb7af289792489f77f5580312585a
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/5313
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-05 13:11:25 +00:00
Tim Newsome 9e097d0fc4
From upstream (#684)
* flash/nor/atsame5: add LAN9255 devices

Support Microchip LAN9255 devices with embedded SAME53J MCU.

Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>
Change-Id: Ia811c593bf7cf73e588d32873c68eb67c6fafad7
Reviewed-on: https://review.openocd.org/c/openocd/+/6811
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* tcl/board: Add EVB-LAN9255 config

Config for EVB-LAN9255, tested using Atmel-ICE debugger on J10
connector.

Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>
Change-Id: I8bcf779e9363499a98aa0b7d10819c53da6a19e7
Reviewed-on: https://review.openocd.org/c/openocd/+/6812
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* aarch64: support for aarch32 ARM_MODE_UND

Fix:
unrecognized psr mode: 0x1b
cannot read system control register in this mode: (UNRECOGNIZED : 0x1b)

Change-Id: I4dc3e72f90d57e52c0fe63cb59a7529a398757b3

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Change-Id: Ifa5d21ae97492fde9e8c79ee7d99d8a2a871b1b5
Reviewed-on: https://review.openocd.org/c/openocd/+/6808
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Combine register lists of smp targets.

This is helpful when you want to pretend to gdb that your heterogeneous
multicore system is homogeneous, because gdb cannot handle heterogeneous
systems. This won't always works, but works fine if e.g. one of the
cores has an FPU while the other does not. (Specifically, HiFive
Unleashed has 1 core with no FPU, plus 4 cores with an FPU.)

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I05ff4c28646778fbc00327bc510be064bfe6c9f0
Reviewed-on: https://review.openocd.org/c/openocd/+/6362
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* semihosting: use open mode flags from GDB, not from sys/stat.h

Values defined in sys/stat.h are not guaranteed to match
the constants defined by the GDB remote protocol, which are defined in
https://sourceware.org/gdb/onlinedocs/gdb/Open-Flags.html#Open-Flags.
On my local system (Manjaro 21.2.1 x86_64), for example, O_TRUNC is
defined as 0x40, whereas GDB requires it to be 0x400,
causing all "w" file open modes to misbehave.

This patch has been tested with STM32F446.

Change-Id: Ifb2c740fd689e71d6f1a4bde1edaecd76fdca910
Signed-off-by: Pavel Kirienko <pavel.kirienko@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6804
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* semihosting: User defined operation, Tcl command exec on host

Enabling a portion (0x100 - 0x107) of the user defined semihosting
operation number range (0x100 - 0x1FF) to be processed with the help of
the existing target event mechanism, to implement a general-purpose Tcl
interface for the target available on the host, via semihosting
interface.

Example usage:
- The user configures a Tcl command as a callback for one of the newly
	defined events (semihosting-user-cmd-0x10X) in the configuration
	file.
- The target can make a semihosting call with <opnum>, passing optional
	parameters for the call.

If there is no callback registered to the user defined operation number,
nothing happens.

Example usage: Configure RTT automatically with the exact, linked
control block location from target.

Signed-off-by: Zoltán Dudás <zedudi@gmail.com>
Change-Id: I10e1784b1fecd4e630d78df81cb44bf1aa2fc247
Reviewed-on: https://review.openocd.org/c/openocd/+/6748
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/smp: use a struct list_head to hold the smp targets

Instead of reinventing a simply linked list, reuse the list helper
for the list of targets in a smp cluster.
Using the existing helper, that implements a double linked list,
makes trivial going through the list in reverse order.

Change-Id: Ib36ad2955f15cd2a601b0b9e36ca6d948b12d00f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6783
Tested-by: jenkins

* helper/list: add list_for_each_entry_direction()

Use a bool flag to specify if the list should be forward or
backward iterated.

Change-Id: Ied19d049f46cdcb7f50137d459cc7c02014526bc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6784
Tested-by: jenkins

* target/riscv: revive 'riscv resume_order'

This functionality was lost in [1], which was merged as commit
615709d140 ("Upstream a whole host of RISC-V changes.").
Now it works as expected again.

Add convenience macro foreach_smp_target_direction().

Link: [1] https://github.com/riscv/riscv-openocd/pull/567
Change-Id: I1545fa6b45b8a07e27c8ff9dcdcfa2fc4f950cd1
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6785
Tested-by: jenkins

* doxygen: fix some function prototype description

Change-Id: I49311a643ea73143839d2f6bde976cfd76f8c67f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6830
Tested-by: jenkins

* Cadence virtual debug interface (vdebug) integration

Change-Id: I1bc105b3addc3f34161c2356c482ff3011e3f2cc
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6097
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* gdb_server: Include thread name as XML attribute

Explicitly providing a thread name in the "thread" element produces
better thread visualizations in downstream tools like IDEs.

Signed-off-by: Ben McMorran <bemcmorr@microsoft.com>
Change-Id: I102c14ddb8b87757fa474de8e3a3f6a1cfe10d98
Reviewed-on: https://review.openocd.org/c/openocd/+/6828
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Fix small memory leak.

See https://github.com/riscv/riscv-openocd/pull/672

Change-Id: Ia11ab9bcf860f770ea64ad867102c74b898f6b66
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6831
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* server: remove remaining crust from dropped eCos code

Commit 39650e2273 ("ecosboard: delete bit-rotted eCos code") has
removed eCos code but has left some empty function that was used
during non-eCos build to replace eCos mutex.

Drop the functions and the file that contain them.

Change-Id: I31bc0237ea699c11bd70921660f960ee406ffa80
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6835
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* rtos: threadx: Add hla_target support for ThreadX

Tested with an AZ3166 dev board (which uses the STM32F412ZGT6) running
the Azure RTOS ThreadX demonstration system.

Signed-off-by: Ben McMorran <bemcmorr@microsoft.com>
Change-Id: I44c8f7701d9f1aaa872274166321cd7d34fb1855
Reviewed-on: https://review.openocd.org/c/openocd/+/6829
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* .gitmodules: switch away from repo.or.cz

The host repo.or.cz is often offline, creating issues for cloning
and building OpenOCD from scratch.
Already 'jimtcl' developer has dropped repo.or.cz, triggering the
OpenOCD commit 861e75f54e ("jimtcl: switch to github").

Change also the link of the remaining submodules 'git2cl' and
'libjaylink' to their respective main repository.

Change-Id: Ib513237427635359ce36a480a8f2060e2fb12ba4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6834
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>

* flash/nor/stm32f2x: Fix erase of bank 2 sectors

This commit corrects the erase function for stm32f2x when dealing with
sectors in bank 2, for STM32F42x/43x devices with 1MB flash.

On STM32F42x/43x with 1MB flash in dual bank configuration, the sector
numbering is not consecutive. The last sector in bank 1 is number 7, and
the first sector in bank 2 is number 12.
The sector indices used by openocd, however, _are_ consecutive (0 to 15
in this case). The arguments "first" and "last" to stm32x_erase() are of
this type, and so the logic surrounding sector numbers needed to be
corrected.
Since the two banks in dual bank mode have the same number of sectors, a
sector index in bank 2 is larger than or equal to half the total number
of sectors.

Change-Id: I15260f8a86d9002769a1ae1c40ebdf62142dae18
Signed-off-by: Simon Johansson <ampleyfly@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6810
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* target/cortex_m: fix target_to_cm() helper

The third parameter of container_of() should point to the same member
as target->arch_info points to, struct arm.

It worked just because struct arm is the first member in
struct armv7m_common.
If you move arm member from the first place, OpenOCD fails heavily.

Change-Id: I0c0a5221490945563e17a0a34d99a603f1d6c2ff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6749
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/armv7m,cortex_m: introduce checked arch_info cast routines

target_to_armv7m() and target_to_cm() do not match the magic number
so they are not suitable for use outside of target driver code.

Add checked versions of pointer getters. Match the magic number
to ensure the returned value points to struct of the correct type.

Change-Id: If90ef7e969ef04f0f2103e0da29dcbe8e1ac1c0d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6750
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/cortex_m: add Cortex-M part number getter

The getter checks the magic numbers in arch_info to detect eventual
type mismatch.

Change-Id: I61134b05310a97ae9831517d0516c7b4240d35a5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6751
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* flash/nor/stm32xx: fix segfault accessing Cortex-M part number

Some of STM32 flash drivers read Cortex-M part number from
cortex_m->core_info.
In corner cases the core_info pointer was observed uninitialised
even if target_was_examined() returned true. See also [1]

Use the new and safe helper to get Cortex-M part number.

While on it switch also target_to_cm()/target_to_armv7m() to the safe
versions. This prevents a crash when the flash bank is misconfigured
with non-Cortex-M target.

Add missing checks for target_was_examined() to flash probes.

[1] 6545: fix crash in case cortex_m->core_info is not set
    https://review.openocd.org/c/openocd/+/6545

Change-Id: If2471af74ebfe22f14442f48ae109b2e1bb5fa3b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Fixes: f5898bd93f (flash/stm32fxx.c: do not read CPUID as this info is stored in cortex_m_common)
Reviewed-on: https://review.openocd.org/c/openocd/+/6752
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* cpld: altera-epm240: Add additional IDCODEs

This adds some additional IDCODEs from the datasheet. It also adds
support for customizing the tap name.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I7cda10b92c229b61836c12cd9ca410de358ede2e
Reviewed-on: https://review.openocd.org/c/openocd/+/6846
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* cpld: altera-epm240: Increase adapter speed

According to the datasheet, the minimum clock period with Vccio1 = 1.5V
(the lowest voltage supported) is 143ns, or around 6MHz. Set the default
adapter speed to 5 MHz.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de
Reviewed-on: https://review.openocd.org/c/openocd/+/6847
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target: Add support for ls1088a

The LS1088A is an octo-core aarch64 processor from NXP in the layerscape
family. The JTAG is undocumented, but I was able to figure things out
from the output of `dap info`. This is the first in-tree example of
using the hwthread rtos (as far as I know), so hopefully it can serve as
an example to other developers. There are some ETMs, but I was unable to
try them out because I got 'invalid command name "etm"' when trying to
test things out.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I9b0791d27d8c41170a413a8d86431107a85feba2
Reviewed-on: https://review.openocd.org/c/openocd/+/6848
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target: ls1088a: Add service processor

Normally the service processor is not necessary for debugging. However,
if you are using the hard-coded RCW or your boot source is otherwise
corrupt, then the general purpose processors will never be released from
hold-off. This will cause GDB to become confused if it tries to attach,
since they will appear to be running arm32 processors. To deal with
this, we can release the CPUs manually with the BRRL register. This
register cannot be written to from the axi target, so we need to do it
from the service processor target. This involves halting the service
processor, modifying the register, and then resuming it again. We try
and determine what state the service processor was in to avoid resuming
it if it was already halted.

The reset vector for the general purpose processors is determined by the
boot logation pointer registers in the device configuration unit.
Normally these are set using pre-boot initialization commands, but if
they are not set then they default to 0. This will cause the CPU to
almost immediately hit an illegal instruction. This is fine because we
will almost certainly want to attach to the processor and load a program
anyway.

I considered adding this as an event handler for either gdb-attach or
reset-init. However, this command shouldn't be necessary most of the
time, and so I don't think we should run it automatically.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I1b725292d8a11274d03af5313dc83678e10e944c
Reviewed-on: https://review.openocd.org/c/openocd/+/6850
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* board: Add NXP LS1088ARDB

This adds a board file for the NXP LS1088ARDB. This only covers the
"primary" JTAG header J55, and not the PCIe header (J91). The only
oddity is that the LS1088A and CPLD are muxed by adding/removing a
jumper from J48. Unfortunately, it doesn't look like OpenOCD supports
this CPLD beyond determining the irlen, so it's not very useful. Those
who are interested in experimenting can define CWTAP to access the CPLD,
but the default is to access the CPU.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: Ia07436a534f86bd907aa5fe2a78a326a27855a24
Reviewed-on: https://review.openocd.org/c/openocd/+/6849
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* gdb_server: fix double free

Commit 6541233aa7 ("Combine register lists of smp targets.")
unconditionally assigns the output pointers of the function
smp_reg_list_noread(), even if the function fails and returns
error.
This causes a double free from the caller, that has assigned NULL
to the pointers to simplify the error handling.

Use local variables in smp_reg_list_noread() and assign the output
pointers only on success.

Change-Id: Ic0fd2f26520566cf322f0190780e15637c01cfae
Fixes: 6541233aa7 ("Combine register lists of smp targets.")
Reported-by: Michele Bisogno <michele.bisogno.ct@renesas.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6852
Tested-by: jenkins
Reviewed-by: Michele Bisogno <michele.bisogno.ct@renesas.com>
Reviewed-by: Tim Newsome <tim@sifive.com>

* gdb_server: check target examined while combining reg list

Commit 6541233aa7 ("Combine register lists of smp targets.")
assumes that all the targets in the SMP cluster are already
examined and unconditionally call target_get_gdb_reg_list_noread()
that will in turn return error if the target is not examined yet.

Skip targets not examined yet.
Add an additional check in case the register list cannot be built,
e.g. because no target in the SMP cluster is examined. This should
never happen, but it's better to play safe.

Change-Id: I8609815c3d5144790fb05a870cb0c931540aef8a
Fixes: 6541233aa7 ("Combine register lists of smp targets.")
Reported-by: Michele Bisogno <michele.bisogno.ct@renesas.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6853
Tested-by: jenkins
Reviewed-by: Michele Bisogno <michele.bisogno.ct@renesas.com>
Reviewed-by: Tim Newsome <tim@sifive.com>

* flash/stm32l4x: fix maybe-uninitialized compiler error

using gcc (Ubuntu 9.3.0-17ubuntu1~20.04) 9.3.0 we get:
error: ‘retval’ may be used uninitialized in this function

fixes: 13cd75b6ec (flash/nor/stm32xx: fix segfault accessing Cortex-M part number)
Change-Id: I897c40c5d2233f50a5385d251ebfa536023e5cf7
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6861
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Fix build.

Change-Id: Ia60246246dd859d75659a43d1c59588dbb274d46
Signed-off-by: Tim Newsome <tim@sifive.com>

Co-authored-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>
Co-authored-by: Julien Massot <julien.massot@iot.bzh>
Co-authored-by: Pavel Kirienko <pavel.kirienko@gmail.com>
Co-authored-by: Zoltán Dudás <zedudi@gmail.com>
Co-authored-by: Antonio Borneo <borneo.antonio@gmail.com>
Co-authored-by: Jacek Wuwer <jacekmw8@gmail.com>
Co-authored-by: Ben McMorran <bemcmorr@microsoft.com>
Co-authored-by: Simon Johansson <ampleyfly@gmail.com>
Co-authored-by: Tomas Vanek <vanekt@fbl.cz>
Co-authored-by: Sean Anderson <sean.anderson@seco.com>
Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2022-03-03 10:03:55 -08:00
Erhan Kurubas 87c0cda00f
riscv: implement maskisr steponly command (#681)
* riscv: implement maskisr steponly command

Change-Id: I1a3b666d466b064460c3acc307a36485ce165601
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>

* riscv: restore triggers and irq mask inside step function

Change-Id: I4e1b0665f4f2f75e42a6191c61634bdfa19ae2fb
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>

* doc: update for riscv set_maskisr command

Change-Id: Ia7d3a6df846cfc4568d79558f719e93f038aee9b
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2022-03-01 10:05:54 -08:00
Tomas Vanek b53f5c2571 target/cortex_m: add Cortex-M part number getter
The getter checks the magic numbers in arch_info to detect eventual
type mismatch.

Change-Id: I61134b05310a97ae9831517d0516c7b4240d35a5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6751
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2022-02-25 20:26:56 +00:00
Tomas Vanek e4ba76a003 target/armv7m,cortex_m: introduce checked arch_info cast routines
target_to_armv7m() and target_to_cm() do not match the magic number
so they are not suitable for use outside of target driver code.

Add checked versions of pointer getters. Match the magic number
to ensure the returned value points to struct of the correct type.

Change-Id: If90ef7e969ef04f0f2103e0da29dcbe8e1ac1c0d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6750
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-25 19:56:41 +00:00
Tomas Vanek 10b5ac9ccb target/cortex_m: fix target_to_cm() helper
The third parameter of container_of() should point to the same member
as target->arch_info points to, struct arm.

It worked just because struct arm is the first member in
struct armv7m_common.
If you move arm member from the first place, OpenOCD fails heavily.

Change-Id: I0c0a5221490945563e17a0a34d99a603f1d6c2ff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6749
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-25 19:53:18 +00:00
Erhan Kurubas 64f3f8877e
riscv: call debug_execution related events (#679)
Change-Id: Ice7cdc816f3e568a6ba2db8f9101903b8f7a08ce
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2022-02-21 09:02:07 -08:00
Tim Newsome 435a652236
Merge pull request #678 from riscv/invalidate-progbuf-cache
fix progbuf cache: invalidate it when needed
2022-02-15 10:27:16 -08:00
Tim Newsome 2c0a65baa2 Fix small memory leak.
See https://github.com/riscv/riscv-openocd/pull/672

Change-Id: Ia11ab9bcf860f770ea64ad867102c74b898f6b66
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6831
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-14 15:13:11 +00:00
Tim Newsome 49c40a7529 target/riscv: revive 'riscv resume_order'
This functionality was lost in [1], which was merged as commit
615709d140 ("Upstream a whole host of RISC-V changes.").
Now it works as expected again.

Add convenience macro foreach_smp_target_direction().

Link: [1] https://github.com/riscv/riscv-openocd/pull/567
Change-Id: I1545fa6b45b8a07e27c8ff9dcdcfa2fc4f950cd1
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6785
Tested-by: jenkins
2022-02-14 15:10:56 +00:00
Antonio Borneo 16cc853bcf target/smp: use a struct list_head to hold the smp targets
Instead of reinventing a simply linked list, reuse the list helper
for the list of targets in a smp cluster.
Using the existing helper, that implements a double linked list,
makes trivial going through the list in reverse order.

Change-Id: Ib36ad2955f15cd2a601b0b9e36ca6d948b12d00f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6783
Tested-by: jenkins
2022-02-14 15:10:10 +00:00
Jan Matyas 8274cc58c1 fix progbuf cache: another two cases for invalidation
Continuation of the previous patch. There are two more cases
when progbuf cache in OpenOCD shall be invalidated:

- When OpenOCD resets the debug module undergoes reset (dmactive=0),
  e.g. during target examination

- When the user manually performs that very same operation
  (via riscv dmi_write)

Change-Id: I53f8f08250eeedcbd55ab4361d5665370b063680
Signed-off-by: Jan Matyas <matyas@codasip.com>
2022-02-14 14:14:14 +01:00
Jan Matyas feb83b78b7 fix progbuf cache: invalidate it when needed
This commit relates to progbuf cache,
implemented in https://github.com/riscv/riscv-openocd/pull/381

Make sure the cache gets invalidated when the progbuf
contents change via other means. I've identified two
such cases where the invalidation is required:

1) When the user manually tinkers with the progbuf registers
   (TCL command "riscv dmi_write")

2) When program buffer is used as a scratch memory
   (scratch_write64())

Change-Id: Ie7ffb0fccda63297de894ab919d09082ea21cfae
Signed-off-by: Jan Matyas <matyas@codasip.com>
2022-02-14 13:02:56 +01:00
Erhan Kurubas 9fe791ba4a riscv: fix remove_trigger return code for unavailable hw bp slot 2022-02-09 22:42:46 +01:00
Zoltán Dudás 5ab74bde06 semihosting: User defined operation, Tcl command exec on host
Enabling a portion (0x100 - 0x107) of the user defined semihosting
operation number range (0x100 - 0x1FF) to be processed with the help of
the existing target event mechanism, to implement a general-purpose Tcl
interface for the target available on the host, via semihosting
interface.

Example usage:
- The user configures a Tcl command as a callback for one of the newly
	defined events (semihosting-user-cmd-0x10X) in the configuration
	file.
- The target can make a semihosting call with <opnum>, passing optional
	parameters for the call.

If there is no callback registered to the user defined operation number,
nothing happens.

Example usage: Configure RTT automatically with the exact, linked
control block location from target.

Signed-off-by: Zoltán Dudás <zedudi@gmail.com>
Change-Id: I10e1784b1fecd4e630d78df81cb44bf1aa2fc247
Reviewed-on: https://review.openocd.org/c/openocd/+/6748
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-05 21:40:17 +00:00
Tim Newsome 7d91f639bb
Merge pull request #674 from riscv/from_upstream
From upstream
2022-02-04 08:47:50 -08:00
Tim Newsome 52ca5d198e
Ask the RTOS which target to set swbp on. (#673)
This lets the RTOS pick the "current" target, which matters if address
translation differs between threads.

Change-Id: I5b5510ab6a06621589c902f42a91562055817dc4
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-01-31 09:23:38 -08:00
Pavel Kirienko dbbac5f11d semihosting: use open mode flags from GDB, not from sys/stat.h
Values defined in sys/stat.h are not guaranteed to match
the constants defined by the GDB remote protocol, which are defined in
https://sourceware.org/gdb/onlinedocs/gdb/Open-Flags.html#Open-Flags.
On my local system (Manjaro 21.2.1 x86_64), for example, O_TRUNC is
defined as 0x40, whereas GDB requires it to be 0x400,
causing all "w" file open modes to misbehave.

This patch has been tested with STM32F446.

Change-Id: Ifb2c740fd689e71d6f1a4bde1edaecd76fdca910
Signed-off-by: Pavel Kirienko <pavel.kirienko@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6804
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-01-29 18:25:21 +00:00
Julien Massot 93f2276cdd aarch64: support for aarch32 ARM_MODE_UND
Fix:
unrecognized psr mode: 0x1b
cannot read system control register in this mode: (UNRECOGNIZED : 0x1b)

Change-Id: I4dc3e72f90d57e52c0fe63cb59a7529a398757b3

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Change-Id: Ifa5d21ae97492fde9e8c79ee7d99d8a2a871b1b5
Reviewed-on: https://review.openocd.org/c/openocd/+/6808
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-01-29 18:20:48 +00:00
Tim Newsome b6fabdd429 Merge branch 'master' into from_upstream
Change-Id: I61e24edbdeceddba265514fd7e0a489ec23e2a4c
2022-01-28 09:40:43 -08:00
Tim Newsome 6f3daf38c7
Fix small memory leak. (#672)
Change-Id: Ia11ab9bcf860f770ea64ad867102c74b898f6b66
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-01-27 10:00:06 -08:00
Antonio Borneo e3bda57982 target: use target_event_name()
We have the API target_event_name().
Use it to improve code readability.

Change-Id: Ic48d2227bdefe9af05aff99a871a45e0612e5254
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6790
Tested-by: jenkins
2022-01-22 10:19:48 +00:00
Antonio Borneo 1536e249f2 aarch64: dump a message when CTI is missing
If the CTI is not specified OpenOCD fails target's examination
without indicating the reason.

Drop an error message about the missing CTI.

Change-Id: I344537fb21cf38785796ba938e71890e04135509
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6788
Tested-by: jenkins
2022-01-22 10:15:01 +00:00
Tim Newsome cc0ecfb6d5 Merge branch 'master' into from_upstream
Conflicts:
	doc/openocd.texi
	src/flash/nor/fespi.c

Change-Id: Iaac61cb6ab8bba9df1d4b9a52671a09163eb50b2
2021-12-28 10:45:40 -08:00
Tim Newsome 3ba21e5f00 target/riscv: calloc() memory per register.
This replaces a static array with 8 bytes per register. When there are
vector registers larger than 8 bytes, they would end up clobbering each
other's values. I can't believe I didn't catch this earlier.

See https://github.com/riscv/riscv-openocd/pull/658

Change-Id: I9df4eaf05617a2c8df3140fff9fe53f61ab2b261
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6775
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-12-24 15:10:20 +00:00
Antonio Borneo 9828c0a440 semihosting: use macro COMMAND_HANDLER
We have the macro
	#define COMMAND_HANDLER(name) \
		static __COMMAND_HANDLER(name)
Use it!

Change-Id: I0e5385cb54197c743348f0d2ce215c93b8e396a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6786
Tested-by: jenkins
2021-12-24 15:07:26 +00:00
Tomas Vanek 33fa237b2f target/cortex_m: minor refactoring in cortex_m_store_core_reg_u32()
Unlike cortex_m_load_core_reg_u32() storing core register uses
the same code pattern around DHCSR read as offered by the convenience
helper cortex_m_read_dhcsr_atomic_sticky().

Use the helper.

Change-Id: Ia947204944a8b549f3c2be7fb2f717aad18970c4
SeeAlso: 65d7629183 (cortex_m: poll S_REGRDY on register r/w)
SeeAlso: 0dcf95c717 (target/cortex_m: cumulate DHCSR sticky bits)
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6767
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-12-18 17:23:04 +00:00
Bohdan Tymkiv 71ca3a1349 target/arm_jtag.h: fix wrong comparison in arm_jtag_set_instr
Change [1] introduced a regression that results in comparison
in arm_jtag_set_instr() to be always true if the length of the
IR register is not 8 bit. The value on the left side
of the != operator contains only tap->ir_length number of
bits while value on the right is full 8-bit instruction code.

This forces OpenOCD to update the JTAG IR register on each
transaction even if the instruction in the JTAG IR register
is correct. This causes noticeable performance degradation,
especially with slow JTAG adapters.

[1] https://review.openocd.org/c/openocd/+/6285

time ./src/openocd -s tcl/ -f interface/cmsis-dap.cfg \
  -c "transport select jtag" -f target/psoc6.cfg \
  -c "init; load_image data.bin 0x08000000; exit"

Without this change:
real    0m4,863s
user    0m0,074s
sys     0m0,128s

With this change:
real    0m3,083s
user    0m0,038s
sys     0m0,098s

Signed-off-by: Bohdan Tymkiv <bohdan200@gmail.com>
Change-Id: Iaded83a04ecc7e65f18256afae582267ccc1fc59
Reviewed-on: https://review.openocd.org/c/openocd/+/6762
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-12-11 17:49:30 +00:00
Yasushi SHOJI d7142a5727 target/target: Check checksum_memory before call
Make sure checksum_memory is present.  Otherwise it'll segfault.

Change-Id: If31123323bd8a03282da43505c9604fde735ad0e
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6758
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-12-11 17:41:46 +00:00
Antonio Borneo 68ec9d2175 adi_v5_swd: add jtag-to-swd through dormant
ARM IHI 0031A does not support SWJ-DP, so no switch between JTAG
and SWD is considered.
ARM IHI 0031B is not publicly available and it's reported as
"Confidential Beta" in the history list in following doc versions.
From ARM IHI 0031C the direct switch between JTAG and SWD is
already deprecated in favor of passing through dormant mode. With
no access to IHI 0031B we haven't info if any device strictly
requires the direct switch.

OpenOCD implements only the deprecated direct switch, so changing
it could cause regression on devices that do not implement dormant
mode.
Plus, not all the adapters support dormant mode.

Nevertheless there are already target devices that only allow
entering in SWD by passing through dormant.

Let the code try both method, alternating one tentative with the
deprecated legacy direct switch, then another tentative passing
through dormant, and repeat till timeout.
This would work on any device that don't support dormant, on new
devices that require switch through dormant and will work with
adapters that don't support dormant.

Change-Id: Ib8619635277d497872079a33fa4e38be9beb84a0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6695
Tested-by: jenkins
2021-12-11 17:39:58 +00:00
Antonio Borneo 8a448573fb cortex_m: remove last references to debugport_init()
The function debugport_init() has never existed in OpenOCD code,
but few comments erroneously references it in place of the
existing function ahbap_debugport_init().

Commit 00dbc185ee ("arm_adi_v5: Split ahbap_debugport_init")
splits the function ahbap_debugport_init() in dap_dp_init() and
mem_ap_init(), but did not removed all the incorrect comments
about debugport_init(). Few of such comments has been removed in
later patches.

Remove the last comment that references debugport_init().

Change-Id: Ibd1f125475386e5653340fedf706903a0ee15897
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6694
Tested-by: jenkins
2021-12-11 17:32:10 +00:00
Tim Newsome cb4876d80c
Merge pull request #665 from riscv/examined
Don't reexamine targets until it's time.
2021-12-03 14:34:07 -08:00
Tomas Vanek f735faa931 target,flash: allow target_free_working_area on NULL area pointer
Standard C library free() allows NULL pointer as a parameter.

Change target_free_working_area() to conform this convention.

Remove NULL pointer tests before target_free_working_area() calls.

While on it add missing setting pointer to NULL after target_free_working_area().

Change-Id: I7c692ab04a9933398ba5bc614723ad0bdecb87b3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6712
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-12-03 21:59:20 +00:00
Tim Newsome 61a3f65a0c Merge branch 'master' into from_upstream
Merged 1ad6ed38b6

Conflicts:
	src/rtos/rtos_standard_stackings.c

Change-Id: Ica8109135de0f9aa87455353a4538b161b844b04
2021-11-30 10:38:55 -08:00
Tim Newsome f631c906fa Don't reexamine targets until it's time.
Don't reexamine targets until we're past the examine stage of init().
Earlier than that, examine() will likely fail because the scan chain
hasn't been examined yet.

This will likely fix #663.

Change-Id: I76ee9181f35cedcdb1a3e0f8ac33ab361c68d3af
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-11-29 17:57:04 -08:00
Tomas Vanek f66a16c4a0 target/hla_target: set cortex_m->common_magic
hla_target uses the same struct cortex_m_common as the standard cortex_m
target. Unlike the cortex_m target hla missed setting of common_magic.

Set commont_magic to help pointer verification.

Add convenience tests is_cortex_m_or_hla() and
is_cortex_m_with_dap_access()

Use proper test in cortex_m_verify_pointer() - this code relied on
unset common_magic on hla target before the change.

Change-Id: I4dae79f056c3d73adf524e26aa8ef2d3a57b471e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6741
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-11-25 09:47:28 +00:00
Tim Newsome 0b965363a6
Deal with halt race. (#664)
* Deal with halt race.

What could happen:
1. hart 1 halts due to a breakpoint
2. OpenOCD polls and notices hart 1 has halted.
3. hart 0 halts because it is in a halt group with halt 1
4. OpenOCD decides to halt hart 0 also.
5. OpenOCD discovers hart 0 is already halted, and doesn't update the
debug reason.

In that case OpenOCD would tell gdb that hart 0 halted, while the
interesting event is that hart 1 halted.

Fix this by updating the debug reason when we discover a hart is already
halted when we try to halt it.

This race was exposed in the Sv* address translation tests, but the bug
has nothing to do with address translation.

Change-Id: I59d871e8545bd644bf42581266f15234b93e9900
Signed-off-by: Tim Newsome <tim@sifive.com>

* Comment set_debug_reason

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2021-11-24 10:20:15 -08:00
Antonio Borneo b46cb18c91 openocd: use unique name for struct command_registration
Just to avoid name clash when comparing documentation with
registered commands through scripts.

Change-Id: I8832545d8d9236ea5dabe6e73732f51e5246caff
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6717
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2021-11-23 11:04:02 +00:00
Antonio Borneo b5d1b719e5 openocd: use single line for register_commands*()
Do not split in multiple lines the calls to register_commands*().
No change in code behaviour, just make it easy to grep in the code
and identify the commands that can be registered.
This would help detecting undocumented commands.

Change-Id: Id654e107cdabf7ee31fc3d227c1d2a59acc5669e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6716
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-11-23 11:03:38 +00:00
Tomas Vanek 8d9379c9ba target/arm_dap: check SWD DAP configuration
Raise error if

* more than one plain SWD DAPs are defined

* plain and multidrop DAPs are mixed

* two multidrop DAPs have the same TARGETSEL value

Inspired by Graham Sanderson's http://review.openocd.org/4935

Change-Id: I7279744464f5cc6477e50695c596be9c5e5507bf
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6142
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-11-20 14:48:26 +00:00
Tomas Vanek d203399787 target/adi_v5_swd: add support for SWD multidrop
Based on Graham Sanderson's http://review.openocd.org/4935

Unlike Graham Sanderson's version this patch does not add
any multidrop specific queuing.

Multidrop SWD is handled mostly by the same code as single SWD,
just a selection sequence is prepended to a SWD operation
as needed.

This is a minimal working implementation without checking for
configuration errors (mixing multidrop and non multidrop DPs,
multiple use of the same selection id etc...).

Multidrop switching likely demands changes in the adapter code.

Change-Id: I99a5742c209b49c0483e800f6105cb5e59a897d9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6141
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-11-20 14:47:54 +00:00
Tomas Vanek b973a76d86 target/arm_adi_v5,arm_dap: introduce multidrop_targetsel and its configuration
Add multidrop_targetsel to struct adiv5_dap.
Add option -dp-id and -instance-id to dap create command.
Add convenience function dap_is_multidrop()

Change-Id: Ibb93abb5f50b3665c320a10c1497421035762134
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6140
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-11-20 14:47:04 +00:00
Tomas Vanek bb78fa10c7 target/arm_dap: clean up dap_configure code
dap_configure() contained first time init related tasks, as the call to
dap_init_instance() and the check for configured tap.

Move all first time init related stuff to dap_create() to make dap_configure()
usable in eventual stand-alone 'dap configure' command.

Change-Id: Ia86eadb4e960ce54e8581630d01af75720d2318d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6702
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2021-11-20 14:45:54 +00:00
Tomas Vanek 81afe6e3fd target/adi_v5_swd: introduce swd_queue_dp_read/write_inner()
This is a preparatory change for swd multidrop, mostly refactoring.

Split swd_queue_dp_read/write() to inner and outer parts.
Use the inner parts in swd_queue_dp_bankselect(), swd_connect()
they do not need to check reconnect.
Use the outer parts exclusively in swd_dap_ops.

Rearrange the code to reduce forward declarations.

Change-Id: I47b7f0cb037e0032a267463f06ba02123ba96fe7
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6139
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2021-11-20 14:45:35 +00:00
Tomas Vanek 3eef83e4bd target/arm_dap: fix memory leak in error path of dap_create()
Change-Id: I91fa5910670161b62a76fc834b6394c5a6c05395
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6685
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-11-20 14:44:38 +00:00
Tim Newsome 8457a1be10 target: Use target_addr_t for algorithm addresses.
Otherwise 64-bit addresses can't work.

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: Id9f92ff8a1602153cc06810bcf515a9d0a89c81b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6662
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-11-20 14:41:38 +00:00
Tim Newsome 6441fe8d9d riscv: Clear type 6 triggers on connecting.
I missed this when I first add mcontrol6 support.

https://github.com/riscv/riscv-openocd/pull/648

Change-Id: I1a2706c7ea3a6757ed5083091cd2c764a8b0267c
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6684
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-11-20 14:39:52 +00:00
Jan Matyas f8bd2566a9 riscv: Regenerated debug_defines.h and encoding.h
The main intention is to get access to some of the CSRs
that were so far unknown to OpenOCD (tinfo, mcountinhibit, ...).

https://github.com/riscv/riscv-openocd/pull/659

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I824fdb558d5c1f73432b0f56f3b0b4d865eceeba
Reviewed-on: https://review.openocd.org/c/openocd/+/6682
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-11-20 14:39:13 +00:00
Antonio Borneo d385dfbab4 adi_v5_swd: add comment to describe debug flag 'do_sync'
Change-Id: I1f7f0eed7a6e3626f5fde841ec7fa1d29906db29
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6696
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-11-20 14:37:46 +00:00
Antonio Borneo 0432ac8399 arm_adi_v5: add missing enum DORMANT_TO_JTAG
Add the value DORMANT_TO_JTAG in the enum listing the SWJ-DP
switching sequences.
The corresponding bit-sequence is already available.

Change-Id: I6f1ffd29a8f5729ec70ce0303248bc251409d37d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6689
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2021-11-20 14:27:52 +00:00
Andreas Fritiofson caa1698136 cortex_m: Restore fast register reads if no polling is needed
If the target is in a state where S_REGRDY polling is necessary (slow
clock, low power state...?), OpenOCD will continue to use the slow
path even if the condition is temporary and the target at a later
point would be capable of fast reads again.

Revert to fast reads if a full register dump can be made without need
for polling any of the registers; presumably it will succeed the next
time too.

Change-Id: I557f0d90b7ce6f9d81aa409b6400fc9c83d16008
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6678
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-11-18 21:13:19 +00:00
Tomas Vanek 88f429ead0 target/cortex_m: faster reading of all CPU registers
Without the change cortex_m_debug_entry() reads all registers
calling cortex_m_load_core_reg_u32() for each register with
a poor usage of JTAG/SWD queue.
It is time consuming, especially on an USB FS based adapter.
Moreover if target_request debugmsgs are enabled, DCB_DCRDR
is saved and restored on each register read.

This change introduces cortex_m_fast_read_all_regs()
which queues all register reads and a single dap_run() transaction
does all work.

cortex_m_fast_read_all_regs() reads all registers unconditionally
regardless register cache is valid or not. This is a difference
from the original cortex_m_debug_entry() code.

cortex_m_debug_entry times from -d3 log, Cortex-M4F and CMSIS-DAP
(Kinetis K28F-FRDM kit)

target_request |                time [ms]
debugmsgs      | without the change | with the change
---------------+--------------------+-----------------
disable        |        186         |       27
enable         |        232         |       29

Added checking of DHCSR.S_REGRDY flag. If "not ready" is seen,
cortex_m->slow_register_read is set and fallback to the old
register read method cortex_m_slow_read_all_regs() is used
instead of cortex_m_fast_read_all_regs().

Change-Id: I0665d94b97ede217394640871dc451ec93410254
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/5321
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-11-18 21:09:34 +00:00
Antonio Borneo 65d7629183 cortex_m: poll S_REGRDY on register r/w
Accordingly to arm documentation [1], chapter C1.6.4, the
operation to read/write from/to core registers can require time,
and the specific flag DHCSR.S_REGRDY has to be polled to verify
that the operation has been completed.
The lack of check on S_REGRDY causes OpenOCD to fail handling
correctly the core registers on a Cortex-M4 emulated in a slow
FPGA, and it could also fail on devices clocked at very low speed
while using a fast adapter.

Poll S_REGRDY as specified in [1] while either reading or writing
the core registers.
A timeout of 0.5s is added. This could still be too small in some
extremely slow cases, but at least now we log the timeout event,
which can help tracking down such odd issue.
During register read include in the polling loop the read of DCRSR
and to flush the JTAG queue only once.
During register write, relax the write in DCRSR by removing the
atomicity that is now useless since followed by the atomic read to
S_REGRDY.
During register read include the read of DCRSR inside the polling
loop to relax the read of S_REGRDY since followed by the atomic
read to DCRSR.

This change has the drawback of adding other transfers to the
adapter while reading/writing the registers, so it is expected to
introduce some speed degradation during step-by-step.

[1] DDI0403E - "ARMv7-M Architecture Reference Manual"

Change-Id: I61f454248f11a3bec6dcf4c58a50c5c996d7ef81
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/5319
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-11-18 21:08:37 +00:00
Tomas Vanek 0dcf95c717 target/cortex_m: cumulate DHCSR sticky bits
DCB DHCSR register contains S_RETIRE_ST and S_RESET_ST bits cleared
on a read.

The change introduces a helper function cortex_m_cumulate_dhcsr_sticky().
Call this function each time DHCSR is read to preserve S_RESET_ST state
in the case of a reset event was detected.

Introduce cortex_m_read_dhcsr_atomic_sticky() convenience helper to
read DHCSR, store it to cortex_m->dcb_dhcsr and cumulate sticky bits.

The cumulated state of S_RESET_ST is read and cleared in cortex_m_poll()

Change-Id: Ib679599f850fd219fb9418c6ff32eed7cf5740da
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6180
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-11-18 21:08:00 +00:00
Tomas Vanek 111dcbeb1a target/cortex_m: use cortex_m->dcb_dhcsr in cortex_m_soft_reset_halt()
cortex_m->dcb_dhcsr caches status of DHCSR register.
Use it instead of local variable in cortex_m_soft_reset_halt()
like in other code.

Extracted from [1].

[1] Antonio Borneo: 6207: cortex_m: rework handling of dcb_dhcsr

Link: https://review.openocd.org/c/openocd/+/6207
Change-Id: I9a0aeba0b6b0b4969f05f4a32fc2fc8d244f56ca
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6677
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-11-18 21:07:46 +00:00
Tomas Vanek b502947a14 cortex_m: use cortex_m_write_debug_halt_mask() in cortex_m_single_step_core()
cortex_m_single_step_core() used mem_ap_write_atomic_u32() to manipulate
dhcsr bits unlike the rest of code, where a specialized function
cortex_m_write_debug_halt_mask() takes place.

Unify setting of dhcsr bits and use cortex_m_write_debug_halt_mask() here as well.

Extracted from [1].

[1] Antonio Borneo: 6207: cortex_m: rework handling of dcb_dhcsr

Link: https://review.openocd.org/c/openocd/+/6207
Change-Id: I9ef05ce88a9dce42e1d3d5404a4fe87ec86b5fe8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6676
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-11-18 21:07:27 +00:00
Antonio Borneo 3c50288612 jtag: align adapter speed code to new structure
Rename the jtag_XXX functions as adapter_XXX.
Rename internal variables.
Adapt log messages and comments text.

Change-Id: I67f209c67074899cd58bad495055def03f0d1bcf
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6644
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-11-13 10:50:34 +00:00
Antonio Borneo 679dcd0b52 jtag: move prototype of adapter init/quit and speed to adapter.h
After moved the code, align the include files.

Change-Id: I514a3020648816810d69f76c2ec4f6e52a1c57ab
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6643
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-11-13 10:49:59 +00:00
Tim Newsome f4f8b59f62
Properly save/restore vtype.ill (#661)
Change-Id: I2478be8a849ceb4f637bbcfb774099217c509dfd
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-11-12 11:29:00 -08:00
Jan Matyas 641e51ff7f
Regenerated debug_defines.h and encoding.h (#659)
The main intention is to get access to some of the CSRs
that were so far unknown to OpenOCD (tinfo, mcountinhibit, ...).
2021-11-04 09:48:23 -07:00
Tim Newsome b1f244b823 Revive `riscv resume_order`
This functionality was lost in #567. Now it works as expected again.

Change-Id: I11a36e076867c0268034ceee763e28b2d4e6ff0f
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-11-03 10:44:13 -07:00
Tim Newsome d97da0eb74
Merge pull request #655 from riscv/from_upstream
From upstream
2021-11-02 09:55:28 -07:00
Tim Newsome 0ac6930d0c
calloc() memory per register. (#658)
This replaces a static array with 8 bytes per register. When there are
vector registers larger than 8 bytes, they would end up clobbering each
other's values. I can't believe I didn't catch this earlier.

Change-Id: I9df4eaf05617a2c8df3140fff9fe53f61ab2b261
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-11-02 09:55:07 -07:00
Tim Newsome 70196c140c
Don't invalidate register cache of halted target. (#657)
This causes trouble if you disconnect/reconnect gdb, because in that
case a halt is issued again. (It probably would be possible to run into
this problem in other ways as well.)

Change-Id: Id5815f9d1dc2c2dd627770e001c03874a307c279
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-10-29 10:43:22 -07:00
Tim Newsome 9d9e324843
Merge branch 'riscv' into from_upstream 2021-10-29 10:38:26 -07:00
Tim Newsome 897cc3f224
Flush register cache when disconnecting or polling (#656)
This makes things work as expected when OpenOCD disconnects and then
connects again. (This became a problem in #645, which started using the
cache.)

Change-Id: I764e5b410a1a68ca47d2ec39968085618ee363c2
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-10-28 12:52:13 -07:00
Tim Newsome 108231c31d Merge branch 'master' into from_upstream
This primarily contains the large upstreaming of RISC-V changes, so lots
more RISC-V changes than usual.

Conflicts:
	src/target/riscv/opcodes.h
	src/target/riscv/riscv-011.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h

Change-Id: I1145dad538a5470ad209848572e6b0f560b671e9
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-10-25 10:20:31 -07:00
Antonio Borneo 0fb131c23a riscv: use relative path to include contrib's data
Doxygen cannot resolve the path of the files in folder contrib.
Use a path relative to current folder, as done in other files.

Change-Id: If39b416ed422b4854dd108777fa32dd4c809450a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6635
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
2021-10-25 16:12:54 +00:00
Antonio Borneo 37bce98395 openocd: remove 'src' prefix from #include path
There is no reason to add the 'src' prefix.
Remove it.

Change-Id: Id7d7ee8b3807fb90381cc1d6d545321020bc06c1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6634
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-10-25 16:12:42 +00:00
Tim Newsome 615709d140 Upstream a whole host of RISC-V changes.
Made no attempt to separate this out into reviewable chunks, since this
is all RISC-V-specific code developed at
https://github.com/riscv/riscv-openocd

Memory sample and repeat read functionality was left out of this change
since it requires some target-independent changes that I'll upstream
some other time.

Change-Id: I92917c86d549c232cbf36ffbfefc93331c05accd
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6529
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-10-25 16:12:05 +00:00
Antonio Borneo 8f1971295b mips64_pracc: fix three dead assignments
Clang scan-build complains for three dead assignments:
	Although the value stored to 'data' is used in the
	enclosing expression, the value is never actually read
	from 'data'

	Value stored to 'address' is never read

Remove the useless assignment and the variable 'data'.

Change-Id: Ie8dcb74b1c1aa5eea1acd06b3c45c5b44954c9e7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6592
Tested-by: jenkins
2021-10-25 16:10:16 +00:00
Antonio Borneo 327040ad74 target/lakemont: fix dead assignment
Clang scan-build complains for a dead assignment:
	Value stored to 'tapstatus' is never read

Remove the assignment and add a comment to point for a potential
removal of the line.

Change-Id: Iad2fdc7e6faf650e24cc086ee74c745acb0d1c73
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6591
Tested-by: jenkins
2021-10-25 16:10:04 +00:00
Antonio Borneo 01de751025 armv8: fix five dead assignments
Clang scan-build complains for five dead assignments:
	Value stored to 'retval' is never read

Check the returned value and propagate the error.

Change-Id: I01172887a056d6f39ddcf2807848423970db1e89
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6590
Tested-by: jenkins
2021-10-25 16:09:26 +00:00
Antonio Borneo 48d74f9711 arm_semihosting: fix two dead assignments
Clang scan-build complains for two dead assignments:
	Value stored to 'r' is never read

Use the variable in the following line, instead of re-computing
the pointer.

Change-Id: I5d4069872be9da85fb28bbe0a82020b90f1efe46
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6589
Tested-by: jenkins
2021-10-25 16:09:12 +00:00
Antonio Borneo 57262ebeae arm_tpiu_swo: fix two dead assignments
Clang scan-build complains for two dead assignments:
	Value stored to 'retval' is never read

Since the timer callback should not return error, print an error
message if the data cannot be send out. Add a FIXME comment
because in current code there is no string/name to report which
connection has failed.

In command tpiu enable check the returned value and propagate the
error.

Change-Id: I9a89e4c4f7b677e8222b2df09a31b2478ac9ca4f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6588
Tested-by: jenkins
2021-10-25 16:09:02 +00:00
Tim Newsome a554e09e7c
Properly handle held-in-reset targets. (#654)
* Properly handle held-in-reset targets.

1. Let OpenOCD continue into some pre-existing code that will periodically
   call examine() until it passes.
2. Fix crash in riscv_openocd_poll()
   When SMP is configured, it's not guaranteed that all targets have been
   examine()d when poll is called on one of them.

Change-Id: Ic6c1d217dc766ea69b67bb2e9a4898e37ee94927
Signed-off-by: Tim Newsome <tim@sifive.com>

* Actually poll for examine at least every 5s.

That's what the comment says the code is trying to do.

Change-Id: I34ff909a98f8aebb3c514e0f3ee403be7699c094
Signed-off-by: Tim Newsome <tim@sifive.com>

* Compact this error message a bit.

Reduces clutter when some targets haven't been properly examined yet.

Change-Id: Id865f191f0fbb48abece8b8558cc9fa2041a26df
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-10-21 17:08:49 -07:00
Tim Newsome c67a887a00 Attempt to fix tracking of examined status.
Fails dual-hart RV64 FreeRTOS test.

Change-Id: If0d6000b0daf116c0efa6072fb545bca9bf54ffe
2021-10-06 13:27:56 -07:00
Tim Newsome 6112814f45 Fix build.
Change-Id: I12f90bed9a1fe470ef3d49f9219227ee0de928b6
2021-10-05 17:47:17 -07:00
Tim Newsome 1775341ef8 Merge branch 'master' into from_upstream
Conflicts:
	src/jtag/drivers/remote_bitbang.c
	src/rtos/rtos_standard_stackings.c
	src/rtos/rtos_standard_stackings.h
	src/target/breakpoints.c
	src/target/riscv/riscv.c
	src/target/target.c

Change-Id: Ia6fcba3d43be8ea31728f3bcc2be6cb7e3ccc5c5
2021-10-05 17:46:02 -07:00
Tim Newsome 5215fc52ab
Fix flashing on HiFive1. (#649)
Broken by #645. It probably broke some other uses as well, but it was
reported (and easy to reproduce) as an issue with flashing.

Change-Id: Ic1b579c1361442479ced14156102ce68ab232396
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-10-05 11:17:24 -07:00
Tim Newsome f139080376
Clear type 6 triggers on connecting. (#648)
I missed this when I first add mcontrol6 support.

Change-Id: I1a2706c7ea3a6757ed5083091cd2c764a8b0267c
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-10-05 10:03:19 -07:00
Yasushi SHOJI 05752557dd helper: Remove src/helper from include dirs
The header files under src/helper/ can currently be included with
either

    #include <bits.h>
    or
    #include <helper/bits.h>

This is because we specify both "src/" and "src/helper/" directories
as include directories.  Some files name under "src/helper/", such as
types.h, log.h, and util.h are too generic and could be ambiguous
depending on the search path.

This commit remove "src/helper/" from our include dir and make C files
include explicitly.

Change-Id: I38fc9b96ba01a513d4a72757d40007e21b502f25
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6507
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-10-02 13:18:15 +00:00
Tarek BOCHKATI 98d9f1168c target: reset target examined flag if target::examine() fails
For example: before this change in cortex_m_examine, if we fail reading CPUID
we return a failure code but target was set to examined which is not consistent.

Change-Id: I9f0ebe8f811849e54d1b350b0db506cb3fdd58f4
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6548
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-10-02 13:15:57 +00:00
Tarek BOCHKATI ba1061fe1d target/cortex_m: enhance multi-core examine logs
Giving the example of STM32WL55x the examine log is the following:
  Info : stm32wlx.cpu0: hardware has 6 breakpoints, 4 watchpoints
  Info : stm32wlx.cpu1: hardware has 4 breakpoints, 2 watchpoints

After this change the examine log becomes:
  Info : stm32wlx.cpu0: Cortex-M4 r0p1 processor detected
  Info : stm32wlx.cpu0: target has 6 breakpoints, 4 watchpoints
  Info : stm32wlx.cpu1: Cortex-M0+ r0p1 processor detected
  Info : stm32wlx.cpu1: target has 4 breakpoints, 2 watchpoints

Change-Id: I1873a75eb76f0819342c441129427b38e984f0df
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6553
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-10-02 13:12:26 +00:00
Antonio Borneo e48093b395 openocd: prevent jimtcl error message while testing commands
The jimtcl API Jim_GetCommand() sets an error message when the
command is not found and flag JIM_ERRMSG is set.
OpenOCD is checking if the command has already been registered,
thus 'command not found' is the desired case.

Pass flag JIM_NONE to prevent jimtcl from setting the error
message.

Change-Id: I3329c2f8722eda0cc9a5f9cbd888a37915b46107
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6562
Tested-by: jenkins
2021-09-25 13:13:28 +00:00
Antonio Borneo 7b504370f7 arm_tpiu_swo: fix support for deprecated 'tpiu' command before 'init'
Commit dc7b32ea4a ("armv7m_trace: get rid of the old tpiu code")
is not handling correctly the old 'tpiu' command if it is run
during the config phase (before command 'init').

Move the call to the old event handler 'trace-config' in function
jim_arm_tpiu_swo_enable(), so it is correctly executed after
'init'.

Add the call to the old event handler 'trace-config' also during
jim_arm_tpiu_swo_disable(), to match the old behaviour.

Add more information while alerting that the event 'trace-config'
is deprecated.

Change-Id: If831d9159b4634c74e19c04099d041a6e2be3f2a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: dc7b32ea4a ("armv7m_trace: get rid of the old tpiu code")
Reviewed-on: https://review.openocd.org/c/openocd/+/6561
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
2021-09-25 13:13:10 +00:00
Antonio Borneo 2a43137619 arm_adi_v5: drop ANY_ID from table dap_part_nums
The initial version of the table dap_part_nums contains only the
part number of the device and not the manufacturer ID.
This causes collisions between devices with same part number but
from different manufacturer.
The table has been extended to include the manufacturer JEDEC code
in commit 2f131d3c30 ("ARM ADIv5: CoreSight ROM decode part
number and designer id").
For two old/legacy table's entries reported without manufacturer
code it was defined a special ANY_ID manufacturer, meaning skip
the check for manufacturer!
The two legacy entries report the comment "from OMAP3 memmap", and
thanks to the associated string has been possible through Google
to identify a Master Report [1] about using OpenOCD with the OMAP3
in a BeagleBoard. The ROM table is printed with OpenOCD command
"dap info 1" at page 8 and reports the Peripheral ID required to
extract the manufacturer ID that, out of any surprise, belong to
Texas Instruments.

Set the two missing manufacturer ID to Texas Instruments JEDEC
code.

Remove the now redundant definition and use of ANY_ID.

While revisiting this old code, remove also the useless comment
"0x113: what?". It was introduced in commit ddade10d4a ("ARM
ADIv5: "dap info" gets more readable") and from the same dump in
[1] it's clearly another element in OMAP3. It is listed as entry
0x8 in the ROM table and there is no further info available.
OpenOCD will anyway list it as:
	Designer is 0x017, Texas Instruments
	Part is 0x113, Unrecognized
Another link https://elinux.org/BeagleBoardOpenOCD reports the
text "Part number 0x113: This is ????", which sounds familiar!
No public document from Texas Instruments reports what is this
device at address 0x54012000.

[1] Warren Clay Grant - University of Texas at Austin
    "Implementation of an Open Source JTAG Debugging Development
    Chain for the BeagleBoard ARM® Cortex A-8" - May 2012
Link: https://repositories.lib.utexas.edu/bitstream/handle/2152/ETD-UT-2012-05-5478/GRANT-MASTERS-REPORT.pdf

Change-Id: I7e007addbb5c6e90303e4e8c110c7d27810fbe9c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6454
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2021-09-25 13:11:41 +00:00
Antonio Borneo 122f36ed7b arm_adi_v5: add arm Neoverse N2 part numbers
Change-Id: Ib7a8c9d460f12762f6d106e9331e84b6d2dec213
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6453
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-09-25 13:11:23 +00:00
Kevin Burke a931c99f5b arm_adi_v5: add arm Neoverse N1 part numbers
Split from change https://review.openocd.org/6077/

Change-Id: I5e3d3736beb741de3940ea6e23b0ccbf47e8dec7
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6452
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-09-25 13:11:10 +00:00
Antonio Borneo 8f73bd3d48 arm_adi_v5: add arm Cortex-R52 part numbers
Extract new part numbers from Arm Cortex-R52 Processor Technical
Reference Manual Revision r1p3 and add them to the array
dap_partnums.

Change-Id: I8020f36de587951af60422ef33d7e438dc7d9d53
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6451
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-09-25 13:07:41 +00:00
Antonio Borneo c55fbe190b arm_adi_v5: add arm SoC-600 part numbers
Extract new part numbers from ARM CoreSight System-on-Chip SoC-600
Technical Reference Manual Revision r4p1 and add them to the array
dap_partnums.

Change-Id: I88d8aa3c084f6e832b75032e75bfb6d377a08360
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6450
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-09-25 13:06:53 +00:00
Antonio Borneo 02b5fa5103 arm_adi_v5: add helper to search for part number
Improve code readability and prepare to re-use the helper.

Change-Id: Iee5e01047c82be3dd86707f5c283f0b20cc4070d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6449
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-09-25 13:06:01 +00:00
Kevin Burke cf6909a57c arm_adi_v5: move in a separate function devtype decode/display
For readability, move in a separate function the decoding and the
display of devtype register.
The function will be reused with ADIv6.

Split from change https://review.openocd.org/6077/

Change-Id: I7a26a2c9759d5db5f9acfae5c169b90b3deb2f18
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6448
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-09-25 13:04:53 +00:00
Antonio Borneo ddbc13a6f2 arm_adi_v5: simplify handling of AP type
The complete AP type should include 'class' and 'manufacturer'.

Cleanup the definition of AP type from AP_REG_IDR register.
Include the check of 'class', together with manufacturer and type.
Add the new MEM-AP from ARM IHI0074C.

Change-Id: Ic8db7c040108ba237b54f73b1abe24b8b853699b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6447
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2021-09-25 13:00:55 +00:00
Antonio Borneo 06d2e430db arm_coresight: add include file and use it
Several magic numbers related to ARM CoreSight specification
IHI0029E are spread around OpenOCD code.

Define through macros the ARM CoreSight magic numbers and collect
them in a single include file.
Use the new macros wherever possible.

Change-Id: I9b0c1c651ce4ffbaf08d31791ef16e95983ee4cb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6446
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2021-09-25 13:00:27 +00:00
Antonio Borneo c4e6034e26 armv7m.h: relax dependency from 'arm_adi_v5.h'
The include file 'armv7m.h' includes 'arm_adi_v5.h' only to get
the definition of 'struct adiv5_ap', but doesn't need the struct
content.

Reducing the cross dependencies speeds-up the compile time during
code development by avoiding re-compiling file.

Relax the dependency by locally declaring 'struct adiv5_ap' in
'armv7m.h' and remove the include of 'arm_adi_v5.h'.
Fix the other files that have now lost the includes file that
'arm_adi_v5.h' depends from.

Change-Id: Ic0d40b17db6045fa43f348bda83eaf211a6b347d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6468
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-09-25 12:59:12 +00:00
Tim Newsome 3858878d38
Properly cache s0/s1 (#645)
* WIP on register caching.

So we don't have to save/restore S0 all the time.

Change-Id: I9d83a24dbd92a325213f2b25eebc9ede9dca2868

* Seems to work for RV32.

Change-Id: Ide620faa5dfef4f39c3146e094787ea28d041327

* Use caching everywhere.

Change-Id: I0de249437589e1f49811f34c12726528c045c74f

* Getting closer...

Change-Id: I532455f1e416723b79eecc7d33ec6407ccb8e33c

* All spike tests pass again.

Running all tests now takes 2m54s compared to 3m0s. That's probably not
the thing to measure, since the goal is to improve interactive
performance, while the tests do all kinds of other stuff (like sleep,
and start spike, etc.).

Change-Id: Ic7d944454a64b2baf6e6028debb4a1ba896834d8

* Save s0/s1 during examine.

Change-Id: I4795180e3b04d01433a11d4a0ccb38c35074cc44
Signed-off-by: Tim Newsome <tim@sifive.com>

* Check flush registers result.

Change-Id: I8350c4198cb41881e1143816698aed677a312111
Signed-off-by: Tim Newsome <tim@sifive.com>

* Fix upstream style regression.

Change-Id: I4cc7034151ba62fa51aea77e44b0cad9b9b97876
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-09-23 15:07:38 -07:00
Antonio Borneo 73c6416799 target: do not cast NULL in assignment
NULL is defined as 'void *'.
There is no need to cast NULL while assigning it to a pointer.

Change-Id: Ibaf18e5d47329707ec9c1c184cd4bba2e8e702ff
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6540
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
2021-09-18 15:26:14 +00:00
Antonio Borneo 79800db98a openocd: remove last NULL comparisons
The NULL pointers preceded by cast where not detected by the
scripting tools looking for NULL pointer comparison.

Remove them and, while there, further simplify the code and apply
the other coding style rules.

Change-Id: Ia7406122e07ef56ef311579ab0ee7ddb22c8e4b5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6539
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-09-18 15:22:30 +00:00
Tim Newsome f78f9a90a6 In SMP config, replicate watchpoints on each core
This works well with gdb on RISC-V, since hardware breakpoints are
per-core and gdb thinks that targets are really processes on a machine.

Are there targets where this is a bad idea? Should the target definition
specify whether this behavior is desired or not?

Change-Id: Ia32be2707b04347fd8bf2ca6fbb2b0ceaad3704a
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6528
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-09-11 12:08:38 +00:00
Yasushi SHOJI 3ae2583b48 target: cortex_m: Fix a typo VECTRESET
According to ARM Cortex M3 technical reference manual, it's
"VECTRESET" instead of "VECRESET".

Change-Id: Iff5534beac2b313cee6da3252d76d4d44a61eeed
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6508
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-09-04 07:24:50 +00:00
Tim Newsome dc1e8484e2 Fix build.
Change-Id: I1ef6978fed7de7fa0b82f07d5bcb2f0264fda037
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-08-31 10:27:39 -07:00
Tim Newsome a1146731a8 Merge branch 'master' into from_upstream
Conflicts:
	src/flash/nor/fespi.c
	src/jtag/drivers/ftdi.c
	src/rtos/FreeRTOS.c
	src/rtos/hwthread.c
	src/rtos/rtos.c
	src/rtos/rtos.h
	src/rtos/rtos_ecos_stackings.c
	src/rtos/rtos_embkernel_stackings.c
	src/rtos/rtos_standard_stackings.c
	src/rtos/rtos_standard_stackings.h
	src/rtos/rtos_ucos_iii_stackings.c
	src/server/gdb_server.c
	src/server/server.c
	src/target/riscv/riscv-013.c
	src/target/target.c
	src/target/target.h

Change-Id: If0924a3e799260c33fae5feb85975b1273b45a0f
2021-08-30 15:03:59 -07:00
root 3f1c15d2a7 target/adi_v5_jtag: Add support for 8-bit IR JTAG-DP
As per Arm Debug Interface Architecture Specification (ADIv5.0 to
ADIv5.2), B3.3.1, the JTAG-DP as an IR length of 4 or 8 bits
depending on the ARM implementation. The current code
only support 4-bit and this patch extends the support to 8-bit IR.
Not tested back yet on a 4-bit target.

Change-Id: Ie4f875dc336caf014c6cfced57574b54d0970623
Signed-off-by: Antoine C. <acalando@free.fr>
Reviewed-on: https://review.openocd.org/c/openocd/+/6285
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-08-22 20:27:59 +00:00
Antonio Borneo 347b88a3e1 cortex_a: use the ap number specified at target create
Current implementation ignores the flag '-ap-num' provided to
command 'target create' and searches for the first AP of APB type.

If specified, use the ap number.

Change-Id: If1ac12345220d14a4a60515efe46dc2a2eac079a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6413
Tested-by: jenkins
2021-08-22 20:26:38 +00:00
Antonio Borneo 7a61a006de jep106: use packed jedec manufacturer code
JEP106 encodes JEDEC-assigned manufacture code as:
a) a sequence of zero or more escape codes 0x7f;
b) an odd-parity bit of the next 7 bits;
c) 7 bits.

The same code is often represented as a single value composed by
the logical OR between:
- the number of escape codes in a), shifted left by 7 positions;
- the 7 bits in c).
This is the preferred packed representation used by this change.

Currently there are only two uses of JEP106 in openocd to get the
manufacturer name:
- to decode the JTAG IDCODE of each TAP, where the JEP106 code is
  already packed as in the preferred representation above in bits
  IDCODE[11:1];
- to decode the ARM CoreSight PIDR register, where the JEP106 code
  is split in 3 parts:
  = PIDR3[3:0], corresponding to bits [10:7] of the packed code;
  = PIDR2[2:0], corresponding to bits [6:4] of the packed code;
  = PIDR1[7:4], corresponding to bits [3:0] of the packed code.

Wrap the existing JEP106 decode function in a simpler API using
the packed code.
Simplify the callers by skipping the bit unpacking.
Change the manufacturer code in CoreSight table dap_partnums[] to
match the packed representation, by removing the always-one bit 7
erroneously taken from PIDR bit JEDEC and included in the former
table.

Change-Id: I63eb4da9e6801fab25e330f1f6b792d2fd619493
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6418
Tested-by: jenkins
2021-08-22 20:26:06 +00:00
Antonio Borneo 66175577e1 arm_adi_v5: update coresight class names
Update the list of ARM coresight classes wrt to latest ARM
documentation.
Use c99 array designator to easily track changes in future.
Add a comment for the entry "OptimoDE DESS". It was added in 2009
by David Brownell, but Google cannot find any reference other than
this line in openocd code its associated commit. It should not be
an issue keeping it as is.

Change-Id: Ia3b646131ee68ca5263095c3a0aeaf75c004b324
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6431
Tested-by: jenkins
2021-08-22 20:25:19 +00:00
Antonio Borneo 6f28ac8fde cortex_m: fix command 'step address'
The command 'step' accepts an optional parameter 'address' to run
the step-by-step execution from an address different from current
program counter.
When OpenOCD sets the new program counter value in the register
cache, it doesn't flag it as dirty. The following call to function
armv7m_restore_context() does not propagate the new value of the
program counter to the target. This cause the target to continue
from the old program counter value, ignoring the user's request.

It is hard to notice the issue if the target is halted in an idle
loop! In fact the default mode to operate step-by-step is to set a
breakpoint to the following instruction and resume execution. In
the idle loop the CPU will pass through the breakpoint whatever
the resume address is. User will find the target halting at the
instruction following 'address' which is consistent with the
expected behaviour of command 'step address'.

To verify the issue on an STM32F4, use a dummy code in SRAM:
	halt
	mww 0x20000000 0xbf00bf00
	mww 0x20000004 0xbf00bf00
	mww 0x20000008 0xe7fcbf00
	arm disassemble 0x20000000 6
	        0x20000000  bf00    nop
	        0x20000002  bf00    nop
	        0x20000004  bf00    nop
	   +--> 0x20000006  bf00    nop
	   |    0x20000008  bf00    nop
	   +-<- 0x2000000a  e7fc    b   #0x20000006
	resume 0x20000006
	halt
	step 0x20000000
the target doesn't halt because it is in the loop from 0x20000006
to 0x2000000a. The 'step 0x20000000' did not changed the program
counter so the temporary breakpoint at 0x20000002 is never hit.
Then:
	halt
	step 0x20000008
		target halted ...
		... pc: 0x2000000a
gives the feeling that only the instruction at 0x20000008 has been
executed, but actually the whole loop has been executed from the
place 'halt' stopped the execution till the breakpoint at the
instruction following 0x20000008.

Flag the program counter cached value as 'valid' and 'dirty' to
force armv7m_restore_context() to update the target's register.

Change-Id: I49bd8bb95b2f5429ec38ed016f2ad706618ae68a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6434
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-08-22 20:23:09 +00:00
Antonio Borneo 3ce70962d1 arm_adi_v5: use macro DP_APSEL_MAX in place of magic number
Commit 11019a824d ("adi_v5: enforce check on AP number value")
introduces the macro DP_APSEL_MAX and use it in place of hardcoded
magic numbers for the upper limit of AP selection value.

Fix one more place where the macro should be used.

Change-Id: I6c57f72405c69bbb40924221309d95dfeb5f7540
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 11019a824d ("adi_v5: enforce check on AP number value")
Reviewed-on: http://openocd.zylin.com/6415
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-08-14 13:31:06 +01:00
Antonio Borneo 020e46d186 arm_adi_v5: fix access to 64-bit MEM-AP
Commit ac22cdc573 ("target/adiv5: Large Physical Address
Extension") reads the register MEM_AP_REG_CFG and keeps it in a
new field of struct adiv5_ap. The test on LE bit (Large Extension)
is used to identify if mem_ap addresses are 32 or 64 bits.
But the register MEM_AP_REG_CFG is only read during mem_ap_init(),
that is called only when the AP is used as a target debug AP or if
a target mem_ap is attached to that AP.

The openocd commands '<dapname> baseaddr', '<dapname> info' and
'dap info' can be executed on AP that has not been associated yet
to a target, thus executed without any knowledge of MEM_AP_REG_CFG
value. The initialization to ADI_BAD_CFG causes openocd to always
use 32 bit mode on un-associated APs.

Verify if MEM_AP_REG_CFG has not been read and eventually read it.
In case of 32 bits mode AP, MEM_AP_REG_BASE64 is defined as 'RES0'
(reserved, but readable); the code can queue both the read of
MEM_AP_REG_CFG and MEM_AP_REG_BASE64, before knowing if the former
is required. This speeds-up the operation.
Rename ADI_BAD_CFG as MEM_AP_REG_CFG_INVALID.

Change-Id: If3bbd792b56a483022c37ccc2ce82b5ba5c36caa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: ac22cdc573 ("target/adiv5: Large Physical Address Extension")
Reviewed-on: http://openocd.zylin.com/6412
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2021-08-14 13:30:35 +01:00
Antonio Borneo 2f97856c5b arm_adi_v5: fix signed offset in Class 0x1 ROM tables
In both arm ADIv5 and ADIv6 documentation, for both Class 0x1 and
Class 0x9 ROM tables, the offset field from ROM tables is supposed
to be a signed value: "Negative values of OFFSET are permitted,
using two’s complement."

The commit ac22cdc573 ("target/adiv5: Large Physical Address
Extension") extends to 64 bits the addresses while managing the ROM
tables. The offset is read as unsigned and in the former 32 bits
implementation the wrap-around was hiding the need for converting
the offset to signed. The new implementation requires the proper
cast to the offset.

On a STM32F411, without this fix the ROM table dump is incorrectly
reporting addresses out of the 32 bit bus range:
MEM-AP BASE 0xe00ff003
	Valid ROM table present
		Component base address 0xe00ff000
		Peripheral ID 0x00000a0411
		Designer is 0x0a0, STMicroelectronics
		Part is 0x411, Unrecognized
		Component class is 0x1, ROM table
		MEMTYPE system memory present on bus
	ROMTABLE[0x0] = 0xfff0f003
		Component base address 0x1e000e000
		                       ^^^^^^^^^^^

Cast the offset before adding it to the base address of the ROM
table.

Change-Id: I8d31fd2b3d657286cb96f8e22fb00842baa728f7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: ac22cdc573 ("target/adiv5: Large Physical Address Extension")
Reviewed-on: http://openocd.zylin.com/6410
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
2021-08-14 13:30:14 +01:00
Antonio Borneo 08a0cfdeeb helper/align.h: use it
Use the new helper to make the code more readable.

Change-Id: I11b2a79dbc6f93f6cfde382bcc00dd7ff710d908
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6375
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-08-14 13:29:50 +01:00
Tim Newsome db16b3dc5b Call poll at a fixed interval.
The existing implementation blocks in select() for a fixed amount of
time. This change tracks when the next event (likely poll()) wants to be
run, and uses a shorter timeout in select() if necessary.

Also track all these timeouts using milliseconds as returned by
timeval_ms() instead of `struct timeval` to simplify the code.

This feature is helpful if poll() wants to do something like sample PCs
or memory values for basically the entire time that otherwise OpenOCD
would be hung in select(). See
https://github.com/riscv/riscv-openocd/pull/541 for an example of that.
The RISC-V code using this change will be upstreamed some day, too.

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I67104a7cf69ed07c8399c14aa55963fc5116a67d
Reviewed-on: http://openocd.zylin.com/6363
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-31 10:08:47 +01:00
Florian Fainelli ae6de2f93d arm_adi_v5: Added Cortex-A76 identifiers
Add identifiers of the Cortex-A76 ROM and debug unit.

Change-Id: Ieef0d990189d3c0502e8d530874dc9cbca4417d8
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-on: http://openocd.zylin.com/6358
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-24 10:39:35 +01:00
Florian Fainelli e2ef1c9090 arm_adi_v5: Provide Brahma-B53 identifiers
The Broadcom Brahma-B53 CPUs contains a number of custom ROM table
entries for its PMU, Debug unit, and a couple of ROM tables.

Change-Id: I1f21f07ed296579c374f24e781325789bf4ebf51
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-on: http://openocd.zylin.com/6368
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-24 10:39:12 +01:00
Antonio Borneo c0c7d6fe8b openocd: fix Yoda conditions with checkpatch
The new checkpatch can automatically fix the code, but this
feature is still error prone and not complete.

Patch generated automatically through the new checkpatch with
flags "--types CONSTANT_COMPARISON --fix-inplace".

Some Yoda condition is detected by checkpatch but not fixed; it
will be fixed manually in a following commit.

Change-Id: Ifaaa1159e63dbd1db6aa3c017125df9874fa9703
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6355
Tested-by: jenkins
2021-07-24 10:38:31 +01:00
Antonio Borneo 54e699b260 openocd: manually remove NULL comparisons
For the remaining NULL comparisons, remove then manually.

While there, make more readable a loop, by moving the assigment
out of the loop condition.

Change-Id: I44193aaa95813156a3a79c16b80e1ad333dc1eaf
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6353
Tested-by: jenkins
2021-07-24 10:38:19 +01:00
Antonio Borneo 0a1f904707 openocd: remove NULL comparisons with checkpatch [2/2]
Patch generated automatically through a modified checkpatch that
detects the patterns
	if (NULL == symbol)
	if (NULL != symbol)
and through flags "--types COMPARISON_TO_NULL --fix-inplace".

The unmodified checkpatch detects this pattern as Yoda condition,
but it's odd fixing it as Yoda condition and then again as NULL
comparison. This triggered the modification to the script.

Change-Id: I5fe984a85e9c4fc799f049211797aef891ebce18
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6352
Tested-by: jenkins
2021-07-24 10:38:11 +01:00
Antonio Borneo 3917823187 openocd: remove NULL comparisons with checkpatch [1/2]
Patch generated automatically through the new checkpatch with
flags "--types COMPARISON_TO_NULL --fix-inplace".
This only fixes the comparisons
	if (symbol == NULL)
	if (symbol != NULL)
The case of NULL on the left side of the comparison is not tested.

Some automatic fix is incorrect and has been massaged by hands:
	-	if (*psig == NULL)
	+	if (*!psig)
changed as
	+	if (!*psig)

Change-Id: If4a1e2b4e547e223532e8e3d9da89bf9cb382ce6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6351
Tested-by: jenkins
2021-07-24 10:38:00 +01:00
Antonio Borneo 08ee7bb982 openocd: fix simple cases of NULL comparison
There are more than 1000 NULL comparisons to be aligned to the
coding style.
For recurrent NULL comparison it's preferable using trivial
scripts in order to minimize the review effort.

Patch generated automatically with the command:
	sed -i PATTERN $(find src/ -type f)
where PATTERN is in the list:
	's/(\([a-z][a-z0-9_]*\) == NULL)/(!\1)/g'
	's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) == NULL)/(!\1)/g'
	's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) == NULL)/(!\1)/g'

	's/(\([a-z][a-z0-9_]*\) != NULL)/(\1)/g'
	's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) != NULL)/(\1)/g'
	's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) != NULL)/(\1)/g'

	's/(NULL == \([a-z][a-z0-9_]*\))/(!\1)/g'
	's/(NULL == \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(!\1)/g'
	's/(NULL == \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(!\1)/g'

	's/(NULL != \([a-z][a-z0-9_]*\))/(\1)/g'
	's/(NULL != \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(\1)/g'
	's/(NULL != \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(\1)/g'

Change-Id: Ida103e325d6d0600fb69c0b7a1557ee969db4417
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6350
Tested-by: jenkins
2021-07-24 10:37:49 +01:00
Antonio Borneo b159f5cded target: rename CamelCase symbols
No major cross dependencies, mostly changes internal to each
file/function.

Change-Id: I7cc87458a341bae29a4f772b0af5d97b4bfc2da3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6343
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
2021-07-24 10:37:25 +01:00
Tim Newsome 90d1d490c1
Add support for hypervisor bits. (#631)
Expose them in the virtual priv register, and set them on mcontrol6
hardware triggers. I have no good way to test this right now, so it's
all untested. But this change doesn't break anything, at least.

Change-Id: I0343a6169a0b2b1f0cc0abf687c6bdc560d99b1b
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-07-23 14:42:05 -07:00
Tim Newsome 2ae1e88178
Fix clobbering s2 in read_memory_progbuf(increment=0) (#634)
Fixes #632.

Change-Id: Ic884823faf67749f1ac8fbd91fe67ff9ebdd8fd0
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-07-23 12:01:41 -07:00
Antonio Borneo 20b29b7767 openocd: manually fix Yoda conditions
Fix the remaining Yoda conditions, detected by checkpatch but not
fixed automatically.

While there, apply minor style changes.

Change-Id: I6e1978b89c4d56a20aceaeb2b52968eb6384432a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6356
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Xiang W <wxjstz@126.com>
2021-07-20 14:55:43 +01:00
Antonio Borneo 28c24a5c41 openocd: fix simple cases of Yoda condition
There are ~900 Yoda conditions to be aligned to the coding style.
For recurrent Yoda conditions it's preferable using a trivial
script in order to minimize the review effort.
E.g. comparison of uppercase macro/enum with lowercase variable:
	- ...(ERROR_OK == retval)...
	+ ...(retval == ERROR_OK)...

Patch generated automatically with the command:
	sed -i \
	's/(\([A-Z][A-Z0-9_]*\) \([=!]=\) \([a-z][a-z0-9_]*\))/(\3 \2 \1)/g' \
	$(find src/ -type f)

While there, remove the braces {} around a single statement block
to prevent warning from checkpatch.

Change-Id: If585b0a4b4578879c87b2dd74d9e0025e275ec6b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6354
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>
2021-07-20 14:55:24 +01:00
Antonio Borneo 71aba329a3 target/nds32: use lowercase for C variables
Convert to lowercase the name of arrays.
Convert to macro two uppercase const variables.

Change-Id: Ic6f5cad38722dfdf78d662ff4893e94482ab423d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6348
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Xiang W <wxjstz@126.com>
2021-07-20 14:54:27 +01:00
Antonio Borneo 43750e8d53 target/nds32: rename CamelCase symbols
Change-Id: I4619eb47cd051f52e60a3fdbc49aaf71e13a81e2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6342
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Xiang W <wxjstz@126.com>
2021-07-20 14:53:12 +01:00
Antonio Borneo cbaccc5c3e target/mips: rename CamelCase symbols
No major cross dependencies, mostly changes internal to each
file/function.

Change-Id: Iec58f7fe1d65f621ae0c841b5e25ef222885792b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6341
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Xiang W <wxjstz@126.com>
2021-07-20 14:53:03 +01:00
Antonio Borneo 12d6f6d804 target/arm: opcodes: rename CamelCase symbols and uppercase variables
No major cross dependencies, mostly changes internal to each
file/function.

Change-Id: I1325560ef0350517d86d4927cb17ceaae81b75d2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6340
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Xiang W <wxjstz@126.com>
2021-07-20 14:52:49 +01:00
Antonio Borneo c0ea4295df target/cortex_m: rename CamelCase symbol
Change-Id: I67d803e15ba9fd08f2b31361fb3604275e483605
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6339
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Xiang W <wxjstz@126.com>
2021-07-20 14:52:38 +01:00
Antonio Borneo 67cb50e26a target/arm: rename CamelCase symbols
No major cross dependencies, mostly changes internal to each
file/function.

Change-Id: I3f0879f0f33c6badc36a0dc60229323978a7e280
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6338
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Xiang W <wxjstz@126.com>
2021-07-20 14:52:25 +01:00
Jan Matyas 65c9653cc7 target: add support for 64bit data in mem2array and array2mem
- Added support for reading and writing 64-bit data items
  using TCL commands "mem2array" and "array2mem". Until now,
  data items only up to 32 bits were supportd.

- Cleaned up functions target_array2mem() and
  target_mem2array(), especially data types of variables
  and variable declarations (scope).

Change-Id: Ia0ba427804f8fd8d7568f12714ab36984d6d5e24
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: http://openocd.zylin.com/6286
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-10 15:31:38 +01:00
Daniel Goehring c819444e96 target: add 64-bit address array command support
Add 64-bit address support to the target mem2array and array2mem commands

Change-Id: Ibdcc076ca5581f4fd87e92318aab33907e22d6ce
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: http://openocd.zylin.com/6246
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-10 15:31:11 +01:00
Jan Matyas 6f439e2032 target/semihosting: Fix of close(): Never close standard streams
This change fixes behavior of the SEMIHOSTING_SYS_CLOSE operation.
It ensures that OpenOCD's own stdin/stdout/stderr streams are never
closed, not even if the target requests it via semihosting.

Change-Id: Ia85af5963d1a3516284fd834f7197369a8fb268c
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: http://openocd.zylin.com/6291
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-10 15:29:58 +01:00
Jan Matyas 4487270ea4 target/semihosting: Capture errno in SEMIHOSTING_SYS_ISTTY
Capture the value of "errno" in semihosting isatty() call,
as is done in other syscalls.

Change-Id: I41b72175635f06c000536f583e3efa30fb57379e
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: http://openocd.zylin.com/6292
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-10 15:28:42 +01:00
Marc Schink 81b59e876c target/cortex_a: Replace printf() with LOG_DEBUG()
Change-Id: I38fa8e21959b398033741cbd779b632d572c7ce4
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6336
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-02 17:14:21 +01:00
Marc Schink b1a8082f59 target/aarch64: Replace printf() with LOG_DEBUG()
Change-Id: If32bc320c48259dec4b81d457b848e972bcda784
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6335
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-02 17:14:17 +01:00
Marc Schink aad4f1c1f5 target/mips64: Replace printf() with LOG_ERROR()
Change-Id: I73956dc3485a23b761aecd869cc37d657c393bde
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6334
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-02 17:14:11 +01:00
Jan Matyas c8e643fd9f target: check return value of register get/set callbacks
- In "reg" TCL command handler, the return value of register get()
  and set() callbacks must be checked, in the same manner as it is
  done in e.g. gdb_set_register_packet() or gdb_get_register_packet().

- Minor cleanup of variable definitions in the "reg" command
  handler.

Change-Id: I8c57e7c087fe31d1abffa3c4d1f79a01af4c9c97
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: http://openocd.zylin.com/6293
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-02 17:13:06 +01:00
Marc Schink 66334354b7 target/stm8: Remove unused member 'stm8_common'
Change-Id: Ie8b59a82142bfdf2ee9395d38b1bedc27de728b8
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6325
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-02 17:12:38 +01:00
Kevin Burke ac22cdc573 target/adiv5: Large Physical Address Extension
Provides ARM LPAE support to allow 64-bit TAR setting
on MEM AP accesses.

Tested on a 4-core ARM ARES Processor system using an
AXI Access Port.

Change-Id: I88f7a0a57a6abb58665032929194a41dd8729f6b
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: http://openocd.zylin.com/5576
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-02 17:12:11 +01:00
Tim Newsome 5edbbb4827 Merge branch 'master' into from_upstream
Conflicts:
	src/flash/nor/nrf5.c
	src/flash/nor/xcf.c
	src/jtag/drivers/remote_bitbang.c
	src/rtos/FreeRTOS.c
	src/rtos/zephyr.c
	src/target/cortex_a.c
	src/target/cortex_a.h
	src/target/cortex_m.c
	src/target/riscv/riscv.c

Change-Id: I80b0a33b40c06c229d20fe34e04d6322da83326d
2021-06-30 14:56:44 -07:00
Marc Schink 0478a93ed5 target/breakpoints: Remove dead code and cleanup
Change-Id: I8027178b6e771753775514a8641a050c6e63a1d5
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6321
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-26 14:42:01 +01:00
Antonio Borneo 2044df3dac armv7m: replace flag 'stlink' with 'is_hla_target'
The HLA target is not anymore used by ST-Link only, but required
by Nu-Link and TI-ICDI too.

Rename the flag 'stlink' as 'is_hla_target'.

Change-Id: Id2ee2c0a1e8bf1f1e899f7a560140c34eefeeee5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6206
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-06-26 14:41:15 +01:00
Marc Schink 873e5c3976 target/dsp563xx: Use bool data type for 'hardware_breakpoints_cleared'
Change-Id: Ic18973d3e90d74c211b48627bdaac4cf3357b682
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6324
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-26 14:40:34 +01:00
Marc Schink 56b72b33cf target/dsp563xx: Handle return values
This fixes 'dead assignment' bugs identified by the clang static analyzer.

Change-Id: I140ed55f0043e06a533f45f50a36887614585b04
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6323
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-26 14:40:18 +01:00
Jesse Sheridan 0ef5144c32 target/riscv: Implement get_gdb_arch()
Change-Id: I5f4ab5243104df41031950682f688f2448a09b17
Signed-off-by: Jesse Sheridan <jesse.sheridan@gmail.com>
Reviewed-on: http://openocd.zylin.com/6322
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-26 14:38:59 +01:00
Marc Schink da770c4fbb Use boolean argument for register_get_by_name()
Change-Id: Ie913630c6ab3b600532d8e375e2fc11ca202cf5e
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6295
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-18 23:14:27 +01:00
Marc Schink 4bb1d8b45e target/register: Minor code cleanup
Change-Id: Ie02a112c0339ae5d3b3763483e493370b487be98
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6294
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-18 23:14:09 +01:00
Tarek BOCHKATI 1185760729 cortex_m: enhance core and arch detection
Rework core detection by adding cortex_m_partno enum to detect all CPUs
using the same method.

Instead of checking the core PARTNO then assign the arch, use the stored
information within cortex_m parts[] with the flags inside which can help
simplifying a bit the cortex_m_examine code.

This change fixes:
 - the Cortex-M1 detection as ARMv6-M Core (was managed as ARMv7-M)
 - the displayed CPU name for Cortex-M0+ (was displayed Cortex-M0)

Change-Id: I40b6e03f7cf3664c85e297adfc25323196dfe90b
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6233
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-18 23:13:18 +01:00
Tarek BOCHKATI f69adafb3d target/arm: optimize architecture flags
In target/arm.h the struct arm do contain 3 flags to retain architecture
version for some tweaks.
The proposal is to have only one enumerated flag 'arch' for the same purpose.

Change-Id: Ia5d5accfed8158ca21eb54af2fdea8e36f0266ae
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6229
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-18 23:12:54 +01:00
Marc Schink 3e8ca67d1f target: Rename 'linked_BRP' to 'linked_brp'
Change-Id: I9dd67ac3e8cd5dd9cdeffce56020b387a8f298fa
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6316
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-18 23:10:57 +01:00
Tarek BOCHKATI cb5d9e0098 armv4_5: do not read/write non-existent registers
Change-Id: I4a0c401a325e57ba5d4d93d83b7e6b71a4d0865e
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6064
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-13 19:59:16 +01:00
Tarek BOCHKATI 708284a1ac arm_dpm: do not read/write non-existent registers
Change-Id: I6a991899bb178ee0c6b41870a45d0a9439d9dc1e
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6063
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2021-06-13 19:59:04 +01:00
Tarek BOCHKATI 21e1ebdc8e armv8_dpm: do not read/write non-existent registers
Change-Id: I0f3fffa8cf1746569f6acce0233e9544d3862f51
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6062
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-13 19:58:51 +01:00
Marc Schink 076b4d708e target/cortex_a: Use bool data type
Change-Id: Ieea3dc05809263aa0eba5125d52fef3fe77e9c5a
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6289
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-13 19:57:25 +01:00
Tim Newsome f4950b7c5d
From upstream (#620)
* cortex_m: use unsigned int for FPB and DWT quantifiers

related quantifiers are:
 - fp_num_lit
 - fp_num_code
 - dwt_num_comp
 - dwt_comp_available

Change-Id: I07dec2d4aa21bc0e580be0d9fd0a6809f876c2a8
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6185
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* telnet: allow hiding selected commands during auto-completion

We have TCL procedure and commands that we do not want to show in
the list of auto-completion. E.g. TCL wrappers for deprecated
commands, internal procedures that are not supposed to be exposed
to user, or even commands that the user decides to hide.

Create a TCL procedure to be called by telnet auto-complete code
in place of the hard-coded TCL command. The procedure will run the
same command and will filter-out the unwanted command names.

Initialize the list of commands to be filtered-out with the name
of the TCL procedure above, as it is considered as internal.

Change-Id: I2d83bbf8194502368c589c85cccb617e69128c69
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6194
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* telnet/auto-complete: hide deprecated and internal commands

For both:
- TCL proc that redirect deprecated commands to the new commands,
- TCL proc used internally and not supposed to be exposed to user,
add their name to the list of commands that should be hide by the
telnet auto-complete.

Change-Id: I05237c6a79334b7d2b151dfb129fb57b2f40bba6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6195
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* startup.tcl: prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Modify the script startup.tcl compiled-in OpenOCD binary to comply
with the new jimtcl.

Change-Id: I520dcafacadaa289a815035f93f250447ca66ea0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6158
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.

Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines

%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
 #!/usr/bin/perl -Wpi

 my $re_sym = qr{[a-z_][a-z0-9_]*}i;
 my $re_var = qr{(?:\$|\$::)$re_sym};
 my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
 my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
 my $re_op = qr{<<|>>|[+\-*/&|]};
 my $re_expr = qr{(
     (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
     \s*$re_op\s*
     (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
 )}x;

 # [expr [dict get $regsC100 SYM] + HEXNUM]
 s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;

 # [ expr (EXPR) ]
 # [ expr EXPR ]
 # note: $re_expr captures '$3'
 s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
 s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---

Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* tcl: [2/3] prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Enclose within double quote the argument of 'expr' when there is
the need to concatenate strings.

Change-Id: Ic0ea990ed37337a7e6c3a99670583685b570b8b1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6160
Tested-by: jenkins

* tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Fix manually the remaining lines that don't match simple patterns
and would require dedicated boring scripting.
Remove the 'expr' command where appropriate.

Change-Id: Ia75210c8447f88d38515addab4a836af9103096d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6161
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target/stm8: Make 'stm8_command_handlers' static

Change-Id: I5237a8f2a1ecba9383672e37bd56f8ccd17598b6
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6200
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/riscv: Change 'authdata_read' output

Use a constant output length and remove the line break to make the
authentication data easier to parse.

Change-Id: Iebbf1f171947ef89b0f360a2cb286a4ea15c6ba5
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6199
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>

* Enable adapter "Bus Pirate" by default.

The Bus Pirate is now listed in the "OpenOCD configuration summary" too.

Change-Id: Ieb7bf9134af456ebe9803f3108a243204fb2a62d
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/5637
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* coding-style: additional style for C code

To improve readability and to push more uniform code style.

Prefer 'if (false) {...}' for unused code so it get checked by the
compiler.
Define preferred indentation for 'switch' statement.
Require balanced brackets in 'if/else'.
Report the max line length.
Report the formatting strings for stdint/inttypes types.
Report the type 'target_addr_t'.
Prefer 'unsigned int' to 'unsigned'.

Change-Id: I0192a4ed298f6c6c432764fdd156cffd4b13fc89
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6203
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Marc Schink <dev@zapb.de>

* Add IPDBG JtagHost functionality to OpenOCD

IPDBG are utilities to debug IP-cores. It uses JTAG for
transport to/from the FPGA. The different UIs use TCP/IP
as transport. The JtagHost makes the bridge between these
two.

Comparable to the bridge between GDB and the in-circuit-
debugging-unit of a micro controller.

Change-Id: Ib1bc10dcbd4ea426e492bb7b2d85c1ed1b7a8d5a
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: http://openocd.zylin.com/5938
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* flash/nor/xcf: Do not use 'Yoda conditions'

Change-Id: I17308f5237338ce468e5b86289a0634429deaaa9
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6201
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* cortex_m: add armv8m special registers

Change-Id: I1942f375a5f4282ad1fe4a2ff3b8f3cbc64d8f7f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6016
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* rtos: Add support for Zephyr RTOS

With this patch, the Zephyr[1] RTOS is supported by OpenOCD.

As usual with support for other RTOSes, Zephyr must be compiled with
the DEBUG_THREAD_INFO option. This will generate some symbols
with information needed in order to build the list of threads.

The current implementation is limited to Zephyr running on ARM
Cortex-M processors. This is the only ARM variant supported by Zephyr
at the moment and is used on most of the officially supported boards.

[1] https://www.zephyrproject.org/

Change-Id: I22afdbec91562f3a22cf5b88cd4ea3a7a59ba0b4
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Signed-off-by: Daniel Glöckner <dg@emlix.com>
Reviewed-on: http://openocd.zylin.com/4988
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/armv7m.h: [style] replace tab with space between variable type and name

Change-Id: I9740c25857295a2a655d3046322a3f23f0ee7f78
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6230
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* server: gdb_server: Add colon for target extended-remote

Both GDB commands "target remote" and "target extended-remote" require
to have ":" right before port number.

e.g.
    (gdb) target extended-remote :3333

Add ":" to the warning message so that users can copy & past it.

Change-Id: Id6d8ec1e4dfd3c12cb7f3b314064f2c35fa7ab55
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: http://openocd.zylin.com/6237
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* jimtcl: restrict memory leak workaround on Linux only

The workaround for jimtcl 0.80 in commit 36ae487ed0 ("jimtcl:
add temporary workaround for memory leak in jimtcl 0.80") issues a
compile time error on macOS:
	../src/helper/command.c:157:22: error: aliases are not
	supported on darwin
	__attribute__((weak, alias("workaround_createcommand")));
The OS is x86_64-apple-darwin19.6.0 and the compiler used is
x86_64-apple-darwin13.4.0-clang.

Restrict the workaround on Linux host only. The fix for 'expr'
syntax change is already merged and the workaround will be dropped
soon.

Change-Id: I925109a9c57c05f8c95b70bc7d6604eb1172cd79
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Adam Jeliński <ajelinski@users.sourceforge.net>
Fixes: 36ae487ed0 ("jimtcl: add temporary workaround for memory leak in jimtcl 0.80")
Fixes: https://sourceforge.net/p/openocd/tickets/304/
Reviewed-on: http://openocd.zylin.com/6241
Tested-by: jenkins

* target/armv7m: fix static analyzer warning

Despite of assert(is_packed) clang static analyser complains on use
of the uninitialized offset variable.

Cross compiling with latest x86_64-w64-mingw32-gcc hits warnings
	src/target/armv7m.c: In function ‘armv7m_read_core_reg’:
	src/target/armv7m.c:337:54: error: ‘reg32_id’ may be used
	    uninitialized in this function [-Werror=maybe-uninitialized]

It happens because mingw32 defines assert() without the attribute
"noreturn", whatever NDEBUG is defined or not.

Replace assert(is_packed) by if (is_packed) conditional and call
assert(false) in the else branch.

Change-Id: Id3c7dcccb65106e28be200b9a4d2b642f4d31019
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6256
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>

* cmsis_dap: fix build on macOS

Compile fails with error:
	src/jtag/drivers/cmsis_dap.c:683:28: error: format specifies type
	    'unsigned char' but the argument has type 'int' [-Werror,-Wformat]
	                         " received 0x%" PRIx8, CMD_DAP_TFER, resp[0]);
	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~

Fix the format specifier.

Change-Id: I0a5a1a35452d634019989d14d849501fb8a7e93a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6255
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* cortex_m: do not perform soft_reset_halt on targets without VECTRESET

Change-Id: Ib3df457e0afe4e342c82ad1af25e03aad6979d87
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6209
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* cortex_m: fix VECTRESET detection for ARMv6-M cores

VECTRESET check should be done after verifying if the core is an ARMv6-M core,
and not before that.

Fixes: 2dc9c1df81 ("cortex_m: [FIX] ARMv8-M does not support VECTRESET")
Change-Id: I8306affd332b3a35cea69bba39ef24ca71244273
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6232
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/arm_dpm: rename 'wp_pc' as 'wp_addr'

The field 'wp_pc' was originally introduced in commit 55eeea7fce
("ARMv7a/Cortex-A8: report watchpoint trigger insn") in end 2009
to contain the address of the instruction which triggered a
watchpoint. Later on with commit 651b861d5d ("target/aarch64:
Add watchpoint support") it has been reused in to hold directly
the memory address that triggered a watchpoint.

Rename 'wp_pc' as 'wp_addr' and change its doxygen description.
While there, fix the format string to print the field.

Change-Id: I2e5ced1497e4a6fb6b38f91e881807512e8d8c47
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6204
Tested-by: jenkins
Reviewed-by: Liming Sun <limings@nvidia.com>

* target/aarch64: fix watchpoint management

The early documentation for armv8a report the debug register WFAR
as containing the address of the instruction that triggered the
watchpoint. More recent documentation report the register EDWAR as
containing the data memory address that triggered the watchpoint.

The name of macros CPUV8_DBG_WFAR0 and CPUV8_DBG_WFAR1 is not
correct as they point to the debug register EDWAR, so reading such
register returns directly the data memory address that triggered
the watchpoint. The code incorrectly passes this address value to
the function armv8_dpm_report_wfar(); this function is supposed to
adjust the PC value, decrementing it to remove the effects of the
CPU pipeline. This pipeline offset, that has no meaning on the
value in EDWAR, caused commit 651b861d5d ("target/aarch64: Add
watchpoint support") to add back the offset while comparing the
address with the watchpoint enabled.

The upper 32 bits of EDWAR are not valid in aarch32 mode and have
to be ignored.

Rename CPUV8_DBG_WFAR0/1 as CPUV8_DBG_EDWAR0/1.
Remove the function armv8_dpm_report_wfar().
Remove the offset while searching the matching watchpoint.
Ignore the upper 32 bits of EDWAR in aarch32 mode.
Fix a comment and the LOG text.

Change-Id: I7cbdbeb766fa18e31cc72be098ca2bc501877ed1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6205
Tested-by: jenkins
Reviewed-by: Liming Sun <limings@nvidia.com>

* flash/stm32l4x: add missing break statement

this is not a bug fix, this for loop will issue only one match
adding the break will save unnecessary more loops.

Change-Id: Ic1484ea8cdea1b284eb570f9e3e7818e07daf5cd
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6248
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins

* github/action: create a permanent 'latest' release

this commit extends the existing snapshot action to create a release named
'latest' with the built binaries for windows.

this 'latest' release will be updated after every push to github.

Change-Id: I75a64c598169241743add3ac9aa7a0337fbab7f2
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6127
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* tcl/rp2040: remove empty line at end of file

Change-Id: I212a96b77282b151a8ecbd46a6436e2bbbda4161
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6221
Tested-by: jenkins

* tcl: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.
While there, fix one indentation.

Change-Id: I72369ed26f363bacd760b40b8c83dd95e89d28a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6214
Tested-by: jenkins

* flash: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: Ia5f134c91beb483fd865df9e4877e0ec3e789478
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6215
Tested-by: jenkins

* jtag: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: I101c76a638805d77c1ff356cf0f027552389e5d3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6216
Tested-by: jenkins

* target: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: I548581247db72e683249749d1b8725035530b06e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6217
Tested-by: jenkins

* openocd: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: I7b4cae1798ff5ea048fcbc671a397af763fdc605
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6218
Tested-by: jenkins

* Document the buspirate interface driver.

Change-Id: Iaff13fc5187041a840f4f00eb6b4ee52880cf47e
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/6231
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Warn on undefined preprocessor symbols

Preprocessor directives like "#if SYMBOL" silently replace undefined or
misspelt symbols with 0, which makes configuration bugs hard to spot.
Compiler flag "-Wundef" prevents such errors.

Change-Id: I91b7ba2db02ef0c3c452d334601c53aebda4660e
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/6238
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Remove compatibility macros m4_ifblank and m4_ifnblank

They are at least since Autoconf 2.67 present,
and we are requiring version 2.69.

Change-Id: I41b33d4ebe02198f03cdddcc4a3c1beedd993d78
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/6239
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* configure.ac: use a separate folder for Autoconf-generated files

Autoconf generates several files in root folder of the project.
Keep the root folder cleaner by specifying subfolder 'build-aux'.
Align .gitignore accordingly.

Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Change-Id: Ied87faba495d9eeb8f98e78c2e2b7e7e596febfb
Reviewed-on: http://openocd.zylin.com/6236
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* helper/command: silent debug msg on command register/unregister

Commit e216186fab ("helper/command: register full-name commands
in jim") and commit a7d68878e4 ("helper/command: unregister
commands through their full-name") introduce a LOG_DEBUG() message
each for command registration and unregistration.
The messages above are quite noisy and pollute the log when
debug_level is 3 or higher.
They can be useful to debug the command registration logic, but
for the other debug activities on OpenOCD are just noisy.
Already commit a03ac1ba30 ("helper/command: disable logging of
registered commands [RFC]") was merged to silent the first case
that is now back with additional logs.

Silent both log messages.
Use 'if (false)' to silent them, making easy to re-enable it when
or if someone needs it.

Change-Id: Id8a067e60e822d4ecbddcb036d081298f7e6181f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6220
Tested-by: jenkins

* mem_ap: fix target arch_info type

The target mem_ap appears as an ARM target, thus it allows the
execution of ARM specific commands causing the crash of OpenOCD.
E.g. 'arm mrc ...' can be executed and segfaults.

Replace the incorrect ARM magic number with a dedicated one.
While there, remove the 'struct arm', that is now holding only the
mem_ap's dap, and replace it with a pointer to the dap.

Change-Id: I881332d3fdf8d8f8271b8711607737b052a5699b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6213
Tested-by: jenkins

* riscv: drop unused variable

The array newly_halted[] is assigned but its value is never used.
Drop it!

Change-Id: I678812a31c45a3ec03716e3eee6a30b8e8947926
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6257
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Tim Newsome <tim@sifive.com>

* riscv: replace macro DIM() with ARRAY_SIZE()

OpenOCD already defines the macro ARRAY_SIZE, while riscv code
uses a local macro DIM.

Prefer using the macro ARRAY_SIZE() instead of DIM().
Not all the riscv code has been upstreamed, yes; this patch only
covers the code already upstreamed.

Change-Id: I89a58a6d91916d85c53ba5e4091b558271f8d618
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6258
Reviewed-by: Xiang W <wxjstz@126.com>
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>

* target/zynqmp : Add AXI AP access port

The Xilinx Zynq UltraScale+ SoC have an "AXI-AP" access port for direct memory accesses without halting CPUs.

Change-Id: I6303331c217795657575de4759444938e775dee1
Signed-off-by: Olivier DANET <odanet@caramail.com>
Reviewed-on: http://openocd.zylin.com/6263
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* drivers/versaloon: use ARRAY_SIZE()

Replace the custom macro dimof() with the OpenOCD macro
ARRAY_SIZE().

Change-Id: I2fe638444f6c16f2a78c1fd558b21550f76282d6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6259
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>

* openocd: use macro ARRAY_SIZE()

There are still few cases where the macro ARRAY_SIZE() should be
used in place of custom code.

Use ARRAY_SIZE() whenever possible.

Change-Id: Iba0127a02357bc704fe639e08562a4f9aa7011df
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6260
Reviewed-by: Xiang W <wxjstz@126.com>
Tested-by: jenkins

* rtos: use ARRAY_SIZE() and simplify rtos_type.create()

Use the existing macro ARRAY_SIZE().
Rewrite the functions rtos_type.create() to simplify the logic.

Change-Id: I8833354767045d1642801d26944c9087a77add00
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6261
Tested-by: jenkins

* tcl: remove remaining deprecated commands

There are still few adapter_khz, ftdi_location, jtag_nsrst_delay
and xds110_serial strolling around ...

Change-Id: I3e8503dcc3875e3c92e6536f3d455a5e448d51ff
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6270
Tested-by: jenkins

* help text: remove trailing space

Some help text end with a useless space character.
Remove it.

Change-Id: I397e1194fac8042f0fab694222f925f906716de3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6222
Tested-by: jenkins

* help: fix line size in 'usage' output

The implementation of command 'usage' is broken while checking the
line limit of 76 chars per line (e.g. 'usage load_image') and the
line wrapping is not correct. The same broken code is used for the
first output line of command 'help' too.

When call command_help_show_wrap(), include the command's name in
the string so the whole text would be wrapped.

Change-Id: Idece01ce54994db7e851d8522435ff764b11f3ac
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6223
Tested-by: jenkins

* LICENSES: Add the MIT license

Add the full text of the MIT license to the kernel tree.  It was copied
directly from:

  https://spdx.org/licenses/MIT.html#licenseText

Add the required tags for reference and tooling.

Change-Id: I94a5dea5ced6421809ea2a3448f8dda19a93f5c9
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6219
Tested-by: jenkins

* stlink: add comment of firmware version for each flag bit

Change-Id: I7f7c7b9c9cfd88125f82662ed864a2c0715140b1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6211
Tested-by: jenkins

* stlink: reorder the flag macro by firmware release

The corresponding bit for each macro is changed, but this is not
relevant in the code.

Change-Id: I7039464f5a3d55d008208f44952aadeb815bd5a3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6212
Tested-by: jenkins

* tcl/board: Add ST NUCLEO-8S208RB

Change-Id: I384c6ad9b4cbabbc004160677f600d8c4bd3eb71
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6268
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/arm_adi_v5: Fix clear sticky overrun flag during replay of commands

When a WAIT occurs the commands after the WAIT are replayed and the
STICKYORUN is cleared. However if another WAIT occurs during the
command replay, the command itself is resent but the STICKYORUN bit
shall also be cleared. If this is not done, the MEM-AP hangs.

Change-Id: I14e8340cd5d8f58f4de31509da96cfa2ecb630d1
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Reviewed-on: http://openocd.zylin.com/6278
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* target/cortex_a: add support for watchpoints

The current implementation of OpenOCD does not support watchpoints for
cortex_a architecture. So, I replaced the add_watchpoint and
remove_watchpoint with the specific implementation for the
cortex a and using the breakpoint implementation and the arm
documentation [1] as reference. In particular, I have made the
following changes:

* added the following functions

- cortex_a_add_watchpoint
  This wrapper function check whether there are any watchpoint
  available on the target device by calling cortex_a_set_watchpoint.

- cortex_a_set_watchpoint
  This function is responsible for settings the watchpoint register
  pair. In particular, it sets the WVR and the WCR registers with
  the cortex_a_dap command.

- cortex_a_remove_watchpoint
  This wrapper function the selected watchpoint on the target device
  by calling cortex_a_unset_watchpoint.

- cortex_a_unset_watchpoint
  This function sets both the WVR and the WCR registers to zero, thus
  unsetting the watchpoint.

[1]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BCGDHIEJ.html

Change-Id: I86611dab474cb84836662af572b17636dc68e282
Signed-off-by: Chengyu Zheng <chengyu.zheng@polimi.it>
Reviewed-on: http://openocd.zylin.com/3913
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins

* target/cortex_a: fix number of watchpoints

Decrement the available watchpoints only when succeed setting it.
Initialize the available watchpoint with the correct value.

Change-Id: I0f93b347300b8ebedbcd9e718d4ba32b26cf6846
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6196
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* target/cortex_a: add support for watchpoint length of 1, 2 and 4 bytes

Use byte address select for 1 and 2 bytes length.
Use normal mode for 4 bytes length.

Change-Id: I28d182f25145d0635de64d0361d456f1ad96640e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6197
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* target/cortex_a: fix memory leak on watchpoints

The memory allocated to hold the watchpoints is not freed at
OpenOCD exit.

Free the watchpoint memory at OpenOCD exit.

Change-Id: I518c9ce0dc901cde2913d752e3154734f878b854
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6210
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* helper/jim-nvp: comply with coding style [1/2]

The helper jim-nvp does not comply with OpenOCD coding style due
to typedef of struct and CamelCase symbol names.
While it's trivial fixing the helper and all its current use in
the code, changing these APIs will potentially break a number of
patches pending in gerrit. Gerrit will not trigger any alert, but
the code will generate compile error after the merge.

Add the compile flag "-Wno-error=deprecated-declarations" to keep
as warning (not as error) the use of "deprecated" functions and
types.
Rename all the CamelCase symbols is lowercase and provide struct
prototypes in place of the typedef.
Add a DEPRECATED section to 'jim-nvp.h' where the old CamelCase
symbols and the old typedef are re-declared with compile attribute
'deprecated'.

With this change OpenOCD compiles, but generates warnings.
The remaining changes allover OpenOCD code will be fixed in a
separate patch for easier review.

The patches merged later that still use the old deprecated API
will compile with warnings. This will permit to identify and fix
these cases.

Change-Id: I786385d0f662dbb1be5be313ae42623156d68ce5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6183
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>

* helper/jim-nvp: comply with coding style [2/2]

With the API fixed to comply with OpenOCD coding style, fix all
the references in the code.

Patch generated automatically with the script below.
The list is in reverse order to replace a common prefix after the
replacement of the symbols with the same prefix.

%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
(cat << EOF
Jim_SetResult_NvpUnknown         jim_set_result_nvp_unknown
Jim_Nvp_value2name_simple        jim_nvp_value2name_simple
Jim_Nvp_value2name_obj           jim_nvp_value2name_obj
Jim_Nvp_value2name               jim_nvp_value2name
Jim_Nvp_name2value_simple        jim_nvp_name2value_simple
Jim_Nvp_name2value_obj_nocase    jim_nvp_name2value_obj_nocase
Jim_Nvp_name2value_obj           jim_nvp_name2value_obj
Jim_Nvp_name2value_nocase_simple jim_nvp_name2value_nocase_simple
Jim_Nvp_name2value_nocase        jim_nvp_name2value_nocase
Jim_Nvp_name2value               jim_nvp_name2value
Jim_Nvp                        struct jim_nvp
Jim_GetOpt_Wide                  jim_getopt_wide
Jim_GetOpt_String                jim_getopt_string
Jim_GetOpt_Setup                 jim_getopt_setup
Jim_GetOpt_Obj                   jim_getopt_obj
Jim_GetOpt_NvpUnknown            jim_getopt_nvp_unknown
Jim_GetOpt_Nvp                   jim_getopt_nvp
Jim_GetOpt_Enum                  jim_getopt_enum
Jim_GetOpt_Double                jim_getopt_double
Jim_GetOpt_Debug                 jim_getopt_debug
Jim_GetOptInfo                 struct jim_getopt_info
Jim_GetNvp                       jim_get_nvp
Jim_Debug_ArgvString             jim_debug_argv_string
EOF
) | while read a b; do
    sed -i "s/$a/$b/g" $(find src -type f ! -name jim-nvp.\? )
done
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---

Change-Id: I10a12bd64bb8b17575fd9150482c989c92b298a2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6184
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins

* server/telnet: fix autocomplete for jimtcl commands

Current autocomplete filters-out some command reported by "info
commands". One of the filter rule concerns the command's private
data.
Every command registered by OpenOCD has its 'struct command' as
private data.

By ignoring commands without private data, we loose several TCL
commands registered by jimtcl, e.g. 'foreach', 'llength'.

By assuming that every command with non-NULL private data has
'struct command' as private data, we risk at best to access
inconsistent data, at worst to trigger a segmentation fault.

Export the already available functions:
- to check if a command has been registered by OpenOCD and
- to get the private data.
While there, rename jimcmd_is_ocd_command() as
jimcmd_is_oocd_command().
Don't filter-out jimtcl commands with no private data.
Check the private data only on OpenOCD commands.

Change-Id: Ib5bf8d2bc5c12440c0cfae438f637c38724a79b7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6282
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* helper/list.h: align file to Linux v5.12

Main improvement is in the doxygen comments.
Minimize the delta with kernel file.
Skip the functions hlist_unhashed_lockless() and
__list_del_clearprev() that are relevant only in kernel.
Remove gcc extension "omitted conditional operand".

Change-Id: I2e9ddb54cfe2fa5f7cf18f44726acd144e1f98b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6276
Reviewed-by: <rdiezmail-openocd@yahoo.de>
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>

* contrib: add an example of using list.h

Change-Id: Ic3d399d7ad2e4d10677cf78d64968040941b74e5
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6280
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>

* helper/list.h: add mention to the example in contrib

Without such reference, it could be difficult to find the example.

Change-Id: Ia9ffb06bc1a45446c2c7b53197ab3400e1d8a9e9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6281
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>

* tcl/target/stm32f4x: fix hardcoded chip name

Fixes: c945d6e616 ("tcl/target: start using the new TPIU/SWO support")
Change-Id: I4543c9a204f7b4b3b14e6eabc5042653106aff0e
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6277
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins

* Makefile: add special target .DELETE_ON_ERROR

The special .DELETE_ON_ERROR deletes the target file on recipe error.
Otherwise, an incomplete output file may be considered up to date
the next time around. .DELETE_ON_ERROR provides reasonable
protection at virtually no cost.

Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Change-Id: I67dca47ae5ddf3786993c87b9991b3046a85f00b
Reviewed-on: http://openocd.zylin.com/6235
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* gdb_server: Log both incoming and outgoing GDB packets

- Made sure that also outgoing GDB packets are logged,
  not only the incoming ones.

- Improved the treatment of non-printable characters
  in the packets to make it more robust.

Prior to this change:

- Outgoing packets were not printed unless OpenOCD was
  re-compiled with _DEBUG_GDB_IO_.
- Non-prinable characters were only treated in incoming
  'X' packets.

After this change:

- Both incoming and outgoing GDB packets are logged
  on debug_level >= 3, so that both directions of the
  GDB channel are visible.
- Non-printable characters are checked for in every packet
  so that hey do not interfere with the terminal.

Change-Id: I0613e57ae5059b3279b0abcb71276cf5719a8699
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: http://openocd.zylin.com/6269
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/renesas_rz_g2: Introduce tcl config file for RZ/G2 devices

Initial support for Renesas RZ/G2 MPU family

Change-Id: I5ca74cddfd0c105a5307de56c3ade7084f9c28d2
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Reviewed-on: http://openocd.zylin.com/6250
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* drivers/jlink: Remove trailing dots

This makes the messages consistent with most of the rest of
the OpenOCD output.

Change-Id: I915a01187e7fc317e02483ac0bbd39ec077d6321
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6274
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target: Use 'bool' for 'reset_halt'

Change-Id: I974a6360ea7467067511541ac212f2e9d3de7895
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6262
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* cmsis_dap: add support for swo commands

Replaced mixed snake_case_CamelCase with snake_case.
Define variables at first-use location.

CMSIS-DAP SWO specification:

    https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__swo__gr.html

Change-Id: Ieba79b16efd445143f964b614673d041aae74f92
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Reviewed-on: http://openocd.zylin.com/5820
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Add target_data_bits().

This is used to compute memory block read alignment, and specifically
allows 64-bit targets to ensure that memory block reads are only
requested on 64-bit boundaries.

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: Idb1a27b9fc02c46245556bb0f3d6d94b368c4817
Reviewed-on: http://openocd.zylin.com/6249
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Avoid non-standard conditionals with omitted operands.

Fixes bug #257.

Change-Id: I05fc6468306d46399e769098e031e7e588798afc
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/6271
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/startup.tcl: Do not use 'Yoda conditions'

Change-Id: I5e1bbaf032659dda1b365ef4ec6ea4a635d921ce
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6284
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Fix build.

Change-Id: I4f2667db91f84f07af354691aac5d4c9e3aea3fa
Signed-off-by: Tim Newsome <tim@sifive.com>

Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Co-authored-by: Antonio Borneo <borneo.antonio@gmail.com>
Co-authored-by: Marc Schink <dev@zapb.de>
Co-authored-by: R. Diez <rdiezmail-openocd@yahoo.de>
Co-authored-by: Daniel Anselmi <danselmi@gmx.ch>
Co-authored-by: Evgeniy Didin <didin@synopsys.com>
Co-authored-by: Yasushi SHOJI <yashi@spacecubics.com>
Co-authored-by: Tomas Vanek <vanekt@fbl.cz>
Co-authored-by: Olivier DANET <odanet@caramail.com>
Co-authored-by: Thomas Gleixner <tglx@linutronix.de>
Co-authored-by: micbis <michele.bisogno.ct@renesas.com>
Co-authored-by: Chengyu Zheng <chengyu.zheng@polimi.it>
Co-authored-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Co-authored-by: Jan Matyas <matyas@codasip.com>
Co-authored-by: Adrian Negreanu <adrian.negreanu@nxp.com>
2021-06-11 13:01:55 -07:00
Tim Newsome ab0a2a38a3
Call keep_alive() more often. (#616)
When it doesn't do anything (most of the time) it has negligible
performance impact. With slower remote bitbang, and multiple spike
instances being tested in a single chain, things are sufficiently slow
that if a computer is busy then this is required to pass
riscv-tests/debug.

Change-Id: I8816efedaa0cc3b25734ba8fdc979ee4502284a1
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-06-08 10:54:26 -07:00
Jan Matyas 0211e6bf4c
Print dcsr.cause always (#617)
Minor change/debug print: Made sure that dcsr.cause is printed
into the log always.
2021-06-07 12:40:58 -07:00
Marc Schink bb81ec8bf0 target/startup.tcl: Do not use 'Yoda conditions'
Change-Id: I5e1bbaf032659dda1b365ef4ec6ea4a635d921ce
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6284
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-04 17:46:48 +01:00
R. Diez 6a49b1ce23 Avoid non-standard conditionals with omitted operands.
Fixes bug #257.

Change-Id: I05fc6468306d46399e769098e031e7e588798afc
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/6271
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-04 17:46:24 +01:00
Tim Newsome 358ab3483d Add target_data_bits().
This is used to compute memory block read alignment, and specifically
allows 64-bit targets to ensure that memory block reads are only
requested on 64-bit boundaries.

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: Idb1a27b9fc02c46245556bb0f3d6d94b368c4817
Reviewed-on: http://openocd.zylin.com/6249
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-04 17:45:58 +01:00
Marc Schink c4dd883c9a target: Use 'bool' for 'reset_halt'
Change-Id: I974a6360ea7467067511541ac212f2e9d3de7895
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6262
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-06-04 17:44:42 +01:00
Antonio Borneo 9e7b31479b helper/jim-nvp: comply with coding style [2/2]
With the API fixed to comply with OpenOCD coding style, fix all
the references in the code.

Patch generated automatically with the script below.
The list is in reverse order to replace a common prefix after the
replacement of the symbols with the same prefix.

%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
(cat << EOF
Jim_SetResult_NvpUnknown         jim_set_result_nvp_unknown
Jim_Nvp_value2name_simple        jim_nvp_value2name_simple
Jim_Nvp_value2name_obj           jim_nvp_value2name_obj
Jim_Nvp_value2name               jim_nvp_value2name
Jim_Nvp_name2value_simple        jim_nvp_name2value_simple
Jim_Nvp_name2value_obj_nocase    jim_nvp_name2value_obj_nocase
Jim_Nvp_name2value_obj           jim_nvp_name2value_obj
Jim_Nvp_name2value_nocase_simple jim_nvp_name2value_nocase_simple
Jim_Nvp_name2value_nocase        jim_nvp_name2value_nocase
Jim_Nvp_name2value               jim_nvp_name2value
Jim_Nvp                        struct jim_nvp
Jim_GetOpt_Wide                  jim_getopt_wide
Jim_GetOpt_String                jim_getopt_string
Jim_GetOpt_Setup                 jim_getopt_setup
Jim_GetOpt_Obj                   jim_getopt_obj
Jim_GetOpt_NvpUnknown            jim_getopt_nvp_unknown
Jim_GetOpt_Nvp                   jim_getopt_nvp
Jim_GetOpt_Enum                  jim_getopt_enum
Jim_GetOpt_Double                jim_getopt_double
Jim_GetOpt_Debug                 jim_getopt_debug
Jim_GetOptInfo                 struct jim_getopt_info
Jim_GetNvp                       jim_get_nvp
Jim_Debug_ArgvString             jim_debug_argv_string
EOF
) | while read a b; do
    sed -i "s/$a/$b/g" $(find src -type f ! -name jim-nvp.\? )
done
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---

Change-Id: I10a12bd64bb8b17575fd9150482c989c92b298a2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6184
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
2021-06-04 17:40:48 +01:00
Antonio Borneo 3bd26ebb59 target/cortex_a: fix memory leak on watchpoints
The memory allocated to hold the watchpoints is not freed at
OpenOCD exit.

Free the watchpoint memory at OpenOCD exit.

Change-Id: I518c9ce0dc901cde2913d752e3154734f878b854
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6210
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2021-06-03 23:27:20 +01:00
Antonio Borneo 0c64bb2583 target/cortex_a: add support for watchpoint length of 1, 2 and 4 bytes
Use byte address select for 1 and 2 bytes length.
Use normal mode for 4 bytes length.

Change-Id: I28d182f25145d0635de64d0361d456f1ad96640e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6197
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2021-06-03 23:27:13 +01:00
Antonio Borneo ffaef5809c target/cortex_a: fix number of watchpoints
Decrement the available watchpoints only when succeed setting it.
Initialize the available watchpoint with the correct value.

Change-Id: I0f93b347300b8ebedbcd9e718d4ba32b26cf6846
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6196
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2021-06-03 23:26:56 +01:00
Chengyu Zheng 1fb736f6c5 target/cortex_a: add support for watchpoints
The current implementation of OpenOCD does not support watchpoints for
cortex_a architecture. So, I replaced the add_watchpoint and
remove_watchpoint with the specific implementation for the
cortex a and using the breakpoint implementation and the arm
documentation [1] as reference. In particular, I have made the
following changes:

* added the following functions

- cortex_a_add_watchpoint
  This wrapper function check whether there are any watchpoint
  available on the target device by calling cortex_a_set_watchpoint.

- cortex_a_set_watchpoint
  This function is responsible for settings the watchpoint register
  pair. In particular, it sets the WVR and the WCR registers with
  the cortex_a_dap command.

- cortex_a_remove_watchpoint
  This wrapper function the selected watchpoint on the target device
  by calling cortex_a_unset_watchpoint.

- cortex_a_unset_watchpoint
  This function sets both the WVR and the WCR registers to zero, thus
  unsetting the watchpoint.

[1]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BCGDHIEJ.html

Change-Id: I86611dab474cb84836662af572b17636dc68e282
Signed-off-by: Chengyu Zheng <chengyu.zheng@polimi.it>
Reviewed-on: http://openocd.zylin.com/3913
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
2021-06-03 23:26:35 +01:00
micbis b40dc09dd9 target/arm_adi_v5: Fix clear sticky overrun flag during replay of commands
When a WAIT occurs the commands after the WAIT are replayed and the
STICKYORUN is cleared. However if another WAIT occurs during the
command replay, the command itself is resent but the STICKYORUN bit
shall also be cleared. If this is not done, the MEM-AP hangs.

Change-Id: I14e8340cd5d8f58f4de31509da96cfa2ecb630d1
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Reviewed-on: http://openocd.zylin.com/6278
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2021-05-31 20:56:33 +01:00
Antonio Borneo a40cbd85e0 help text: remove trailing space
Some help text end with a useless space character.
Remove it.

Change-Id: I397e1194fac8042f0fab694222f925f906716de3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6222
Tested-by: jenkins
2021-05-29 21:34:55 +01:00
Xiang W 3249d41559
Refactor opcodes.h (#613)
Simplify the code and prevent some field of the instruction from overflowing

Change-Id: I0acade05ad351d0e1918be4b75702b1637aa02c9
Signed-off-by: Xiang W <wxjstz@126.com>
2021-05-28 13:27:22 -07:00
Antonio Borneo 036de3b482 riscv: replace macro DIM() with ARRAY_SIZE()
OpenOCD already defines the macro ARRAY_SIZE, while riscv code
uses a local macro DIM.

Prefer using the macro ARRAY_SIZE() instead of DIM().
Not all the riscv code has been upstreamed, yes; this patch only
covers the code already upstreamed.

Change-Id: I89a58a6d91916d85c53ba5e4091b558271f8d618
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6258
Reviewed-by: Xiang W <wxjstz@126.com>
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
2021-05-22 10:11:41 +01:00
Antonio Borneo 8d207b5d2e riscv: drop unused variable
The array newly_halted[] is assigned but its value is never used.
Drop it!

Change-Id: I678812a31c45a3ec03716e3eee6a30b8e8947926
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6257
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
2021-05-22 10:11:36 +01:00
Antonio Borneo 2fe2cafe20 mem_ap: fix target arch_info type
The target mem_ap appears as an ARM target, thus it allows the
execution of ARM specific commands causing the crash of OpenOCD.
E.g. 'arm mrc ...' can be executed and segfaults.

Replace the incorrect ARM magic number with a dedicated one.
While there, remove the 'struct arm', that is now holding only the
mem_ap's dap, and replace it with a pointer to the dap.

Change-Id: I881332d3fdf8d8f8271b8711607737b052a5699b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6213
Tested-by: jenkins
2021-05-22 10:11:10 +01:00
Antonio Borneo f1bc46c78a target: fix some minor typo
Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: I548581247db72e683249749d1b8725035530b06e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6217
Tested-by: jenkins
2021-05-22 10:06:45 +01:00
Antonio Borneo 15dd48119a target/aarch64: fix watchpoint management
The early documentation for armv8a report the debug register WFAR
as containing the address of the instruction that triggered the
watchpoint. More recent documentation report the register EDWAR as
containing the data memory address that triggered the watchpoint.

The name of macros CPUV8_DBG_WFAR0 and CPUV8_DBG_WFAR1 is not
correct as they point to the debug register EDWAR, so reading such
register returns directly the data memory address that triggered
the watchpoint. The code incorrectly passes this address value to
the function armv8_dpm_report_wfar(); this function is supposed to
adjust the PC value, decrementing it to remove the effects of the
CPU pipeline. This pipeline offset, that has no meaning on the
value in EDWAR, caused commit 651b861d5d ("target/aarch64: Add
watchpoint support") to add back the offset while comparing the
address with the watchpoint enabled.

The upper 32 bits of EDWAR are not valid in aarch32 mode and have
to be ignored.

Rename CPUV8_DBG_WFAR0/1 as CPUV8_DBG_EDWAR0/1.
Remove the function armv8_dpm_report_wfar().
Remove the offset while searching the matching watchpoint.
Ignore the upper 32 bits of EDWAR in aarch32 mode.
Fix a comment and the LOG text.

Change-Id: I7cbdbeb766fa18e31cc72be098ca2bc501877ed1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6205
Tested-by: jenkins
Reviewed-by: Liming Sun <limings@nvidia.com>
2021-05-22 10:04:20 +01:00
Antonio Borneo 510df38407 target/arm_dpm: rename 'wp_pc' as 'wp_addr'
The field 'wp_pc' was originally introduced in commit 55eeea7fce
("ARMv7a/Cortex-A8: report watchpoint trigger insn") in end 2009
to contain the address of the instruction which triggered a
watchpoint. Later on with commit 651b861d5d ("target/aarch64:
Add watchpoint support") it has been reused in to hold directly
the memory address that triggered a watchpoint.

Rename 'wp_pc' as 'wp_addr' and change its doxygen description.
While there, fix the format string to print the field.

Change-Id: I2e5ced1497e4a6fb6b38f91e881807512e8d8c47
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6204
Tested-by: jenkins
Reviewed-by: Liming Sun <limings@nvidia.com>
2021-05-22 10:04:12 +01:00
Tarek BOCHKATI 936cff887a cortex_m: fix VECTRESET detection for ARMv6-M cores
VECTRESET check should be done after verifying if the core is an ARMv6-M core,
and not before that.

Fixes: 2dc9c1df81 ("cortex_m: [FIX] ARMv8-M does not support VECTRESET")
Change-Id: I8306affd332b3a35cea69bba39ef24ca71244273
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6232
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-20 20:56:48 +01:00
Tarek BOCHKATI 3a85fd52b6 cortex_m: do not perform soft_reset_halt on targets without VECTRESET
Change-Id: Ib3df457e0afe4e342c82ad1af25e03aad6979d87
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6209
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-05-20 20:54:35 +01:00
wxjstz b36d176721
remove needless function declaration from src/target/riscv/program.h (#608)
Signed-off-by: Xiang W <wxjstz@126.com>
2021-05-20 11:55:47 -07:00
Tim Newsome 19f7b5c43c
Add keepalive for vector register access. (#611)
(And whatever else does a lot of register writes.)

Change-Id: I86a1a784fb7b9430aa470dbb39a495b89f56d8c9
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-05-20 11:50:34 -07:00
Tomas Vanek d7558e2ed6 target/armv7m: fix static analyzer warning
Despite of assert(is_packed) clang static analyser complains on use
of the uninitialized offset variable.

Cross compiling with latest x86_64-w64-mingw32-gcc hits warnings
	src/target/armv7m.c: In function ‘armv7m_read_core_reg’:
	src/target/armv7m.c:337:54: error: ‘reg32_id’ may be used
	    uninitialized in this function [-Werror=maybe-uninitialized]

It happens because mingw32 defines assert() without the attribute
"noreturn", whatever NDEBUG is defined or not.

Replace assert(is_packed) by if (is_packed) conditional and call
assert(false) in the else branch.

Change-Id: Id3c7dcccb65106e28be200b9a4d2b642f4d31019
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6256
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>
2021-05-18 09:03:28 +01:00
Tim Newsome 10957400c0
Merge pull request #605 from riscv/rtos_riscv
Remove enable_rtos_riscv command.
2021-05-17 12:08:19 -07:00
Antonio Borneo 9bdd1daec3 riscv: replace macro DIM() with ARRAY_SIZE()
OpenOCD already defines the macro ARRAY_SIZE, while riscv code
uses a local macro DIM.

Prefer using the macro ARRAY_SIZE() instead of DIM().
Not all the riscv code has been upstreamed, yes; this patch only
covers the code already upstreamed.

Change-Id: I89a58a6d91916d85c53ba5e4091b558271f8d618
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-16 13:57:11 +02:00
Antonio Borneo 6f5259db05 riscv: prefer ARRAY_SIZE() to DIM()
OpenOCD already defines the macro ARRAY_SIZE, while riscv code
uses a local macro DIM.

Prefer using the macro ARRAY_SIZE() instead of DIM().
Not all the riscv code has been upstreamed, yes; this patch only
covers the code not upstreamed.

Change-Id: Ie3e411280f76bc798f1d51c2574cfec148ee0d0d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-16 13:53:10 +02:00
Antonio Borneo 0944e12232 riscv: drop unused variable
The array newly_halted[] is assigned but its value is never used.
Drop it!

Change-Id: I678812a31c45a3ec03716e3eee6a30b8e8947926
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-16 13:40:55 +02:00
Tarek BOCHKATI d624da96a9 target/armv7m.h: [style] replace tab with space between variable type and name
Change-Id: I9740c25857295a2a655d3046322a3f23f0ee7f78
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6230
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-15 20:56:10 +01:00
Tim Newsome f31c130286 Remote enable_rtos_riscv command.
I'd missed this when that functionality was removed.

Change-Id: If5b697d9dbac517a077d9c1826c747fc95b19f1f
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-05-14 16:32:30 -07:00
Tim Newsome 8fcc19d70b Keep alive when accessing registers.
With the bitbang performance decrease and talking to slower targets
(daisy chain spike) we more often don't meet the expected keepalive time
for gdb. This addresses the cases I ran into.

Change-Id: Ie69c2c602c3be9c156e508fdfa6d0178f104e1d8
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-05-12 11:44:32 -07:00
Tarek BOCHKATI 5d9de1c400 cortex_m: add armv8m special registers
Change-Id: I1942f375a5f4282ad1fe4a2ff3b8f3cbc64d8f7f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6016
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-05-11 06:30:29 +01:00
Marc Schink 40dd1e5284 target/riscv: Change 'authdata_read' output
Use a constant output length and remove the line break to make the
authentication data easier to parse.

Change-Id: Iebbf1f171947ef89b0f360a2cb286a4ea15c6ba5
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6199
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
2021-05-08 09:49:52 +01:00
Marc Schink 167adaf841 target/stm8: Make 'stm8_command_handlers' static
Change-Id: I5237a8f2a1ecba9383672e37bd56f8ccd17598b6
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6200
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-08 09:49:32 +01:00
Antonio Borneo 82b6a41117 startup.tcl: prepare for jimtcl 0.81 'expr' syntax change
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Modify the script startup.tcl compiled-in OpenOCD binary to comply
with the new jimtcl.

Change-Id: I520dcafacadaa289a815035f93f250447ca66ea0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6158
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-05-08 09:48:36 +01:00
Antonio Borneo 223b79ebe2 telnet/auto-complete: hide deprecated and internal commands
For both:
- TCL proc that redirect deprecated commands to the new commands,
- TCL proc used internally and not supposed to be exposed to user,
add their name to the list of commands that should be hide by the
telnet auto-complete.

Change-Id: I05237c6a79334b7d2b151dfb129fb57b2f40bba6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6195
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-05-08 09:48:15 +01:00
Tarek BOCHKATI 8ecc2888cf cortex_m: use unsigned int for FPB and DWT quantifiers
related quantifiers are:
 - fp_num_lit
 - fp_num_code
 - dwt_num_comp
 - dwt_comp_available

Change-Id: I07dec2d4aa21bc0e580be0d9fd0a6809f876c2a8
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6185
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-05-04 23:13:20 +01:00
Tim Newsome 38eea2367c Add keep_alive() to system bus read loop.
Without it the repeat read test wasn't passing any longer. This is
because 7dd323b26d reduced the remote
bitbang performance. I've notified the mailing list about this.

Change-Id: Ie71592792202423aec89fa889b9e3d2a60a3c25f
Signed-off-by: Tim Newsome <tim@sifive.com>
2021-05-03 14:56:34 -07:00
Tim Newsome 927c4db298 Merge branch 'master' into from_upstream
I may have broken memory sampling with this merge.

Conflicts:
	doc/openocd.texi
	src/helper/command.c
	src/jtag/drivers/ftdi.c
	src/rtos/FreeRTOS.c

Change-Id: I2b7e09b2d3b244db546c5212532e6b48fb66dca4
2021-05-03 11:04:15 -07:00
Tarek BOCHKATI a115b589a7 cortex_m: implement hit_watchpoint function
this change aims to provide a better gdb debugging experience,
by making gdb understand what's really happening.

before this change when hitting a watchpoint
 - openocd reports "T05" to gdb
 - gdb displays: Program received signal SIGTRAP, Trace/breakpoint trap.

after the change
 - openocd reports "T05watch:20000000;" to gdb
 - gdb displays:
   Hardware watchpoint 1: *0x20000000

   Old value = 16000000
   New value = 170000000
   ...

Change-Id: Iac3a85eadd86663617889001dd04513a4211ced9
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6181
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-05-02 22:42:29 +01:00
Tim Newsome 87c90393fe Cleanup of config/includes.
Remove a use of AH_BOTTOM from configure.ac. This macro is used by
autoheader to add '#include' of some include file to the end of
config.h.in and then to config.h. OpenOCD can be built with a custom
config.h, so it's preferable to move these '#include' statement directly
in the C files that need them dropping this unneeded dependency.

It also causes problems when I want to use the gnulib library (which
comes with its own Makefile, and does not have the same include path as
the top-level Makefile).

So this change touches a lot of files, but is actually really simple. It
does not affect functionality at all.

Change-Id: I52c70bf15eb2edc1dd10e0fde23b2bcd4caec000
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/6171
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-01 14:35:09 +01:00
Christian Hoff 565129119f target/image: report error if ELF file contains no loadable sections
The existing code asserted in that case, which is not correct. This
would allow the user to crash OpenOCD with a bad ELF file, which is
not what we want. A proper error should be reported in that case and
OpenOCD should not crash.

Change-Id: Ied5a6a6fd4ee0fd163f3fe850d304a121ecbe33a
Signed-off-by: Christian Hoff <christian.hoff@advantest.com>
Reviewed-on: http://openocd.zylin.com/6172
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-01 13:36:28 +01:00
Florian Meister 9206bd243b target/image: allow loading of 64-bit ELF files
Change-Id: I9b88edacf5ffcc3c1caeab8c426693de0d92a695
Signed-off-by: Florian Meister <florian.meister@advantest.com>
Signed-off-by: Christian Hoff <christian.hoff@advantest.com>
Reviewed-on: http://openocd.zylin.com/5204
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Ooi, Cinly <cinly.ooi@intel.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-05-01 13:36:15 +01:00
Tarek BOCHKATI ef0da79448 cortex_m: mark FPU register as non-existent instead of playing with num_regs
Change-Id: Iac7c5bfbb95c8d9a8c6d65104d138692a44eca78
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6015
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-04-30 08:23:29 +01:00
Tomas Vanek ef0aa38c10 target/armv7m: change FPv4_SP and FPv5_SP/DP identifiers to uppercase
Change-Id: Ia421a973e5fb4767715c9f95c91745f8ca1de1da
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6177
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-04-30 08:20:54 +01:00
Tomas Vanek ab337d05f4 target/arm_adi_v5: move DP register definitions to one block
DP and MEM-AP definitions were mixed.

Change-Id: I2f691b2274c01e9090c1e5160c6903d3207e35c2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6138
Tested-by: jenkins
2021-04-25 23:08:49 +01:00
Tomas Vanek 4455469847 target/adi_v5_swd: remove double space from swd_cmd() parameters
Change-Id: I6b68868947010512c4de76e5d37142f067e27b06
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6137
Tested-by: jenkins
2021-04-25 23:08:41 +01:00
Tomas Vanek 45eff3a806 target/arm_adi_v5: add JTAG_TO_DORMANT sequence
Change-Id: Ie9e32e42a84cf88bf779e691a67c114eef1bb457
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6136
Tested-by: jenkins
2021-04-25 23:08:19 +01:00
Antonio Borneo 3cacfd86ab smp: move command deprecation to startup.tcl
Commit 246782229f ("smp: replace commands smp_on/smp_off with
"smp [on|off]"") deprecates some multi-word comments, when openocd
was unable to properly handle mixes of multi-word commands and tcl
procedures having a common initial word.
This limitation is over, so move in startup.tcl the multi-word
commands deprecation, making it easy to remove them after a grace
period.

Change-Id: Icb550d1fa7559b95692d2a1244880da6c90ec0b2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5677
Tested-by: jenkins
2021-04-25 23:03:28 +01:00
Antonio Borneo e216186fab helper/command: register full-name commands in jim
While still keeping the tree of struct command, stop registering
commands in jim by the root "word" only.

Register the full-name of the command and pass as private data the
struct command of the command itself.

Still use the tree of struct command to un-register the commands.

Some "native" commands (.jim_handler) share the same handler, then
the handler checks the command name to run the right code.
Now argv[0] returns the full-name of the command, so check the
name by looking in the struct command passed as private data.

Change-Id: I5623c61cceee8a75f5d5a551ef3fbf5a303af6be
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5671
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-04-18 15:34:10 +01:00
Antonio Borneo 41c95aa4ea helper/command: pass command prefix to command registration
Replace the "struct command *parent" parameter with a string that
contains the command prefix.
This abstracts the openocd code from the knowledge of the tree of
struct command.
This also makes unused the function command_find_in_context(), so
remove it.

Change-Id: I598d60719cfdc1811ee6f6edfff8a116f82c7ed6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5668
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-04-18 15:33:30 +01:00
Antonio Borneo 4289389937 helper/command: override target only on target prefixed cmds
In current code the current target is overridden whenever
jim_handler_data is not NULL. This happens not only with target
prefixed commands, but also with cti, dap and swo/tpiu prefixed
commands.
While this is not causing any run-time issue, by now, the
behaviour is tricky and makes the code cryptic.

Add a specific field to struct command for the target override so
the content of jim_handler_data can be restricted to command
specific data only (today only cti, dap and swo/tpiu).

Extend the API register_commands() to specify the presence of
either the command data or the override target.

The new API makes obsolete calling command_set_handler_data() to
set jim_handler_data, so remove it.

Change-Id: Icc323faf754b0546a72208f90abd9e68ff2ef52f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5667
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-04-18 15:33:23 +01:00
Antonio Borneo 7cd679a2de helper/command: get current target from dedicated API
Now that target override is uniformly implemented for all types of
commands, there is no need for target-prefixed "native" commands
(.jim_handler) to sneakily extract the overridden target from the
struct command.

Modify the commands to use the standard API get_current_target().

Change-Id: I732a09c3261e56524edd5217634fa409eb97a8c6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5666
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-04-18 15:33:15 +01:00
Antonio Borneo a510c8e23c helper/command: always pass struct command as jim private data
While registering a new command, jim accepts a pointer to command's
private data that will be accessible during the command execution.

Today openocd is not consistent and passes different private data
depending on the command, and then even overwrites it:
- "simple" commands (.handler) are registered with their own
  struct command pointer as command private data;
- "native" commands (.jim_handler) at root level are registered
  with NULL command private data;
- "native" commands (.jim_handler) not at root level are
  registered with the struct command pointer of their root command
  as command private data but, when executed, the command private
  data is overwritten by the value in field jim_handler_data taken
  from their struct command.

Uniform the usage of command private data by always set it to the
struct command pointer while registering the new commands.
Note: for multi-word commands only the root command is registered,
so command private data will be set to the struct command of the
root command. This will change later in this series when the full-
name of the command will be registered.

Don't overwrite the command private data, but let the commands that
needs jim_handler_data to get it directly through struct command.

For sake of uniformity, let function command_set_handler_data() to
set the field jim_handler_data also for "group" commands, even if
such value will not be used.

Now Jim_CmdPrivData() always returns a struct command pointer, so
wrap it in the inline function jim_to_command() to gain compile
time check on the returned type.
While there, uniform the code to use the macro Jim_CmdPrivData()
to access the command's private data pointer.

Change-Id: Idba16242ba1f6769341b4030a49cdf35a5278695
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5664
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-04-18 15:32:57 +01:00
Cheng-Shiun Tsai a9904ba22c Aarch64:Switch to EL1 from EL0 before manipulate MMU
If current core is in EL0, it cannot use 'msr sctlr_el1, x0'

Change-Id: I04e60e39e4c84f9d9de7cc87a8e438f5d2737dc3
Signed-off-by: Cheng-Shiun Tsai <cheng.shiun.tsai@gmail.com>
Reviewed-on: http://openocd.zylin.com/6051
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2021-04-18 15:32:24 +01:00
Tim Newsome 7420382a4d Merge branch 'master' into from_upstream
Conflicts:
	.github/workflows/snapshot.yml
	NEWS
	configure.ac
	contrib/loaders/checksum/riscv_crc.c
	jimtcl
	src/helper/time_support.h
	src/jtag/drivers/arm-jtag-ew.c
	src/rtos/FreeRTOS.c
	src/target/image.c
	src/target/riscv/riscv.c

Change-Id: I043624ba540d4672fc123dddb2066bcb9c6b5a05
2021-04-13 11:26:25 -07:00
Antonio Borneo 0f06d94336 mem_ap: allow GDB connections
The target mem_ap is a convenient way to access buses, memory and
peripherals behind an ARM AP.
The current implementation provides only access through OpenOCD
commands, because GDB remote protocol has to interact with a CPU
and has to operate on CPU states and registers.
Using GDB to access the memory is welcome, because GDB can resolve
the symbol's address from an ELF file and can nicely display the
content of complex struct and data types.

Extend mem_ap target with the bare minimal support for a remote
GDB connection, by emulating a fake basic ARM core. It means that
only a GDB that has support for ARM can be used (either 'aarch64',
'arm' or 'multiarch' GDB). This is not seen as a big limitation,
because the mem_ap target is mainly used on ARM based devices.

Add a minimalist register description for the fake CPU.
Fill the field 'debug_reason' as expected by GDB server.
Call the target halted event to reply to GDB halt requests.

For backward compatibility, don't open the GDB port by default. If
needed, it has to be specified at 'target create' or 'configure'
with the flag '-gdb-port'.

Change-Id: I5a1b7adb749746516f5d4ffc6193c47b70132364
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6034
Tested-by: jenkins
2021-04-11 21:34:30 +01:00
Liming Sun 651b861d5d target/aarch64: Add watchpoint support
There are some breakpoint/watchpoint related code in armv8_dpm.c,
but seems not working for aarch64. Target aarch64 has its own
breakpoint implementation in aarch64.c. This commit follows the
same logic to add watchpoint support for target aarch64.

This commit also increases the size of stop_reason[] in function
gdb_signal_reply() since the old size is too small to fit in a
64-bit address, such as ffff8000115e6980.

Change-Id: I907dc0e648130e36b434220f570c37d0e8eb5ce1
Signed-off-by: Liming Sun <lsun@mellanox.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: http://openocd.zylin.com/4761
Tested-by: jenkins
Reviewed-by: Liming Sun <limings@nvidia.com>
Reviewed-by: Kevin Burke <kevinb@os.amperecomputing.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-04-11 21:28:01 +01:00
Ernie Edgar 28724d996a
Update version check error message from 0.14 to 1.0. (#588) 2021-04-02 11:51:01 -07:00
Evgeniy Didin eca4f964b4 target/arc: refactor ARC register numbers defines
For Zephyr rtos support it is necessary to define general register
numbers for architecture. There were some already in arc.h file.
Let's define ARC registers numbers as a set instead of separate defines.

Change-Id: I63742b8608f9556c2ec9bd2661a0fd9cf88e9b74
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/6105
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-19 22:01:00 +00:00
Rene Kita 6db49eb885 build: remove warnings with gcc 11
This removes some warnings which prevent a successful build with -Werror
which is enabled by default. I'm using gcc 11, so maybe others are not
getting this warnings yet.

In src/flash/nor/numicro.c the debug messages were misleadingly indented.
In src/target/arm920t.c the array size where smaller than expected from
the receiving function.

Change-Id: I66f5c6a63beb9f9416e73b726299297476c884d8
Signed-off-by: Rene Kita <git@rkta.de>
Reviewed-on: http://openocd.zylin.com/6104
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-19 22:00:34 +00:00
Tarek BOCHKATI 84af95bb54 aarch64: handle semihosting in aarch32 state
Change-Id: I0e868d617db126a2b258e27b11979b75b5bb72f5
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5860
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-19 21:59:48 +00:00
Tim Newsome 41147e6fcd Implement CRC32 algorithm for RISC-V.
Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: Id437f78e74e3d837ff203f84c4eeb996bfad9a01
Reviewed-on: http://openocd.zylin.com/6076
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2021-03-19 21:58:17 +00:00
Christian Hoff 6c0151623c aarch64: add support for "reset halt"
Support halting the CPU directly after a reset. If halt is
requested, the CPU stops directly at the reset vector, before
any code is executed.

This functionality was implemented using the Reset Catch
debug event.

Change-Id: If90d54c088442340376f0b588ba10267ea8e7327
Signed-off-by: Christian Hoff <christian.hoff@advantest.com>
Reviewed-on: http://openocd.zylin.com/5947
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-03-19 21:57:43 +00:00
Antonio Borneo 25218e8935 jtag: remove minidriver code and minidriver-dummy
With zy1000 removed, there is no other implementation that uses
the minidriver, apart from the test/example minidriver-dummy.
While the idea of the minidriver is probably still valid (that is
to intercept jtag primitives before serialization), there is no
current use case, no guarantee it is really working, and the way
it was implemented (by macros and #if conditionals) is really hard
to maintain and test.

Let's let it rip in git history, from where it could eventually be
taken back in a more modern implementation.
The entry points of minidriver API are still in the code with the
original names.

Change-Id: I882e32cb26cf5842f9cba14e3badaf8948e3760d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6091
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-19 21:56:06 +00:00
Antonio Borneo 26a57b06cf oocd_trace: drop the code, deprecated in v0.10.0
The code for oocd_trace has been marked as deprecated in release
v0.10.0, 4 years ago.

Time to drop it!

Change-Id: I989f8345dee4ff2369bcf5e2e2ace86bbd5aa6a5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6088
Tested-by: jenkins
2021-03-19 21:55:15 +00:00
Antonio Borneo 113f949ac1 target: remove handling of target's deprecated_name
We do not have anymore any deprecated target name.
Drop the code to handle deprecated target names and the placehold
in struct target_type.

This patch is separated from the patch that drops the remaining
deprecated target names to be ready to revert this if there is any
need in the future.

Change-Id: I96fca7ffa39d8292f81e79f115ea45c4a30035d7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6087
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-19 21:55:02 +00:00
Antonio Borneo 64b486e74f target: remove target names already deprecated in v0.8.0
Some target name were marked as deprecated in release v0.7.0 and
v0.8.0, almost 7 years ago, and replaced with more 'actual' names.
We can reasonably expect that in these 7 years any user of OpenOCD
has already migrated to v0.8.0 or to some newer release, thus has
already updated any local/personal script to get rid of the
deprecated message.

Drop the target names already deprecated in v0.8.0.

Change-Id: I7c7491496db1b302b4eb1e9fc6090b58d4acf05a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6086
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-19 21:54:57 +00:00
Antonio Borneo 70ead8ff5d startup.tcl: remove commands already deprecated in v0.7.0
Some command were already marked as deprecated in release v0.7.0,
more then 7 years ago, and for some of them the depredation date
is even earlier.
We can reasonably expect that in these 7 years any user of OpenOCD
has already migrated to v0.7.0 or to some following intermediate
build, thus has already updated any local/personal script to get
rid of the deprecated message.

Drop the commands already deprecated in v0.7.0.

Change-Id: I81cdc415ab855ebf30980ef5199f9780c5d7f932
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6085
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-19 21:54:51 +00:00
Antonio Borneo cda7bc9a4c target/arm920t: remove command 'arm920t cp15i' deprecated in v0.4.0
The command 'arm920t cp15i' was marked as deprecated in release
v0.4.0, almost 11 years ago.
We can reasonably expect that in these years any user of OpenOCD
has already migrated to v0.4.0 or to some newer release, thus has
already updated any local/personal script.
There is no run-time warning about the deprecation, but it is
reported in the help and in the documentation.

Drop the command already deprecated in v0.4.0.

Change-Id: I755c4283e13e125558fcd73b15fe20498eae95ca
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6083
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-19 21:54:41 +00:00
Antonio Borneo ab0def0f38 target/arm720t: remove command 'arm720t cp15' deprecated in v0.4.0
The command 'arm720t cp15' was marked as deprecated in release
v0.4.0, almost 11 years ago.
We can reasonably expect that in these years any user of OpenOCD
has already migrated to v0.4.0 or to some newer release, thus has
already updated any local/personal script.
There is no run-time warning about the deprecation, but it is
reported in the help and in the documentation.

Drop the command already deprecated in v0.4.0.

Change-Id: I2b325d0312d96ca5e5f0f1bad13bb162b3b75c52
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6082
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-19 21:54:32 +00:00
Tarek BOCHKATI bc0c9907d6 cortex_m: avoid reading and writing non-existent registers
Change-Id: Iedc24352c8d3444372da06d00fcec9603540f950
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6059
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-03-10 21:35:31 +00:00
Antonio Borneo cb8e3fb2d9 server: revert commit 7e6556b3ca
With the removal of old tpiu code, commit 7e6556b3ca ("server:
permit the add_service function to return the created service")
http://openocd.zylin.com/5717/ can be reverted.

Fix also the new calls to add_service().

Change-Id: Ib7f2dfc6a9e829239e20313e0f121911085fdc00
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6031
Tested-by: jenkins
Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
2021-03-10 21:34:13 +00:00
Antonio Borneo dc7b32ea4a armv7m_trace: get rid of the old tpiu code
Remove all the old tpiu code and replace it with a wrapper that
uses the new commands, prints-out the new commands and informs
about the deprecation.

All the code that handles the deprecated tpiu commands is enclosed
between the comments
	/* START_DEPRECATED_TPIU */
and
	/* END_DEPRECATED_TPIU */
so will be easy to remove it in the future.

Change-Id: I70b0486770128203b923346382d9a90b8ec08439
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6030
Tested-by: jenkins
Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
2021-03-10 21:34:04 +00:00
Antonio Borneo 184724d14e arm_tpiu_swo: add support for independent TPIU and SWO
This is supposed to replace big part of armv7m_trace.[ch], since
TPIU is not only the one implemented in Cortex-M3 and M4.

Change-Id: I7588d16cbefe9cdb371c52fb0aa5cdfb48518804
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5858
Tested-by: jenkins
2021-03-10 21:33:40 +00:00
Antonio Borneo f9509c92db itm: rework itm commands before 'init'
If the command 'itm port[s]' is issued before 'init', the ITM can
not be programmed because OpenOCD cannot access the target yet.
The configuration is recorded and applied after target examine.
The current test to trigger the ITM delayed-programming is based
on the TPIU configuration. This is allowed because the only use of
ITM it so send data through TPIU.
In case of system TPIU, not belonging anymore to the target, there
is no more association between target ITM and system TPIU.

Add a flag to record the pending ITM configuration requested
before 'init' and test the flag to trigger the delayed-programming
of the ITM.

Change-Id: I101eb97a116d7925cd2ff068f3e8813fc008b08e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6029
Tested-by: jenkins
2021-03-10 21:33:09 +00:00