interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

target: fix some minor typo 

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: I548581247db72e683249749d1b8725035530b06e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6217
Tested-by: jenkins
This commit is contained in:
Antonio Borneo 2021-01-28 13:32:41 +01:00
parent 8e337052b6
commit f1bc46c78a
7 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/target/arc.c
View File

@ -1467,7 +1467,7 @@ static int arc_configure_actionpoint(struct target *target, uint32_t ap_num,
if (control_tt != AP_AC_TT_DISABLE) {
if (arc->actionpoints_num_avail < 1) {
LOG_ERROR("No free actionpoints, maximim amount is %u",
LOG_ERROR("No free actionpoints, maximum amount is %u",
arc->actionpoints_num);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}

2
src/target/arc.h
View File

@ -206,7 +206,7 @@ struct arc_common {
bool dcache_invalidated;
bool l2cache_invalidated;
/* Indicate if cach was built (for deinit function) */
/* Indicate if cache was built (for deinit function) */
bool core_aux_cache_built;
bool bcr_cache_built;
/* Closely Coupled memory(CCM) regions for performance-critical

2
src/target/arm_adi_v5.c
View File

@ -32,7 +32,7 @@
* This file implements support for the ARM Debug Interface version 5 (ADIv5)
* debugging architecture. Compared with previous versions, this includes
* a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
* transport, and focusses on memory mapped resources as defined by the
* transport, and focuses on memory mapped resources as defined by the
* CoreSight architecture.
*
* A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two

4
src/target/avr32_mem.c
View File

@ -176,7 +176,7 @@ int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info,
*/
if (addr & 3) {
/*
* mwa_read will read whole world, no nead to fiddle
* mwa_read will read whole world, no need to fiddle
* with address. It will be truncated in set_addr
*/
retval = avr32_jtag_mwa_read(jtag_info, SLAVE_HSB_UNCACHED,
@ -248,7 +248,7 @@ int avr32_jtag_write_memory8(struct avr32_jtag *jtag_info,
*/
if (addr & 3) {
/*
* mwa_read will read whole world, no nead to fiddle
* mwa_read will read whole world, no need to fiddle
* with address. It will be truncated in set_addr
*/
retval = avr32_jtag_mwa_read(jtag_info, SLAVE_HSB_UNCACHED,

2
src/target/embeddedice.h
View File

@ -106,7 +106,7 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout);
/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be
/* If many embeddedice_write_reg() follow each other, then the >1 invocations can be
* this faster version of embeddedice_write_reg
*/
static inline void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg_addr, uint32_t value)

2
src/target/target.c
View File

@ -5173,7 +5173,7 @@ no_params:
if (goi->isconfigure) {
struct command_context *cmd_ctx = current_command_context(goi->interp);
if (cmd_ctx->mode != COMMAND_CONFIG) {
Jim_SetResultString(goi->interp, "-gdb-max-conenctions must be configured before 'init'", -1);
Jim_SetResultString(goi->interp, "-gdb-max-connections must be configured before 'init'", -1);
return JIM_ERR;
}

2
src/target/target_type.h
View File

@ -79,7 +79,7 @@ struct target_type {
* state correctly.
*
* Otherwise the following would fail, as there will not
* be any "poll" invoked inbetween the "reset run" and
* be any "poll" invoked between the "reset run" and
* "halt".
*
* reset run; halt