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riscv-openocd
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Keep alive when accessing registers. 

With the bitbang performance decrease and talking to slower targets
(daisy chain spike) we more often don't meet the expected keepalive time
for gdb. This addresses the cases I ran into.

Change-Id: Ie69c2c602c3be9c156e508fdfa6d0178f104e1d8
Signed-off-by: Tim Newsome <tim@sifive.com>
This commit is contained in:
Tim Newsome 2021-05-12 11:43:26 -07:00
parent dd3dea88f7
commit 8fcc19d70b
1 changed files with 4 additions and 0 deletions
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4
src/target/riscv/riscv.c
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@ -3513,6 +3513,8 @@ int riscv_set_register(struct target *target, enum gdb_regno regid, riscv_reg_t
LOG_DEBUG("[%s] %s <- %" PRIx64, target_name(target), gdb_regno_name(regid), value);
assert(r->set_register);
keep_alive();
/* TODO: Hack to deal with gdb that thinks these registers still exist. */
if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 && value == 0 &&
riscv_supports_extension(target, 'E'))
@ -3536,6 +3538,8 @@ int riscv_get_register(struct target *target, riscv_reg_t *value,
{
RISCV_INFO(r);
keep_alive();
struct reg *reg = &target->reg_cache->reg_list[regid];
if (!reg->exist) {
LOG_DEBUG("[%s] %s does not exist.",