Commit Graph

4844 Commits

Author SHA1 Message Date
Tommy Murphy 16fa57da41 Fix riscv013_invalidate_cached_progbuf() off by one error
See https://github.com/riscv-collab/riscv-openocd/issues/1139
riscv013_invalidate_cached_progbuf() was failing to zeroize the final
buffer array element. Use memset() instead of a manual loop to zeroize
it in order to address this and simplify the code.
2024-10-03 09:37:28 +01:00
Evgeniy Naydanov 841b61adf3
Merge pull request #1134 from fk-sc/early-exit-support
target/riscv: early exit support for memory access operations
2024-09-30 10:49:35 +03:00
Farid Khaydari 173086a651 target/riscv: early exit support for memory access operations
(1) Error code and 'skip_reason' string were replaced with memory access
    status. It allows to specify whether OpenOCD should exit the access
    early.
(2) Slightly refactored 'read_memory' and 'write_memory' functions.

Checkpatch-ignore: MACRO_ARG_PRECEDENCE, MULTISTATEMENT_MACRO_USE_DO_WHILE
Checkpatch-ignore: TRAILING_SEMICOLON
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-09-27 12:27:11 +03:00
Evgeniy Naydanov 250aa20135 target/riscv: DMI logging improvements
Fixes #1043

There were multiple issuese with DMI logging:
1. Address was assumed to be the same (#1043).
2. Reported IDLE count was not affected by a reset of the delays.
3. VLA were used.

These issues are addressed in the commit.

Change-Id: I82f45505e8a62dfdd7dcb418784975fe10180109
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-09-26 12:25:28 +03:00
Evgeniy Naydanov 7f8c43a77d target/riscv: move `riscv_log_dmi_scan`
Change-Id: Iade30374331e9bde31a411b82056d47207cc39a8
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-09-23 18:28:51 +03:00
Evgeniy Naydanov 3bed4c8015
Merge pull request #1132 from en-sc/en-sc/from_upstream
Merge up to fd7b66c5eb from upstream
2024-09-19 17:46:25 +03:00
Evgeniy Naydanov 4c45762d76 target/breakpoints: fix types in `watchpoint_add_internal()`
There was a conflict:
1. commit 2cd8ebf44d ("breakpoints: use 64-bit type for watchpoint mask
   and value")
2. commit 0bf3373e80 ("target/breakpoints: Use 'unsigned int' for
   length")

The second commit was created erlier, but merged later so the types of
`mask` and `value` became `uint32_t` in `watchpoint_add_internal()`.

This created a bug:
`WATCHPOINT_IGNORE_DATA_VALUE_MASK` is defined as `(~(uint64_t)0)`.
Truncation to uint32_t makes it so the comparisons with the constant
don't work.

Change-Id: I19c414c351f52aff72a60330d83c29db7bbca375
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-09-16 18:41:08 +03:00
Evgeniy Naydanov 269c57e376 Merge up to fd7b66c5eb from upstream
Backports the fix for #1131.

Commit 0bf3373 ("target/breakpoints: Use 'unsigned int' for length")
introduces a bug.
Link: https://review.openocd.org/c/openocd/+/7056/comment/3c4d9185_83614e2a/

Change-Id: I9f5f67050698a83c27f84965f6de031e2cad492d
2024-09-16 18:38:05 +03:00
Richard Allen 930ec2f439 target/espressif: add profiling function for ESP32-S3
Use the TRAX interface DEBUGPC if available.
Otherwise use default stop-and-go profiling.

ESP32-S3, before this patch:
	Internal: 8 samples/second
	FT2232H: 12 samples/second

After this patch:
	Internal: 18ksamples/second
	FT2232H: 100ksamples/second

Change-Id: I681f0bccf4263c1e24f38be511e3b3aec8bf4d60
Signed-off-by: Richard Allen <rsaxvc@rsaxvc.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/8431
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Yurii Shutkin <yurii.shutkin@gmail.com>
2024-09-15 09:13:05 +00:00
Parshintsev Anatoly 7a70a28e6b target/riscv: do not emit warnings when a non-existent CSR is hidden
hide_csrs should not emit warnings on an attempt to hide non-exitents CSR.
hide_csrs funcitonality is intended to be used for scenarios when we don`t
want certain groups of registers to be available in GDB. Typically this is
needed to simplify integration with various IDE. In such scenarious it may
be impractical/unfeseable to figure out which register is present on a
target. So reporting a situation when a user wants to hide a non-existent
register creates way too much noise. This commit reduces severity of
relevant debug message to LOG_TARGET_DEBUG

Change-Id: Icbb982c4bcce7586fe35b6b004d0874d6014d5a7
2024-09-10 12:59:53 +03:00
Evgeniy Naydanov 826923fa60 Revert "target/riscv: re-apply patch do stop avoid warnings when a non-existent CSR is hidden"
This reverts commit e56dc61697.

The reverted commit claims to be the same as
b201a5db23, but it's not -- it changes the
warning in `riscv_reg_impl_expose_csrs()` instead of the one in
`riscv_reg_impl_hide_csrs()`.
2024-09-10 12:55:04 +03:00
Evgeniy Naydanov c85d4e1858
Merge pull request #1129 from rtwfroody/calloc
target/riscv: Fix calloc calls.
2024-09-10 12:02:06 +03:00
Tim Newsome 77bffed1c4 target/riscv: Fix calloc calls.
This was pointed out by gcc. Presumably it's a newer warning. I doubt it
has any effect on anything.
2024-09-06 08:34:58 -07:00
Evgeniy Naydanov a96a0a4e39 target/riscv: avoid unnecessary IR scans
Change-Id: I03feb5c7d72d5aa38f2cc13c4ed30175cffde84a
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-09-06 16:12:39 +03:00
Evgeniy Naydanov 3cd99c08c7
Merge pull request #1112 from en-sc/en-sc/misa-xlen
target/riscv: check `misa` value before reporting
2024-09-06 15:58:39 +03:00
Evgeniy Naydanov d58c656f72
Merge pull request #1111 from en-sc/en-sc/ref-reg-manual-hwbp
target/riscv: manage triggers available to OpenOCD for internal use
2024-09-06 15:57:38 +03:00
Evgeniy Naydanov d7a7c9822e
Merge pull request #1125 from fk-sc/fk-sc/field-duplication
target/riscv: remove duplicate of progbufsize field
2024-09-06 12:23:37 +03:00
Evgeniy Naydanov 5a8697b3cf target/riscv: manage triggers available to OpenOCD for internal use
Before the change, if the user wrote to any `tdata*` register, OpenOCD
would sometimes start to disable all the triggers (by writing zeroes to
`tdata1`) and re-enable them again (by witing all trigger registers to the
values read before for each `tselect` value), e.g. on `step`
(see `disable/enable_triggers()`).

There are a couple of issues with such approach:
1. RISC-V Debug Specification does not require custom register types
   to support re-enabling by such sequence of writes (e.g. some custom
   trigger type may require writing a custom CSR to enable it).
2. OpenOCD may still overwrite these triggers when a user asks to set a
   new WP.

This commit introduces `riscv reserve_trigger ...` command to explicitly
mark the triggers OpenOCD should not touch.

Such approach allows to separate management of custom triggers and
offload it onto the user (e.g. disable/enable such triggers by setting up
an event handler on `step`-related events).

Change-Id: I3339000445185ab221368442a070f412bf44bfab
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-09-05 12:59:35 +03:00
Evgeniy Naydanov 6c021da8cc target/riscv: check `misa` value before reporting
Currently, during register file examination:
1. A read of an XPR is attempted via 64-bit abstract access.
2. If such a read fails (e.g. connection unstable) XLEN is assumed to be
   32.
3. Then `misa` is read. Since `misa` is a CSR and it may be only
   readable via program buffer, `s0` should be readable beforehand (at
   least some assumption about `xlen` should be made).
4. Before the commit, the `misa.mxl` field was not checked against
   `xlen`, therefore erroneous info may have been reported to the user.
   Moreover, the `examine()` would pass indicating no error at all.
5. After the commit, `misa.mxl` is checked against `xlen` value.

Change-Id: I3fe5bd6742e564e6de782aad9ed10e65c0728923
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-09-05 11:56:59 +03:00
Evgeniy Naydanov 909bbb899b
Merge pull request #1115 from en-sc/en-sc/fixup-bscan
target/riscv: restrict BSCAN-related commands to before-`init`
2024-09-04 19:40:41 +03:00
Farid Khaydari a61e7271ef target/riscv: remove duplicate progbufsize field
* removed `progbuf_size`  field from `riscv_info`; added getter
* moved `impebreak` field from `riscv_info` to `riscv013_info`
  as implementation dependent field; added getter

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-09-04 17:55:14 +03:00
Anatoly Parshintsev 22bbdd2a5e
Merge pull request #1109 from aap-sc/aap-sc/sbus_fixup
target/riscv: sys bus v1 fix for sizes greater than 4
2024-09-03 11:07:31 +03:00
Anatoly Parshintsev 8ea44aa381
Merge pull request #1118 from aap-sc/aap-sc/fixup_hidecsr_warnings
target/riscv: re-apply patch do stop avoid warnings when a non-existent CSR is hidden
2024-08-30 01:15:36 +03:00
Tomas Vanek e09bb72da5 target/cortex_m: add DSCSR_CDSKEY bit definition
Needed e.g. for flash drivers handling secure mode.

Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: If6cb49609140d06a73bcf2e446b6a634d6326e80
Reviewed-on: https://review.openocd.org/c/openocd/+/8435
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-08-25 12:44:16 +00:00
Richard Allen 5cb184a732 target: fix profiler output on Windows
Open output file in binary mode to disable EOL
conversion on Windows (and sometimes cygwin depending
on installation settings and path).

Change-Id: I38276dd1af011ce5781b0264b7cbb08c32a1a2ad
Signed-off-by: Richard Allen <rsaxvc@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8278
Reviewed-by: Karl Palsson <karlp@tweak.au>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-08-25 12:42:44 +00:00
Marc Schink 0bf3373e80 target/breakpoints: Use 'unsigned int' for length
Change-Id: I233efb5b18de5f043fdc976807437db0a94236d1
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7056
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2024-08-25 12:41:05 +00:00
Peter Collingbourne 941fa8538f arm_cti: Add CTIDEVCTL to register list
This is useful for setting a reset catch on a CPU that is being
brought out of reset.

Change-Id: Id8fe9bc3f75fd170f207f470a9f3b0faba7f24c1
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8422
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-08-25 12:40:24 +00:00
Peter Collingbourne fc1e73b9cf arm_cti: Clean up the list of CTI registers
Reduce the amount of boilerplate by moving cti_regs into its only
user, making it a local variable and removing the now-redundant
p_val pointer.

Change-Id: I778cc1e960532fae1ac1a952c6ff19c54e578a5f
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8421
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2024-08-25 12:40:00 +00:00
Peter Collingbourne 7eb9a48f2d arm_adi_v5: Also clear sticky overrun bit on init
Some targets start up with the sticky overrun bit set. On such targets
we need to clear it in order to avoid subsequent incorrect reads.

Change-Id: I3e939a9e092de6fcea9494d3179a3386aa1701d2
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8420
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2024-08-25 12:39:25 +00:00
Antonio Borneo d3f50ea914 target: arm_adi_v5: add more CoreSight P/N
Add part numbers for:
- Cortex-A65AE,
- Cortex-M52,
- Cortex-M55,
- Cortex-R52+,
- STAR-MC1.

Change-Id: I6282768896dd727e803a071139816494470744f1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8319
Tested-by: jenkins
2024-08-25 12:38:28 +00:00
Marc Schink 16429f6252 target/arm_cti: Use suitable data types
While at it, fix some small coding style issues.

Change-Id: Ifb8e78b55d29a06d69a3ce71d12d0040777aef13
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8423
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-08-25 12:37:20 +00:00
Antonio Borneo ea859e1cd0 helper: command: drop radix parameter from command_parse_str_to_buf()
Commit 53b94fad58 ("binarybuffer: Fix str_to_buf() parsing
function") introduces the helper command_parse_str_to_buf() to
parse as number a string on TCL command-line.
The parameter 'radix' can specify the base (decimal, octal,
hexadecimal, or auto-detected).

TCL is supposed to use decimal numbers by default, while octal and
hexadecimal numbers must be prefixed respectively with '0' and
'0x' (or '0X').
This would require the helper to always run auto-detection of the
base, thus always set the 'radix' parameter to zero. This makes
the parameter useless.

Keeping the 'radix' parameter can open the door to future abuse of
TCL syntax, E.g. a command can require an octal value without the
mandatory TCL '0' prefix; the octal value cannot be the result of
TCL expression.

To prevent any future abuse of the 'radix' parameter, drop it.

Change-Id: I88855bd83b4e08e8fdcf86a2fa5ef3269dd4ad57
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8393
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
2024-08-25 12:35:47 +00:00
Parshintsev Anatoly e56dc61697 target/riscv: re-apply patch do stop avoid warnings when a non-existent CSR is hidden
the original fix was introduced in b201a5db23 but was lost in 3883b03a
2024-08-21 19:18:10 +03:00
Parshintsev Anatoly 9740a4ddd6 Merge up to ac63cd00d7 from upstream
- src/jtag/drivers/ftdi.c:

```
++<<<<<<< HEAD
 +      int i;
 +      static const uint8_t zero;
++=======
+       uint8_t zero = 0;
++>>>>>>> ocd_upstream
```

Decided to choose the latter.

- src/target/riscv/riscv-013.c:

```
++<<<<<<< HEAD
 +      int abs_chain_position;
 +      /* The base address to access this DM on DMI */
 +      uint32_t base;
++=======
+       unsigned int abs_chain_position;
+
++>>>>>>> ocd_upstream
```

Decided to choose the latter (abs_chain_position is unsigned now)

- src/target/riscv/batch.c:

```
++<<<<<<< HEAD
++=======
+ void dump_field(int idle, const struct scan_field *field)
+ {
  ...
+ }
++>>>>>>> ocd_upstream
```

dump_field function is not needed anymore

Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2024-08-20 15:44:15 +03:00
Evgeniy Naydanov e07d70e52c
Merge pull request #1114 from en-sc/en-sc/dup-dtmcontrol
target/riscv: remove duplicate `dtmcontrol_scan()`
2024-08-16 17:06:10 +03:00
Parshintsev Anatoly ebb8c057a6 target/riscv: sys bus v1 fix for sizes greater than 4
read_memory_bus_v1 incorrectly copied data to output buffer

Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2024-08-15 21:17:51 +03:00
Evgeniy Naydanov 342f294031 target/riscv: restrict BSCAN-related commands to before-`init`
Logically, BSCAN tunneling is used to establish a connection, therefore
it should be set up before the communication starts (i.e. before
`init`).

Moreover, current implementation does not support changing
`bscan_tunnel_ir_width` after `init`. This is evident by RISC-V handler
of the `init` itself.
Link: 9a23c9e679/src/target/riscv/riscv.c (L467-L481)

Change-Id: I817c6a996f7f7171b2286e181daf1092bd358f69
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-08-14 20:50:32 +03:00
Evgeniy Naydanov 4379e84380 target/riscv: remove duplicate `dtmcontrol_scan()`
Also avoid receiving data if the value is discarded on the call-site.

Change-Id: Ied87b551536a00d9fad469b9843cccae1976e6b6
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-08-14 20:13:36 +03:00
Evgeniy Naydanov 5f45b5bd73 target/riscv: reg cache entry is initialized before access
* Register file examination is separated.
* Allow to access registers through cache as early as possible to re-use
  general register access interface and propely track state of the
  register.
* Reduces the number of operations: S0 and S1 are saved/restored only
  when needed (targets without abstract CSR access).

Change-Id: I2e205ae4e88733a5c792f8a35cf30325c68d96b2
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-08-14 19:24:11 +03:00
Evgeniy Naydanov 9a23c9e679
Merge pull request #1104 from TommyMurphyTM1234/fix-include-guards
Align include guards with OpenOCD coding guidelines
2024-08-08 15:25:15 +03:00
Marc Schink d5adab697f target/breakpoints: Fix 'orig_instr' output
The 'orig_instr' information of software breakpoints is incorrect
because buf_to_hex_str() expects the length of the buffer to be
converted in bits and not bytes.

Change-Id: I9a9ed383a8c25200d461b899749d5259ee4c6e3d
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8218
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2024-08-02 16:07:33 +00:00
Marc Schink 7d56407ba7 jtag: Use 'unsigned int' for 'scan_field.num_bits'
This patch modifies as little code as possible in order to simplify the
review. Data types that are affected by these changes will be addresses
in following patches.

While at it, apply coding style fixes if these are not too extensive.

Change-Id: Idcbbbbbea2705512201eb326c3e6cef110dbc674
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8413
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-08-02 16:04:49 +00:00
Marc Schink 9ef59daef0 target/avrt: Remove unused parameter 'rti'
Change-Id: Ib6957b89190188f5c15fadc3d4036709f19a6cea
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8412
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-08-02 16:04:24 +00:00
Marc Schink 0847a4d7fb jtag/commands: Use 'unsigned int' data type
This patch modifies as little code as possible in order to simplify the
review. Data types that are affected by these changes will be addresses
in following patches.

While at it, apply coding style fixes if these are not too extensive.

Change-Id: Ie048b3d472f546fecb6733f17f9d0f17fda40187
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8404
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-08-02 16:03:28 +00:00
Marc Schink 42450345dd jtag: Use 'unsigned int' for 'ir_length'
This patch modifies as little code as possible in order to simplify the
review. Data types that are affected by these changes will be modified
in following patches.

Change-Id: I83921d70e017095d63547e0bc9fe61779191d9d0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8403
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-08-02 16:02:25 +00:00
Marc Schink 4fac13827f jtag: Use 'unsigned int' for 'abs_chain_position'
Change-Id: I1ac0a6a86f820b051619aa132754a69b8f8e0ab9
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8402
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-08-02 16:01:59 +00:00
Antonio Borneo 5b7b77349c cortex_m: fix scan-build false positive
Scan-build is unable to detect that 'target->dbg_msg_enabled' does
not change across the function cortex_m_fast_read_all_regs().
It incorrectly assumes that it can be false at the first check (so
'dcrdr' get not assigned) and it is true later on (when 'dcrdr'
get used).
This triggers a false positive:
	src/target/cortex_m.c:338:12: warning:
		3rd function call argument is an uninitialized value
		[core.CallAndMessage]
	retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);

Use a local variable for 'target->dbg_msg_enabled' so scan-build
can track it as not modified.
While there, change the type of 'target->dbg_msg_enabled' to
boolean as there is no reason to use uint32_t.

Change-Id: Icaf1a1b2dea8bc55108182ea440708ab76396cd7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8391
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2024-07-28 13:26:05 +00:00
Evgeniy Naydanov 9a489be795 target/riscv: single DMI accesses via batch
* Eliminates the use of VLA, which is prohibited by `doc/manual
/style.txt`:
Link: c6bb902629/doc/manual/style.txt (L164-L166)

* Unifies DMI access interface.

* Reduces code duplication.

Change-Id: I2d7b0595f171e21062049ff61f76fb5a3c992d11
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-16 16:43:46 +03:00
Marc Schink 44cfdef0a4 server/gdb: Restructure commands
Use a command group 'gdb' with subcommands instead of individual
commands with 'gdb_' prefix.

The old commands are still available to ensure backwards compatibility,
but are marked as deprecated.

Change-Id: I037dc58554e589d5710cf46924e0a00f863aa300
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8336
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-07-13 22:28:12 +00:00
Jan Matyas 53b94fad58 binarybuffer: Fix str_to_buf() parsing function
The function str_to_buf() was too benevolent and did
not perform sufficient error checking on the input
string being parsed. Especially:

- Invalid numbers were silently ignored.
- Out-of-range numbers were silently truncated.

The following commands that use str_to_buf()
were affected:

- reg (when writing a register value)
- set_reg
- jtag drscan

This pull request fixes that by:

- Rewriting str_to_buf() to add the missing checks.
- Adding function command_parse_str_to_buf() which can
  be used in command handlers. It parses the input
  numbers and provides user-readable error messages
  in case of parsing errors.

Examples:

jtag drscan 10 huh10

- Old behavior: The string "huh10" is silently
  converted to 10 and the command is then executed.
  No warning error or warning is shown to the user.
- New behavior: Error message is shown:
  "'huh10' is not a valid number"

reg pc 0x123456789

Assuming the "pc" is 32 bits wide:

- Old behavior: The register value is silently
  truncated to 0x23456789 and the command is performed.
- New behavior: Error message is shown to the user:
  "Number 0x123456789 exceeds 32 bits"

Change-Id: I079e19cd153aec853a3c2eb66953024b8542d0f4
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8315
Tested-by: jenkins
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-07-13 22:23:15 +00:00