Merge pull request #1104 from TommyMurphyTM1234/fix-include-guards
Align include guards with OpenOCD coding guidelines
This commit is contained in:
commit
9a23c9e679
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef TARGET__RISCV__ASM_H
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#define TARGET__RISCV__ASM_H
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#ifndef OPENOCD_TARGET_RISCV_ASM_H
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#define OPENOCD_TARGET_RISCV_ASM_H
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#include "riscv.h"
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@ -37,4 +37,4 @@ static uint32_t store(const struct target *target, unsigned int src,
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return 0; /* Silence -Werror=return-type */
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}
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#endif
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#endif /* OPENOCD_TARGET_RISCV_ASM_H */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef TARGET__RISCV__SCANS_H
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#define TARGET__RISCV__SCANS_H
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#ifndef OPENOCD_TARGET_RISCV_BATCH_H
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#define OPENOCD_TARGET_RISCV_BATCH_H
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#include "target/target.h"
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#include "jtag/jtag.h"
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@ -234,4 +234,4 @@ bool riscv_batch_was_batch_busy(const struct riscv_batch *batch);
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void riscv_log_dmi_scan(const struct target *target, int idle,
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const struct scan_field *field);
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#endif
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#endif /* OPENOCD_TARGET_RISCV_BATCH_H */
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@ -1,5 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef OPENOCD_TARGET_RISCV_DEBUG_REG_PRINTER_H
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#define OPENOCD_TARGET_RISCV_DEBUG_REG_PRINTER_H
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#include "debug_defines.h"
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enum riscv_debug_reg_show {
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@ -33,3 +36,5 @@ enum riscv_debug_reg_show {
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unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal,
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riscv_debug_reg_ctx_t context, uint64_t value,
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enum riscv_debug_reg_show show);
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#endif /* OPENOCD_TARGET_RISCV_DEBUG_REG_PRINTER_H */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef FIELD_HELPERS_H
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#define FIELD_HELPERS_H
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#ifndef OPENOCD_TARGET_RISCV_FIELD_HELPERS_H
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#define OPENOCD_TARGET_RISCV_FIELD_HELPERS_H
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#include <stdint.h>
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#include <assert.h>
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@ -44,4 +44,4 @@ static inline uint32_t field_value32(uint32_t mask, uint32_t val)
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return set_field32(0, mask, val);
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}
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#endif
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#endif /* OPENOCD_TARGET_RISCV_FIELD_HELPERS_H */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef TARGET__RISCV__GDB_REGS_H
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#define TARGET__RISCV__GDB_REGS_H
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#ifndef OPENOCD_TARGET_RISCV_GDB_REGS_H
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#define OPENOCD_TARGET_RISCV_GDB_REGS_H
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#include "encoding.h"
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@ -125,4 +125,4 @@ enum gdb_regno {
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GDB_REGNO_COUNT
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};
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#endif
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#endif /* OPENOCD_TARGET_RISCV_GDB_REGS_H */
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@ -1,5 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef OPENOCD_TARGET_RISCV_OPCODES_H
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#define OPENOCD_TARGET_RISCV_OPCODES_H
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#include "encoding.h"
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#define ZERO 0
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@ -339,3 +342,4 @@ static uint32_t vslide1down_vx(unsigned int vd, unsigned int vs2,
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return ((vm & 1) << 25) | inst_rs2(vs2) | inst_rs1(rs1) | inst_rd(vd) | MATCH_VSLIDE1DOWN_VX;
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}
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#endif /* OPENOCD_TARGET_RISCV_OPCODES_H */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef TARGET__RISCV__PROGRAM_H
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#define TARGET__RISCV__PROGRAM_H
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#ifndef OPENOCD_TARGET_RISCV_PROGRAM_H
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#define OPENOCD_TARGET_RISCV_PROGRAM_H
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#include "riscv.h"
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@ -77,4 +77,4 @@ int riscv_program_ebreak(struct riscv_program *p);
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int riscv_program_addi(struct riscv_program *p, enum gdb_regno d, enum gdb_regno s, int16_t i);
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#endif
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#endif /* OPENOCD_TARGET_RISCV_PROGRAM_H */
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@ -12,4 +12,4 @@ int riscv011_get_register(struct target *target, riscv_reg_t *value,
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int riscv011_set_register(struct target *target, enum gdb_regno regid,
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riscv_reg_t value);
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#endif /*OPENOCD_TARGET_RISCV_RISCV_011_H*/
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#endif /* OPENOCD_TARGET_RISCV_RISCV_011_H */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef OPENOCD_TARGET_RISCV_RISCV_REG_011_H
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#define OPENOCD_TARGET_RISCV_RISCV_REG_011_H
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#ifndef OPENOCD_TARGET_RISCV_RISCV_011_REG_H
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#define OPENOCD_TARGET_RISCV_RISCV_011_REG_H
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#include "target/target.h"
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@ -16,4 +16,4 @@
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*/
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int riscv011_reg_init_all(struct target *target);
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#endif /*OPENOCD_TARGET_RISCV_RISCV_REG_011_H*/
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#endif /* OPENOCD_TARGET_RISCV_RISCV_011_REG_H */
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@ -20,4 +20,4 @@ int riscv013_set_register(struct target *target, enum gdb_regno rid,
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int riscv013_set_register_buf(struct target *target, enum gdb_regno regno,
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const uint8_t *value);
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#endif /*OPENOCD_TARGET_RISCV_RISCV_013_H*/
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#endif /* OPENOCD_TARGET_RISCV_RISCV_013_H */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef OPENOCD_TARGET_RISCV_RISCV_REG_013_H
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#define OPENOCD_TARGET_RISCV_RISCV_REG_013_H
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#ifndef OPENOCD_TARGET_RISCV_RISCV_013_REG_H
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#define OPENOCD_TARGET_RISCV_RISCV_013_REG_H
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#include "target/target.h"
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#include "gdb_regs.h"
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*/
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int riscv013_reg_save(struct target *target, enum gdb_regno regid);
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#endif /*OPENOCD_TARGET_RISCV_RISCV_REG_013_H*/
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#endif /* OPENOCD_TARGET_RISCV_RISCV_013_REG_H */
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef RISCV_H
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#define RISCV_H
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#ifndef OPENOCD_TARGET_RISCV_RISCV_H
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#define OPENOCD_TARGET_RISCV_RISCV_H
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struct riscv_program;
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@ -433,4 +433,4 @@ int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32
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int riscv_interrupts_disable(struct target *target, uint64_t ie_mask, uint64_t *old_mstatus);
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int riscv_interrupts_restore(struct target *target, uint64_t old_mstatus);
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#endif
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#endif /* OPENOCD_TARGET_RISCV_RISCV_H */
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