target/riscv: single DMI accesses via batch
* Eliminates the use of VLA, which is prohibited by `doc/manual
/style.txt`:
Link: c6bb902629/doc/manual/style.txt (L164-L166)
* Unifies DMI access interface.
* Reduces code duplication.
Change-Id: I2d7b0595f171e21062049ff61f76fb5a3c992d11
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This commit is contained in:
Evgeniy Naydanov
parent
87c581a80d
commit
9a489be795
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@ -190,8 +190,7 @@ int riscv_batch_run_from(struct riscv_batch *batch, size_t start_idx,
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for (size_t i = start_idx; i < batch->used_scans; ++i) {
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const int delay = get_delay(batch, i, delays);
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riscv_log_dmi_scan(batch->target, delay, batch->fields + i,
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/*discard_in*/ false);
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riscv_log_dmi_scan(batch->target, delay, batch->fields + i);
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}
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batch->was_run = true;
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@ -199,14 +198,14 @@ int riscv_batch_run_from(struct riscv_batch *batch, size_t start_idx,
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return ERROR_OK;
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}
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void riscv_batch_add_dm_write(struct riscv_batch *batch, uint64_t address, uint32_t data,
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void riscv_batch_add_dmi_write(struct riscv_batch *batch, uint64_t address, uint32_t data,
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bool read_back, enum riscv_scan_delay_class delay_class)
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{
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assert(batch->used_scans < batch->allocated_scans);
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struct scan_field *field = batch->fields + batch->used_scans;
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field->num_bits = riscv_get_dmi_scan_length(batch->target);
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field->out_value = (void *)(batch->data_out + batch->used_scans * DMI_SCAN_BUF_SIZE);
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riscv_fill_dm_write(batch->target, (char *)field->out_value, address, data);
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riscv_fill_dmi_write(batch->target, (char *)field->out_value, address, data);
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if (read_back) {
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field->in_value = (void *)(batch->data_in + batch->used_scans * DMI_SCAN_BUF_SIZE);
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riscv_fill_dm_nop(batch->target, (char *)field->in_value);
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@ -218,7 +217,7 @@ void riscv_batch_add_dm_write(struct riscv_batch *batch, uint64_t address, uint3
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batch->used_scans++;
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}
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size_t riscv_batch_add_dm_read(struct riscv_batch *batch, uint64_t address,
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size_t riscv_batch_add_dmi_read(struct riscv_batch *batch, uint64_t address,
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enum riscv_scan_delay_class delay_class)
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{
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assert(batch->used_scans < batch->allocated_scans);
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@ -226,7 +225,7 @@ size_t riscv_batch_add_dm_read(struct riscv_batch *batch, uint64_t address,
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field->num_bits = riscv_get_dmi_scan_length(batch->target);
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field->out_value = (void *)(batch->data_out + batch->used_scans * DMI_SCAN_BUF_SIZE);
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field->in_value = (void *)(batch->data_in + batch->used_scans * DMI_SCAN_BUF_SIZE);
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riscv_fill_dm_read(batch->target, (char *)field->out_value, address);
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riscv_fill_dmi_read(batch->target, (char *)field->out_value, address);
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riscv_fill_dm_nop(batch->target, (char *)field->in_value);
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batch->delay_classes[batch->used_scans] = delay_class;
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batch->last_scan = RISCV_SCAN_TYPE_READ;
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@ -190,14 +190,32 @@ int riscv_batch_run_from(struct riscv_batch *batch, size_t start_idx,
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size_t riscv_batch_finished_scans(const struct riscv_batch *batch);
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/* Adds a DM register write to this batch. */
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void riscv_batch_add_dm_write(struct riscv_batch *batch, uint64_t address, uint32_t data,
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void riscv_batch_add_dmi_write(struct riscv_batch *batch, uint64_t address, uint32_t data,
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bool read_back, enum riscv_scan_delay_class delay_class);
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static inline void
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riscv_batch_add_dm_write(struct riscv_batch *batch, uint64_t address, uint32_t data,
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bool read_back, enum riscv_scan_delay_class delay_type)
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{
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return riscv_batch_add_dmi_write(batch,
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riscv_get_dmi_address(batch->target, address), data,
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read_back, delay_type);
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}
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/* DM register reads must be handled in two parts: the first one schedules a read and
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* provides a key, the second one actually obtains the result of the read -
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* status (op) and the actual data. */
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size_t riscv_batch_add_dm_read(struct riscv_batch *batch, uint64_t address,
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size_t riscv_batch_add_dmi_read(struct riscv_batch *batch, uint64_t address,
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enum riscv_scan_delay_class delay_class);
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static inline size_t
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riscv_batch_add_dm_read(struct riscv_batch *batch, uint64_t address,
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enum riscv_scan_delay_class delay_type)
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{
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return riscv_batch_add_dmi_read(batch,
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riscv_get_dmi_address(batch->target, address), delay_type);
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}
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unsigned int riscv_batch_get_dmi_read_op(const struct riscv_batch *batch, size_t key);
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uint32_t riscv_batch_get_dmi_read_data(const struct riscv_batch *batch, size_t key);
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@ -213,7 +231,7 @@ bool riscv_batch_was_batch_busy(const struct riscv_batch *batch);
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/* TODO: The function is defined in `riscv-013.c`. This is done to reduce the
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* diff of the commit. The intention is to move the function definition to
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* a separate module (e.g. `riscv013-jtag-dtm.c/h`) in another commit. */
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void riscv_log_dmi_scan(const struct target *target, int idle, const struct scan_field *field,
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bool discard_in);
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void riscv_log_dmi_scan(const struct target *target, int idle,
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const struct scan_field *field);
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#endif
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@ -56,10 +56,7 @@ static int riscv013_invalidate_cached_progbuf(struct target *target);
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static int riscv013_execute_progbuf(struct target *target, uint32_t *cmderr);
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static void riscv013_fill_dmi_write(struct target *target, char *buf, uint64_t a, uint32_t d);
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static void riscv013_fill_dmi_read(struct target *target, char *buf, uint64_t a);
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static void riscv013_fill_dmi_nop(struct target *target, char *buf);
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static int riscv013_get_dmi_scan_length(struct target *target);
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static void riscv013_fill_dm_write(struct target *target, char *buf, uint64_t a, uint32_t d);
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static void riscv013_fill_dm_read(struct target *target, char *buf, uint64_t a);
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static void riscv013_fill_dm_nop(struct target *target, char *buf);
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static unsigned int register_size(struct target *target, enum gdb_regno number);
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static int register_read_direct(struct target *target, riscv_reg_t *value,
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@ -376,7 +373,9 @@ static unsigned int decode_dmi(const struct target *target, char *text, uint32_t
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return 0;
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}
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void riscv_log_dmi_scan(const struct target *target, int idle, const struct scan_field *field, bool discard_in)
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/* TODO: Move this function to "batch.c" and make it static. */
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void riscv_log_dmi_scan(const struct target *target, int idle,
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const struct scan_field *field)
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{
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static const char * const op_string[] = {"-", "r", "w", "?"};
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static const char * const status_string[] = {"+", "?", "F", "b"};
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@ -400,7 +399,7 @@ void riscv_log_dmi_scan(const struct target *target, int idle, const struct scan
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field->num_bits, op_string[out_op], out_data, out_address,
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status_string[in_op], in_data, in_address, idle);
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if (!discard_in && in_op == DTM_DMI_OP_SUCCESS) {
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if (in_op == DTM_DMI_OP_SUCCESS) {
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char in_decoded[decode_dmi(target, NULL, in_address, in_data) + 1];
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decode_dmi(target, in_decoded, in_address, in_data);
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/* FIXME: The current code assumes that the hardware
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@ -506,220 +505,6 @@ static void decrement_reset_delays_counter(struct target *target, size_t finishe
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"resetting learned delays (reset_delays_wait counter expired)");
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reset_learned_delays(target);
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}
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/**
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* exec: If this is set, assume the scan results in an execution, so more
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* run-test/idle cycles may be required.
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*/
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static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in,
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uint32_t *data_in, dmi_op_t op, uint32_t address_out, uint32_t data_out,
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bool exec)
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{
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riscv013_info_t *info = get_info(target);
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unsigned num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH;
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size_t num_bytes = (num_bits + 7) / 8;
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uint8_t in[num_bytes];
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uint8_t out[num_bytes];
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struct scan_field field = {
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.num_bits = num_bits,
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.out_value = out,
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.in_value = in
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};
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riscv_bscan_tunneled_scan_context_t bscan_ctxt;
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decrement_reset_delays_counter(target, 1);
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memset(in, 0, num_bytes);
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memset(out, 0, num_bytes);
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if (info->abits == 0) {
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LOG_TARGET_ERROR(target, "Can't access DMI because addrbits=0.");
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return DMI_STATUS_FAILED;
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}
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buf_set_u32(out, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, op);
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buf_set_u32(out, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, data_out);
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buf_set_u32(out, DTM_DMI_ADDRESS_OFFSET, info->abits, address_out);
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/* I wanted to place this code in a different function, but the way JTAG command
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queueing works in the jtag handling functions, the scan fields either have to be
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heap allocated, global/static, or else they need to stay on the stack until
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the jtag_execute_queue() call. Heap or static fields in this case doesn't seem
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the best fit. Declaring stack based field values in a subsidiary function call wouldn't
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work. */
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if (bscan_tunnel_ir_width != 0) {
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riscv_add_bscan_tunneled_scan(target, &field, &bscan_ctxt);
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} else {
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/* Assume dbus is already selected. */
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jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
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}
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int idle_count = exec
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? riscv_scan_get_delay(&info->learned_delays, RISCV_DELAY_ABSTRACT_COMMAND)
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: riscv_scan_get_delay(&info->learned_delays, RISCV_DELAY_BASE);
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if (idle_count)
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jtag_add_runtest(idle_count, TAP_IDLE);
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int retval = jtag_execute_queue();
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if (retval != ERROR_OK) {
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LOG_ERROR("dmi_scan failed jtag scan");
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if (data_in)
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*data_in = ~0;
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return DMI_STATUS_FAILED;
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}
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if (bscan_tunnel_ir_width != 0) {
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/* need to right-shift "in" by one bit, because of clock skew between BSCAN TAP and DM TAP */
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buffer_shr(in, num_bytes, 1);
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}
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if (data_in)
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*data_in = buf_get_u32(in, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH);
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if (address_in)
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*address_in = buf_get_u32(in, DTM_DMI_ADDRESS_OFFSET, info->abits);
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riscv_log_dmi_scan(target, idle_count, &field, /*discard_in*/ !data_in);
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return buf_get_u32(in, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH);
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}
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/**
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* @param target
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* @param data_in The data we received from the target.
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* @param dmi_busy_encountered
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* If non-NULL, will be updated to reflect whether DMI busy was
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* encountered while executing this operation or not.
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* @param op The operation to perform (read/write/nop).
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* @param address The address argument to that operation.
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* @param data_out The data to send to the target.
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* @param timeout_sec
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* @param exec When true, this scan will execute something, so extra RTI
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* cycles may be added.
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* @param ensure_success
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* Scan a nop after the requested operation, ensuring the
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* DMI operation succeeded.
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*/
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static int dmi_op_timeout(struct target *target, uint32_t *data_in,
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bool *dmi_busy_encountered, int op, uint32_t address,
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uint32_t data_out, int timeout_sec, bool exec, bool ensure_success)
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{
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select_dmi(target);
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dmi_status_t status;
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if (dmi_busy_encountered)
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*dmi_busy_encountered = false;
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const char *op_name;
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switch (op) {
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case DMI_OP_NOP:
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op_name = "nop";
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break;
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case DMI_OP_READ:
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op_name = "read";
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break;
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case DMI_OP_WRITE:
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op_name = "write";
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break;
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default:
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LOG_ERROR("Invalid DMI operation: %d", op);
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return ERROR_FAIL;
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}
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keep_alive();
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time_t start = time(NULL);
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/* This first loop performs the request. Note that if for some reason this
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* stays busy, it is actually due to the previous access. */
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while (1) {
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status = dmi_scan(target, NULL, NULL, op, address, data_out,
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exec);
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if (status == DMI_STATUS_BUSY) {
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int result = increase_dmi_busy_delay(target);
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if (result != ERROR_OK)
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return result;
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if (dmi_busy_encountered)
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*dmi_busy_encountered = true;
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} else if (status == DMI_STATUS_SUCCESS) {
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break;
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} else {
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dtmcontrol_scan(target, DTM_DTMCS_DMIRESET, NULL /* discard result */);
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break;
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}
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if (time(NULL) - start > timeout_sec)
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return ERROR_TIMEOUT_REACHED;
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}
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if (status != DMI_STATUS_SUCCESS) {
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LOG_TARGET_ERROR(target, "Failed DMI %s at 0x%x; status=%d", op_name, address, status);
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return ERROR_FAIL;
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}
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if (ensure_success) {
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/* This second loop ensures the request succeeded, and gets back data.
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* Note that NOP can result in a 'busy' result as well, but that would be
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* noticed on the next DMI access we do. */
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while (1) {
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status = dmi_scan(target, NULL, data_in, DMI_OP_NOP, address, 0,
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false);
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if (status == DMI_STATUS_BUSY) {
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int result = increase_dmi_busy_delay(target);
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if (result != ERROR_OK)
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return result;
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if (dmi_busy_encountered)
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*dmi_busy_encountered = true;
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} else if (status == DMI_STATUS_SUCCESS) {
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break;
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} else {
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if (data_in) {
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LOG_TARGET_ERROR(target,
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"Failed DMI %s (NOP) at 0x%x; value=0x%x, status=%d",
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op_name, address, *data_in, status);
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} else {
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LOG_TARGET_ERROR(target,
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"Failed DMI %s (NOP) at 0x%x; status=%d", op_name, address,
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status);
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}
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dtmcontrol_scan(target, DTM_DTMCS_DMIRESET, NULL /* discard result */);
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return ERROR_FAIL;
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}
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if (time(NULL) - start > timeout_sec)
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return ERROR_TIMEOUT_REACHED;
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}
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}
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return ERROR_OK;
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}
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static int dmi_op(struct target *target, uint32_t *data_in,
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bool *dmi_busy_encountered, int op, uint32_t address,
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uint32_t data_out, bool exec, bool ensure_success)
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{
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int result = dmi_op_timeout(target, data_in, dmi_busy_encountered, op,
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address, data_out, riscv_get_command_timeout_sec(), exec, ensure_success);
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if (result == ERROR_TIMEOUT_REACHED) {
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LOG_TARGET_ERROR(target, "DMI operation didn't complete in %d seconds. The target is "
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"either really slow or broken. You could increase the "
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"timeout with riscv set_command_timeout_sec.",
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riscv_get_command_timeout_sec());
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return ERROR_FAIL;
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}
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return result;
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}
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static int dmi_read(struct target *target, uint32_t *value, uint32_t address)
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{
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return dmi_op(target, value, NULL, DMI_OP_READ, address, 0, false, true);
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}
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static int dmi_read_exec(struct target *target, uint32_t *value, uint32_t address)
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{
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return dmi_op(target, value, NULL, DMI_OP_READ, address, 0, true, true);
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}
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static int dmi_write(struct target *target, uint32_t address, uint32_t value)
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{
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return dmi_op(target, NULL, NULL, DMI_OP_WRITE, address, value, false, true);
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}
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static uint32_t riscv013_get_dmi_address(const struct target *target, uint32_t address)
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{
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@ -731,12 +516,22 @@ static uint32_t riscv013_get_dmi_address(const struct target *target, uint32_t a
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return address + base;
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}
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static int batch_run_timeout(struct target *target, struct riscv_batch *batch);
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static int dmi_read(struct target *target, uint32_t *value, uint32_t address)
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{
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struct riscv_batch *batch = riscv_batch_alloc(target, 1);
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riscv_batch_add_dmi_read(batch, address, RISCV_DELAY_BASE);
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int res = batch_run_timeout(target, batch);
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if (res == ERROR_OK && value)
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*value = riscv_batch_get_dmi_read_data(batch, 0);
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riscv_batch_free(batch);
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return res;
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}
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static int dm_read(struct target *target, uint32_t *value, uint32_t address)
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{
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dm013_info_t *dm = get_dm(target);
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if (!dm)
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||||
return ERROR_FAIL;
|
||||
return dmi_read(target, value, address + dm->base);
|
||||
return dmi_read(target, value, riscv013_get_dmi_address(target, address));
|
||||
}
|
||||
|
||||
static int dm_read_exec(struct target *target, uint32_t *value, uint32_t address)
|
||||
|
|
@ -744,16 +539,29 @@ static int dm_read_exec(struct target *target, uint32_t *value, uint32_t address
|
|||
dm013_info_t *dm = get_dm(target);
|
||||
if (!dm)
|
||||
return ERROR_FAIL;
|
||||
struct riscv_batch *batch = riscv_batch_alloc(target, 1);
|
||||
riscv_batch_add_dm_read(batch, address, RISCV_DELAY_ABSTRACT_COMMAND);
|
||||
dm->abstract_cmd_maybe_busy = true;
|
||||
return dmi_read_exec(target, value, address + dm->base);
|
||||
int res = batch_run_timeout(target, batch);
|
||||
if (res == ERROR_OK && value)
|
||||
*value = riscv_batch_get_dmi_read_data(batch, 0);
|
||||
riscv_batch_free(batch);
|
||||
return res;
|
||||
}
|
||||
|
||||
static int dmi_write(struct target *target, uint32_t address, uint32_t value)
|
||||
{
|
||||
struct riscv_batch *batch = riscv_batch_alloc(target, 1);
|
||||
riscv_batch_add_dmi_write(batch, address, value, /*read_back*/ true,
|
||||
RISCV_DELAY_BASE);
|
||||
int res = batch_run_timeout(target, batch);
|
||||
riscv_batch_free(batch);
|
||||
return res;
|
||||
}
|
||||
|
||||
static int dm_write(struct target *target, uint32_t address, uint32_t value)
|
||||
{
|
||||
dm013_info_t *dm = get_dm(target);
|
||||
if (!dm)
|
||||
return ERROR_FAIL;
|
||||
return dmi_write(target, address + dm->base, value);
|
||||
return dmi_write(target, riscv013_get_dmi_address(target, address), value);
|
||||
}
|
||||
|
||||
static bool check_dbgbase_exists(struct target *target)
|
||||
|
|
@ -919,8 +727,6 @@ clear_cmderr:
|
|||
return res;
|
||||
}
|
||||
|
||||
static int batch_run_timeout(struct target *target, struct riscv_batch *batch);
|
||||
|
||||
static int execute_abstract_command(struct target *target, uint32_t command,
|
||||
uint32_t *cmderr)
|
||||
{
|
||||
|
|
@ -3095,8 +2901,8 @@ static int init_target(struct command_context *cmd_ctx,
|
|||
generic_info->write_progbuf = &riscv013_write_progbuf;
|
||||
generic_info->execute_progbuf = &riscv013_execute_progbuf;
|
||||
generic_info->invalidate_cached_progbuf = &riscv013_invalidate_cached_progbuf;
|
||||
generic_info->fill_dm_write = &riscv013_fill_dm_write;
|
||||
generic_info->fill_dm_read = &riscv013_fill_dm_read;
|
||||
generic_info->fill_dmi_write = &riscv013_fill_dmi_write;
|
||||
generic_info->fill_dmi_read = &riscv013_fill_dmi_read;
|
||||
generic_info->fill_dm_nop = &riscv013_fill_dm_nop;
|
||||
generic_info->get_dmi_scan_length = &riscv013_get_dmi_scan_length;
|
||||
generic_info->authdata_read = &riscv013_authdata_read;
|
||||
|
|
@ -5533,7 +5339,7 @@ static void riscv013_fill_dmi_read(struct target *target, char *buf, uint64_t a)
|
|||
buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
|
||||
}
|
||||
|
||||
static void riscv013_fill_dmi_nop(struct target *target, char *buf)
|
||||
static void riscv013_fill_dm_nop(struct target *target, char *buf)
|
||||
{
|
||||
RISCV013_INFO(info);
|
||||
buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_NOP);
|
||||
|
|
@ -5547,27 +5353,6 @@ static int riscv013_get_dmi_scan_length(struct target *target)
|
|||
return info->abits + DTM_DMI_DATA_LENGTH + DTM_DMI_OP_LENGTH;
|
||||
}
|
||||
|
||||
void riscv013_fill_dm_write(struct target *target, char *buf, uint64_t a, uint32_t d)
|
||||
{
|
||||
dm013_info_t *dm = get_dm(target);
|
||||
if (!dm)
|
||||
return;
|
||||
riscv013_fill_dmi_write(target, buf, a + dm->base, d);
|
||||
}
|
||||
|
||||
void riscv013_fill_dm_read(struct target *target, char *buf, uint64_t a)
|
||||
{
|
||||
dm013_info_t *dm = get_dm(target);
|
||||
if (!dm)
|
||||
return;
|
||||
riscv013_fill_dmi_read(target, buf, a + dm->base);
|
||||
}
|
||||
|
||||
void riscv013_fill_dm_nop(struct target *target, char *buf)
|
||||
{
|
||||
riscv013_fill_dmi_nop(target, buf);
|
||||
}
|
||||
|
||||
static int maybe_execute_fence_i(struct target *target)
|
||||
{
|
||||
if (has_sufficient_progbuf(target, 2))
|
||||
|
|
|
|||
|
|
@ -5587,16 +5587,16 @@ int riscv_execute_progbuf(struct target *target, uint32_t *cmderr)
|
|||
return r->execute_progbuf(target, cmderr);
|
||||
}
|
||||
|
||||
void riscv_fill_dm_write(struct target *target, char *buf, uint64_t a, uint32_t d)
|
||||
void riscv_fill_dmi_write(struct target *target, char *buf, uint64_t a, uint32_t d)
|
||||
{
|
||||
RISCV_INFO(r);
|
||||
r->fill_dm_write(target, buf, a, d);
|
||||
r->fill_dmi_write(target, buf, a, d);
|
||||
}
|
||||
|
||||
void riscv_fill_dm_read(struct target *target, char *buf, uint64_t a)
|
||||
void riscv_fill_dmi_read(struct target *target, char *buf, uint64_t a)
|
||||
{
|
||||
RISCV_INFO(r);
|
||||
r->fill_dm_read(target, buf, a);
|
||||
r->fill_dmi_read(target, buf, a);
|
||||
}
|
||||
|
||||
void riscv_fill_dm_nop(struct target *target, char *buf)
|
||||
|
|
|
|||
|
|
@ -226,8 +226,8 @@ struct riscv_info {
|
|||
int (*execute_progbuf)(struct target *target, uint32_t *cmderr);
|
||||
int (*invalidate_cached_progbuf)(struct target *target);
|
||||
int (*get_dmi_scan_length)(struct target *target);
|
||||
void (*fill_dm_write)(struct target *target, char *buf, uint64_t a, uint32_t d);
|
||||
void (*fill_dm_read)(struct target *target, char *buf, uint64_t a);
|
||||
void (*fill_dmi_write)(struct target *target, char *buf, uint64_t a, uint32_t d);
|
||||
void (*fill_dmi_read)(struct target *target, char *buf, uint64_t a);
|
||||
void (*fill_dm_nop)(struct target *target, char *buf);
|
||||
|
||||
int (*authdata_read)(struct target *target, uint32_t *value, unsigned int index);
|
||||
|
|
@ -408,8 +408,8 @@ int riscv_write_progbuf(struct target *target, int index, riscv_insn_t insn);
|
|||
int riscv_execute_progbuf(struct target *target, uint32_t *cmderr);
|
||||
|
||||
void riscv_fill_dm_nop(struct target *target, char *buf);
|
||||
void riscv_fill_dm_write(struct target *target, char *buf, uint64_t a, uint32_t d);
|
||||
void riscv_fill_dm_read(struct target *target, char *buf, uint64_t a);
|
||||
void riscv_fill_dmi_write(struct target *target, char *buf, uint64_t a, uint32_t d);
|
||||
void riscv_fill_dmi_read(struct target *target, char *buf, uint64_t a);
|
||||
int riscv_get_dmi_scan_length(struct target *target);
|
||||
|
||||
uint32_t riscv_get_dmi_address(const struct target *target, uint32_t dm_address);
|
||||
|
|
|
|||
Loading…
Reference in New Issue