target/riscv: remove duplicate progbufsize field
* removed `progbuf_size` field from `riscv_info`; added getter * moved `impebreak` field from `riscv_info` to `riscv013_info` as implementation dependent field; added getter Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
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8ea44aa381
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@ -183,8 +183,8 @@ int riscv_program_ebreak(struct riscv_program *p)
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{
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struct target *target = p->target;
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RISCV_INFO(r);
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if (p->instruction_count == riscv_progbuf_size(p->target) &&
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r->impebreak) {
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if (p->instruction_count == riscv_progbuf_size(target) &&
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r->get_impebreak(target)) {
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return ERROR_OK;
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}
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return riscv_program_insert(p, ebreak());
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@ -2356,6 +2356,16 @@ static int riscv011_authdata_write(struct target *target, uint32_t value, unsign
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return ERROR_OK;
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}
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static bool riscv011_get_impebreak(const struct target *target)
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{
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return false;
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}
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static unsigned int riscv011_get_progbufsize(const struct target *target)
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{
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return 0;
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}
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static int init_target(struct command_context *cmd_ctx,
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struct target *target)
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{
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@ -2365,6 +2375,8 @@ static int init_target(struct command_context *cmd_ctx,
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generic_info->authdata_read = &riscv011_authdata_read;
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generic_info->authdata_write = &riscv011_authdata_write;
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generic_info->print_info = &riscv011_print_info;
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generic_info->get_impebreak = &riscv011_get_impebreak;
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generic_info->get_progbufsize = &riscv011_get_progbufsize;
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generic_info->version_specific = calloc(1, sizeof(riscv011_info_t));
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if (!generic_info->version_specific)
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@ -67,6 +67,8 @@ static int read_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
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static int write_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer);
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static bool riscv013_get_impebreak(const struct target *target);
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static unsigned int riscv013_get_progbufsize(const struct target *target);
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typedef enum {
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HALT_GROUP,
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@ -153,7 +155,9 @@ typedef struct {
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/* Number of abstract command data registers. */
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unsigned datacount;
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/* Number of words in the Program Buffer. */
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unsigned progbufsize;
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unsigned int progbufsize;
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/* Hart contains an implicit ebreak at the end of the program buffer. */
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bool impebreak;
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/* We cache the read-only bits of sbcs here. */
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uint32_t sbcs;
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@ -1310,9 +1314,7 @@ static unsigned int register_size(struct target *target, enum gdb_regno number)
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static bool has_sufficient_progbuf(struct target *target, unsigned size)
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{
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RISCV013_INFO(info);
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RISCV_INFO(r);
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return info->progbufsize + r->impebreak >= size;
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return info->progbufsize + info->impebreak >= size;
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}
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/**
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@ -2037,14 +2039,13 @@ static int examine(struct target *target)
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LOG_TARGET_INFO(target, "datacount=%d progbufsize=%d",
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info->datacount, info->progbufsize);
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RISCV_INFO(r);
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r->impebreak = get_field(dmstatus, DM_DMSTATUS_IMPEBREAK);
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info->impebreak = get_field(dmstatus, DM_DMSTATUS_IMPEBREAK);
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if (!has_sufficient_progbuf(target, 2)) {
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LOG_TARGET_WARNING(target, "We won't be able to execute fence instructions on this "
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"target. Memory may not always appear consistent. "
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"(progbufsize=%d, impebreak=%d)", info->progbufsize,
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r->impebreak);
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info->impebreak);
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}
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if (info->progbufsize < 4 && riscv_enable_virtual) {
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@ -2060,6 +2061,8 @@ static int examine(struct target *target)
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enum riscv_hart_state state_at_examine_start;
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if (riscv_get_hart_state(target, &state_at_examine_start) != ERROR_OK)
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return ERROR_FAIL;
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RISCV_INFO(r);
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const bool hart_halted_at_examine_start = state_at_examine_start == RISCV_STATE_HALTED;
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if (!hart_halted_at_examine_start) {
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r->prepped = true;
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@ -2073,10 +2076,6 @@ static int examine(struct target *target)
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target->state = TARGET_HALTED;
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target->debug_reason = hart_halted_at_examine_start ? DBG_REASON_UNDEFINED : DBG_REASON_DBGRQ;
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/* Without knowing anything else we can at least mess with the
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* program buffer. */
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r->progbuf_size = info->progbufsize;
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result = riscv013_reg_examine_all(target);
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if (result != ERROR_OK)
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return result;
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@ -2817,6 +2816,8 @@ static int init_target(struct command_context *cmd_ctx,
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generic_info->read_memory = read_memory;
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generic_info->data_bits = &riscv013_data_bits;
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generic_info->print_info = &riscv013_print_info;
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generic_info->get_impebreak = &riscv013_get_impebreak;
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generic_info->get_progbufsize = &riscv013_get_progbufsize;
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generic_info->handle_became_unavailable = &handle_became_unavailable;
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generic_info->tick = &tick;
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@ -4872,6 +4873,18 @@ static int write_memory(struct target *target, target_addr_t address,
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return ret;
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}
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static bool riscv013_get_impebreak(const struct target *target)
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{
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RISCV013_INFO(r);
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return r->impebreak;
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}
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static unsigned int riscv013_get_progbufsize(const struct target *target)
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{
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RISCV013_INFO(r);
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return r->progbufsize;
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}
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static int arch_state(struct target *target)
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{
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return ERROR_OK;
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@ -5569,7 +5569,7 @@ static enum riscv_halt_reason riscv_halt_reason(struct target *target)
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size_t riscv_progbuf_size(struct target *target)
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{
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RISCV_INFO(r);
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return r->progbuf_size;
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return r->get_progbufsize(target);
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}
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int riscv_write_progbuf(struct target *target, int index, riscv_insn_t insn)
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@ -167,12 +167,6 @@ struct riscv_info {
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* most recent halt was not caused by a trigger, then this is -1. */
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int64_t trigger_hit;
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/* The number of entries in the program buffer. */
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int progbuf_size;
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/* This hart contains an implicit ebreak at the end of the program buffer. */
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bool impebreak;
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bool triggers_enumerated;
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/* Decremented every scan, and when it reaches 0 we clear the learned
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@ -236,6 +230,9 @@ struct riscv_info {
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int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address);
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int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
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bool (*get_impebreak)(const struct target *target);
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unsigned int (*get_progbufsize)(const struct target *target);
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/* Get the DMI address of target's DM's register.
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* The function should return the passed address
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* if the target is not assigned a DM yet.
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