Code cleanup: "slot_t" is unused in riscv013 - remove it.
Change-Id: I9d5a0cf8446a180b1d13a9ce2c86d904b946cf28
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Conflict in src/rtos/FreeRTOS.c due to
fbea7d5d38 -- resolved by replacing
`target->type->name` with a call to `target_type_name()`.
Change-Id: I56702c6133894458903de7a4d764903004aa8b86
hide_csrs should not emit warnings on an attempt to hide non-exitents CSR.
hide_csrs funcitonality is intended to be used for scenarios when we don`t
want certain groups of registers to be available in GDB. Typically this is
needed to simplify integration with various IDE. In such scenarious it may
be impractical/unfeseable to figure out which register is present on a
target. So reporting a situation when a user wants to hide a non-existent
register creates way too much noise. This commit reduces severity of
relevant debug message to LOG_TARGET_DEBUG
Before this patch the following behavior is observed on targets that do
not support hit bit:
```
bp 0x80000004 4 hw
resume 0x80000000
riscv.cpu halted due to watchpoint
```
This happens because the current implementation relies on the presence
of hit bit way too much. While working on this patch few defects in
hit bit-based trigger detection were discovered, added appropriate
TODOs.
Few files include target_type.h even if it is not needed.
Drop the include.
Other files access directly to target type's name instead of using
the proper API target_type_name().
Use the API and drop the include.
Change-Id: I86c0e0bbad51db93500c0efa27b7d6f1a67a02c2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8260
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Do not free the service in 'connection_closed_handler' because it is
free'd by the server infrastructure.
Checkpatch-ignore: COMMIT_LOG_LONG_LINE
This error was detected with valgrind:
==272468== Invalid free() / delete / delete[] / realloc()
==272468== at 0x484B27F: free (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so)
==272468== by 0x1F34C7: remove_service (server.c:374)
==272468== by 0x2ED3D5: semihosting_tcp_close_cnx (semihosting_common.c:1819)
==272468== by 0x2ED3D5: handle_common_semihosting_redirect_command (semihosting_common.c:1926)
==272468== by 0x1FC703: exec_command (command.c:520)
==272468== by 0x1FC703: jim_command_dispatch (command.c:931)
==272468== by 0x36980F: JimInvokeCommand (in /home/marc/openocd/build/src/openocd)
==272468== by 0x1FFFFFFFFF: ???
==272468== by 0x53ED09F: ???
==272468== by 0x300000001: ???
==272468== by 0x1FFEFFF7FF: ???
==272468== by 0x3D3984: ??? (in /home/marc/openocd/build/src/openocd)
==272468== by 0x2: ???
==272468== Address 0x5fff650 is 0 bytes inside a block of size 24 free'd
==272468== at 0x484B27F: free (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so)
==272468== by 0x2ECA42: semihosting_service_connection_closed_handler (semihosting_common.c:1807)
==272468== by 0x1F2E39: remove_connection.isra.0 (server.c:164)
==272468== by 0x1F349E: remove_connections (server.c:350)
==272468== by 0x1F349E: remove_service (server.c:364)
==272468== by 0x2ED3D5: semihosting_tcp_close_cnx (semihosting_common.c:1819)
==272468== by 0x2ED3D5: handle_common_semihosting_redirect_command (semihosting_common.c:1926)
==272468== by 0x1FC703: exec_command (command.c:520)
==272468== by 0x1FC703: jim_command_dispatch (command.c:931)
==272468== by 0x36980F: JimInvokeCommand (in /home/marc/openocd/build/src/openocd)
==272468== by 0x1FFFFFFFFF: ???
==272468== by 0x53ED09F: ???
==272468== by 0x300000001: ???
==272468== by 0x1FFEFFF7FF: ???
==272468== by 0x3D3984: ??? (in /home/marc/openocd/build/src/openocd)
==272468== Block was alloc'd at
==272468== at 0x484DA83: calloc (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so)
==272468== by 0x2ED326: handle_common_semihosting_redirect_command (semihosting_common.c:1931)
==272468== by 0x1FC703: exec_command (command.c:520)
==272468== by 0x1FC703: jim_command_dispatch (command.c:931)
==272468== by 0x36980F: JimInvokeCommand (in /home/marc/openocd/build/src/openocd)
==272468== by 0x1FFFFFFFFF: ???
==272468== by 0x53ED09F: ???
==272468== by 0x400000002: ???
==272468== by 0x1FFEFFF7FF: ???
==272468== by 0x3D3984: ??? (in /home/marc/openocd/build/src/openocd)
==272468== by 0x2: ???
==272468==
Change-Id: I3e5323f145a98d1ff9ea7d03f87ed96140f49a18
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8257
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Currently, errors in pre/post-enable events are ignored and capturing is
always started, even if necessary device configuration fails. This
behaviour is confusing to users. Also, the TPIU must be disabled before
re-configuration is possible.
Start capturing and enable TPIU only if no errors in pre/post-enable
events occurred.
Change-Id: I422033e36ca006e38aa4504d491b7947def1237a
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8254
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
When external capturing is configured (default), the SWO pin frequency
is required. Enforce this to avoid a division by zero error.
While at it, ensure that the 'out_filename' variable always contains a
valid string. This saves a few checks and makes the code more clean and
readable.
Change-Id: If8c1dae9549dd10e2f21d5b896414d47edac9fc2
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8224
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This would elliminate the need for an extra nop in-between the two reads
in case of a 64-bit register.
Change-Id: I2cddc14f7f78181bbda5f931c4e2289cfb7a6674
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
There was an error introduced by
8319eee9e1.
According to RISC-V Debug Spec 1.0.0-rc1 [3.14.2. Debug Module Contro]:
> 0 (inactive): The module’s state, including authentication mechanism,
takes its reset values (the dmactive bit is the only bit which can be
written to something other than its reset value).
`dmactive` was written together with `hartsel` and `hasel` in
8319eee9e1.
Change-Id: I11fba35cb87f8261c0a4a45e28b2813a5a086078
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
For MPU configs, determine memory access rights
by probing protection TLB. Issuing IHI without execute
permissions can trigger an exception.
No new clang static analyzer warnings.
Change-Id: Iea8eab5c2113df3f954285c3b9a79e96d41aa941
Signed-off-by: Ian Thompson <ianst@cadence.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8080
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Historically, the function cortex_a_dap_write_memap_register_u32()
was used to discriminate the register write in APB-AP CPU debug
against the complex memory access in AHB-AP memory bus.
It has no sense to keep the function and its comment.
Plus, by forcing atomic write it impacts the debug performance.
Drop it!
A further rework to enqueue sequence of atomic writes is needed.
Change-Id: I2f5e9015f0e27fa5a6d8337a1ae25e753e2e1d26
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8231
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
The command 'cache auto' was introduced with commit cd440bd32a
("add armv7a_cache handlers") in 2015 to allow disabling the cache
handling done automatically by OpenOCD.
This was probably a way to test the cache handling when there were
still the two independent accesses for APB-AP CPU debug and for
AHB-AP memory bus.
The handling of cache for cortex_a is robust and there is no more
reason to disable it.
The command 'cache auto' is not used in any upstream script.
On target aarch64 this command has never been introduced as the
cache is always handled automatically by OpenOCD.
Drop the command 'cache auto' and add it in the deprecated list.
Drop the flag 'auto_cache_enabled' by considering it as true.
Rename the function 'armv7a_cache_auto_flush_all_data()' as
'armv7a_cache_flush_all_data()' and, while there, fix the error
propagation in SMP case.
Change-Id: I0399f1081b08c4929e0795b76f4a686630f41d56
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8230
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
The initial OpenOCD code for Cortex-A (ARMv7a) [1] was merged in
2009 but, due to lack of public documentation for ARMv7a, it was
almost a simple copy/paste from the existing code for Cortex-M
(ARMv7m).
On Cortex-M the same AP provides access to both CPU debug and CPU
memory. This feature is not present on ARMv7a.
To still keep some communality with ARMv7m code, the change [2]
splits the CPU debug access from the CPU memory access by using
two independent AP; this is copied from the system architecture of
TI OMAP3530 which provides to DAP a direct AHB-AP memory bus on
AP#0, separated from AP#1 for the APB-AP CPU debug.
But the direct memory access through the system bus breaks the
coherency between memory and CPU caches, so change [3] added some
cache invalidation to avoid issues.
The code to allow ARMv7a CPU to really read/write in CPU memory
was added by change [4] in 2011. Such still not optimized
implementation was very slow, so it did not replace the access
through the system bus. A selection through DAP's 'apsel" command
was used to select between the two modes.
Only in 2015, with change [5], the speed of CPU read/write was
improved using the DCC_FAST_MODE. But the direct access to the
memory through the system bus remained.
Finally, with change [6] in 2018 the system bus access was dropped
for good, as the new virtual target "mem_ap" could implement such
access in a more clean way.
Only memory access through CPU remained for ARMv7a.
Nevertheless, a useless cache invalidation remained in the code,
decreasing the speed of the write access.
Drop the useless cache invalidate on CPU memory write and the
associated comment, not anymore valid.
Drop the now unused function armv7a_cache_auto_flush_on_write().
This provides a speedup of between 4 and 8, depending on adapter
and JTAG/SWD speed.
Link: [1] 7a93100c2d ("Add minimalist Cortex A8 file")
Link: [2] 1d0b276c9f ("The rest of the Cortex-A8 support from Magnus: ...")
Link: [3] d4e4d65d28 ("Cache invalidation when writing to memory")
Link: [4] 05ab8bdb81 ("cortex_a9: implement read/write memory through APB-AP")
Link: [5] 0228f8e827 ("Cortex A: fix extra memory read and non-word sizes")
Link: [6] fac9be64d9 ("target/cortex_a: remove buggy memory AP accesses")
Change-Id: Ifa3c7ddf2698b2c87037fb48f783844034a7140e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8229
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
The gdb subsystem is initialized after the first target examine,
so the field struct target::gdb_service is NULL during examine.
A command "smp off" in the examine event handler causes a SIGSEGV
during OpenOCD startup.
Check for pointer not NULL before dereferencing it.
Change-Id: Id115e28be23a957fef1b97ab66d7273f0ea0dce4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8216
Tested-by: jenkins
The code for cortex_a allocates the register cache during the very
first examine of the target.
To prevent a segmentation fault in assert_reset(), the call to
register_cache_invalidate() is guarded by target_was_examined().
But for targets with -defer-examine, the target is set as not
examined in handle_target_reset() just before entering in
assert_reset().
This causes registers to not be invalidated while reset a target
examined but with -defer-examine.
Change the condition and invalidate the register cache if it has
been already allocated.
Change-Id: I81ae782ddce07431d5f2c1bea3e2f19dfcd6d1ce
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8215
Tested-by: jenkins
The code for aarch64 allocates the register cache during the very
first examine of the target.
To prevent a segmentation fault in assert_reset(), the call to
register_cache_invalidate() is guarded by target_was_examined().
But for targets with -defer-examine, the target is set as not
examined in handle_target_reset() just before entering in
assert_reset().
This causes registers to not be invalidated while reset a target
examined but with -defer-examine.
Change the condition and invalidate the register cache if it has
been already allocated.
Change-Id: Ie13abb0ae2cc28fc3295d678c4ad1691024eb7b8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8214
Tested-by: jenkins
Prevent a segmentation fault by preventing to try to halt a target
that has not been examined yet.
Change-Id: I5d344e7fbdb5422f7c5e2c39bdd48cbc6c2a3e58
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8213
Tested-by: jenkins
Commit 16b4b8cf54 ("Cortex-M3: expose most DWT registers") added
the DWT registers to the list of CPU registers.
The commit message from 2009 reports the reason behind this odd
mixing of CPU and DWT registers.
This feature got broken in 2017 with the introduction of the field
struct reg::exist and its further use in the code. As result, the
command 'reg' on a target Cortex-M reports only the core registers
and then the header line
===== Cortex-M DWT registers
not anymore followed by the DWT registers.
Fix it by tagging each DWT registers as existing.
Change-Id: Iab026e7da8d6b8ba052514c3fd3b5cdfe301f330
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: b5964191f0 ("register: support non-existent registers")
Reviewed-on: https://review.openocd.org/c/openocd/+/8198
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
For GDB to fully support hardware watchpoints, OpenOCD needs to tell GDB
which data address has been hit. OpenOCD relies on a target-specific
hit_watchpoint function to do this. If GDB is not given the address, it
will not print the hit variable name or its old and new value.
There does not seem to be a way for the hardware to tell us which
trigger
was hit (0.13 introduced the 'hit bit' but this is optional).
Alternatively,
we can decode the instruction at dpc and find out which memory address
it accesses.
This commit adds support for RVC (compressed) load and store
instructions.
Related to:
https://github.com/riscv-collab/riscv-openocd/issues/688https://github.com/riscv-collab/riscv-openocd/pull/291
This commit is related to testing how OpenOCD responds to `dmi.busy`.
Consider testing on Spike (e.g. `riscv-tests/debug` testsuite). Spike
returns `dmi.busy` if there were less then a given number of RTI cycles
(`required_rti_cycles`) between DR_UPDATE and DR_CAPTURE:
https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/jtag_dtm.cc#L145https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/jtag_dtm.cc#L202
`required_rti_cycles` gets it's value from `--dmi-rti` CLI argument and
is constant throughout the run.
OpenOCD learns this required number of RTI cycles by starting with zero
and increasing it if `dmi.busy` is encountered. So the required number
of RTI cycles is learned during the first DMI access in the `examine()`.
To induce `dmi.busy` on demand `riscv reset_delays <x>` command is
provided. This command initializes `riscv_info::reset_delays_wait`
counter to the provided `<x>` value. The counter is decreased before a
DMI access and when it reaches zero the learned value of RTI cycles
required is reset, so the DMI access results in `dmi.busy`.
Now consider running a batch of accesses. Before the change all the
accesses in the batch had the same number of RIT cycles in between them.
So either:
* Number of accesses in the batch was greater then the value of
`riscv_info::reset_delays_wait` counter and there was no `dmi.busy`
throughout the batch.
* Number of accesses in the batch was less or equal then the value of
`riscv_info::reset_delays_wait` counter and the first access of the
batch resulted in `dmi.busy`.
Therefore it was impossible to encounter `dmi.busy` on any scan of the
batch except the first one.
Change-Id: Ib0714ecaf7d2e11878140d16d9aa6152ff20f1e9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Recently, (after b503fdef02) OpenOCD started to notify user about hart
state updates. This causes confusion in some cases since some internal
updates to the hart state should not be visible to the user as these are
implementation details. For example situation like this:
```
> reset halt
JTAG tap: riscv.tap tap/device found: 0xdeadbeef ...
> resume
[riscv.cpu0] Found 4 triggers
riscv.cpu0 halted due to single-step.
[riscv.cpu1] Found 4 triggers
riscv.cpu1 halted due to single-step.
[riscv.cpu2] Found 4 triggers
riscv.cpu2 halted due to single-step.
[riscv.cpu3] Found 4 triggers
riscv.cpu3 halted due to single-step.
```
likely confuse people.
There is no issue with the resume functionality. It`s just that
resume internally causes single-step that causes hart state
to change.
This commit disable calling of user-specified (and default)
callbacks during the "hidden" step operation disabling these
confusing messages
Change-Id: I3412a089e2abdcd315d86cec7ee732fdd18c1601
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Prior to the commit, pc was cached at `info->dpc`, but dpc at register
cache.
Change-Id: I369788441dbe21bcf8fc360d2e97e98096b25e3a
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
`reg` is a number in register cache, as evident by the following call to
`reg_cache_set()`. `CSR_DCSR` is `GDB_REGNO_DCSR - 65`. This results in
setting cache value for another register, which does not exist, and
causes a segfault if all non-existent registers are not allocated a
value (`reg->value == NULL`).
Change-Id: Iab68a4bb55ce6d4730804e9709e40ab2af8a07c6
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This allows to merge the implementation in `batch.c` with the one in
`riscv-013.c`.
Change-Id: Ic3821a9ce2d75a7c6e618074679595ddefb14cfc
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
According to the RISC-V Debug Spec (1.0.0-rc1)[3.7 Abstract Commands]:
> While an abstract command is executing (busy in abstractcs is high), a
debugger must not change hartsel, and must not write 1 to haltreq,
resumereq, ackhavereset, setresethaltreq, or clrresethaltreq.
The patch ensures the rule is followed.
Change-Id: Id7d363d9fdeb365181b7058e0ceb0be0df39654f
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This allows to examine each DM ones (e.g. enumerating harts assigned to
the DM). Additionaly, it is guaranteed that the DM is reset before the
examination.
Change-Id: I2333d06ff1152bf51c647d59baa55cb402054cb9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
According to the RISC-V Debug Spec (1.0.0-rc1)[3.7 Abstract Commands]:
> While an abstract command is executing (busy in abstractcs is high), a
debugger must not change hartsel, and must not write 1 to haltreq,
resumereq, ackhavereset, setresethaltreq, or clrresethaltreq.
Tracking `abstractcs.busy` allows to enforce this rule.
Change-Id: If5975b48cf9fd379033268145c79103c36fb8134
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Initialized `value` variables that could only be set in a branch.
Change-Id: Iec7413ade9d053c93352a58ff954ad49a6545923
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8179
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Move setting of do_reconnect flag from swd_run_inner()
to swd_run(). Reconnect is not used at the inner level
and the flag had to be cleared after swd_run_inner()
to prevent recursion.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Ib1de80bbdf10d1cbfb1dd351c6a5658e50d12af2
Reviewed-on: https://review.openocd.org/c/openocd/+/8155
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The file 'list.h', copied from FreeBSD, does not depend from any
OpenOCD specific include file, but only needs 'stddef.h' for the
type 'size_t'.
Let 'list.h' to include the correct header file, then fix the now
broken dependencies in the other files that were incorrectly
relying on 'list.h' to include 'helper/types.h'
Change-Id: Idd31b5bf607e226cac44ef41b2aa335ae4dbf519
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8173
Tested-by: jenkins
The logic in `init_registers()` was quite convoluted.
Initialization of each `struct reg` field is separated into function
`gdb_regno_<field_name>()`.
IMHO, this makes it much easier to reason about the code.
Change-Id: Id7faa1464ce026cc5025585d0a6a95a01fb39cee
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Add access to fpr and cp1 registers.
GDB can now check the FPRs with `info reg f` and change them.
Checkpatch-ignore: MACRO_ARG_REUSE
Change-Id: I63896ab6f6737054d8108db105a13a58e1446fbc
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7866
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Extend the existing code to support Monitor mode in AArch32.
Change-Id: Ia43df98d1497baac48aea67b92d81344c24f0635
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8169
Tested-by: jenkins
ADIv6 brought more complicated rules for DP reg 0 banking.
Neither the original implementation [1] nor the later
modification [2] respected that the DP reg 0 is banked
for read only, not for write. Enforcing of an useless
SELECT write before a write to ABORT register may trigger
FAULT (CTRL/STAT bits ORUNDETECT and STICKYORUN are set)
or WAIT (DP is stalled by an outstanding previous operation)
and therefore make ABORT register virtually unusable
on some adapters (bitbang, CMSIS-DAP).
There are DP ABORT specific functions swd_queue_ap_abort()
and swd_clear_sticky_errors() which worked around the problem
using the lowest level swd->write_reg(). Using a specific
write procedure for a single DP register was error prone
(there are other DP_ABORT writes using swd_queue_dp_write_inner())
and also the Tcl command 'xx.dap dpreg 0 value' suffered
from unwanted SELECT write.
Other smaller discords in DP banking probably do not
influence normal DP operation however they may complicate
debugging in corner cases.
Adhere strictly to the DP banking rules for both ADI versions.
Fixes: [1] commit 72fb88613f ("adiv6: add low level swd transport")
Fixes: [2] commit ee3fb5a0ea ("target/arm_adi_v5: fix DP SELECT logic")
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I3328748c1c3e0661c5ecd6eb070ac519b190ace2
Reviewed-on: https://review.openocd.org/c/openocd/+/8154
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Allow direct pointer to struct adiv5_private_config
for targets with adiv5_private_config inside of a bigger
private config container. Use it instead of the private_config
pointer toggling hack in aarch64.c
Allow optional use of -dap parameter and use it instead
of the static variable hack in xtensa_chip.c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I7260c79332940adfa49d57b45cae39325cdaf432
Reviewed-on: https://review.openocd.org/c/openocd/+/8138
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add access to dsp registers and a command for dsp related operations.
Checkpatch-ignore: MACRO_ARG_REUSE
Change-Id: I30aec0b9e4984896965edb1663f74216ad41101e
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7867
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
After commit d9b2607ca0 ("gdb_server: support sparse register
maps"), GDB crashes while requesting the value of 'cpsr' because
the fake register is tagged as not existing.
Change the logic and set all register as existing, while still
limiting the list for the initial GDB request at connect.
Change-Id: I1c4e274c06147683db2a59a8920ae5ccd863e15c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8163
Tested-by: jenkins
For the sake of https://review.openocd.org/c/openocd/+/7957
Instead of "coreid", 'target smp' command call order used as
an index
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Iab86b81868d37c0bf8663707ee11367c41f6b96d
Reviewed-on: https://review.openocd.org/c/openocd/+/8162
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
find members of a union, nested in struct.
Allows file to be compiled with GCC 4.0
Signed-off-by: Sevan Janiyan <venture37@geeklan.co.uk>
Change-Id: Ied68668d3b5f811573a20e11e83aceff268963eb
Reviewed-on: https://review.openocd.org/c/openocd/+/8120
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Allows build with legacy toolchains which do not support
C23 nor GCC extension for binary literals.
Change-Id: I742d3a8a86bf16f81421d11c59d3cb155ee17aed
Signed-off-by: Sevan Janiyan <venture37@geeklan.co.uk>
Reviewed-on: https://review.openocd.org/c/openocd/+/8123
Tested-by: jenkins
Reviewed-by: Jörg Wunsch <openocd@uriah.heep.sax.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add more debug messages connected with triggers.
Update names for internal flags to make them more clarified.
Change-Id: I5642346ce4a1e9bf79b22cdbf36bd757a7beffa8
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
Fix obsoleted references to Cortex-M3 from the time
when M3 was the only supported Cortex.
Fix typo.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I6f93265f1b9328fec063fecd819210deb28aaf2c
Reviewed-on: https://review.openocd.org/c/openocd/+/8099
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In 2008 the commit 1829361253 ("define resetting
the target into the halted or running state as an atomic operation.")
introduced the target_halt() call to the end of cortex_m3_assert_reset(),
Checkpatch-ignore: GIT_COMMIT_ID
A year later the commit ed36a8d15d
("... Updated halt handling for cortex_m3")
prevented cortex_m3_halt() take any action in case of TARGET_RESET state.
This narrowed the target_halt() called from cortex_m3_assert_reset()
to setting target->halt_issued and storing a time stamp.
Introducing ocd_process_reset(_inner) made the setting of halt_issued
and halt_issued_time useless. The Tcl function waits for halt
of all targets if applicable.
cortex_m_halt() and also target_halt() does not work as expected
if the cached target state is TARGET_RESET (although the core could
be out of reset and ready to be halted, just have not been polled).
Explicit Tcl arp_poll must be issued in many scenarios.
Remove the useless hack.
Also remove the explicit error return from cortex_m_halt_one()
in case of RESET_SRST_PULLS_TRST and asserted srst. If the communication
with the target is gated by any reset, cortex_m_write_debug_halt_mask()
fails. Propagate the error return of this call instead.
Change-Id: I0da05b87f43c3d0facb78e54d8f00c1728fe7c46
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8098
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In a corner case when debug_ap is not available,
cortex_m_assert_reset() asserts reset to restore
communication with the target.
Prevent to do so on targets with defer_examine,
as such targets need some special handling to enable them
after reset anyway.
The change makes possible to handle a multicore Cortex-M SoC with
an auxiliary Cortex-M core(s) switched of by default
even with 'reset_config srst_gates_jtag'
Change-Id: I8cec7a816423e588d5e2e4f7904c81c776eddc42
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8097
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Function riscv_program_exec() contains code for restoring
of register values after progbuf execution. This code is
not used anymore by current OpenOCD, and hence removed.
Related discussion can be found under:
https://github.com/riscv/riscv-openocd/issues/982
Change-Id: I4c79bec081522b6fc0d16367cef51ed19a131962
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Fixes:
- Data types of address & data parameters in riscv_batch_add_*()
and riscv*_fill_dm*() changed to uint64_t and uint32_t.
- Corrected the comparison in riscv_batch_full().
- Corrected assertions in riscv_batch_get_dmi_read_op()
and riscv_batch_get_dmi_read_data().
Cleanup:
- Simplified calloc() fail handling in riscv_batch_alloc().
- Added explicit NULL assignments in riscv_batch_alloc()
for clarity and readability. Don't rely on calloc().
- Removed suffix `_u64` from riscv_*_fill_dm*() since it
does not have any meaning.
- Renamed *dmi_write_u64_bits() to *get_dmi_scan_length()
which better describes its purpose.
Change-Id: Id70e5968528d64b2ee5476f1c00e08459a1e291d
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Cleanup, non-functional changes:
- Replaced one call of low-level function dm_op()
by high-level dm_read().
- Made sure that truncation of values passed to dm_*
is explicit. (Added explicit casts.)
Change-Id: I1d1b2f29a822b6841373f3313de2b1e96f514116
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
If targets are in a halt group, and a target in the group reaches a
breakpoint, the target's state was able to remain `TARGET_RUNNING`.
Addresses issue #1010
Change-Id: I734bc6da71d289c4d05b417c8bf67a7d1a56574f
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
clang build triggers an error for an uninitialized value of the
variable 'instr'.
This is a false positive, as the macro
#define MIPS32_CONFIG3_ISA_MASK (3 << MIPS32_CONFIG3_ISA_SHIFT)
guarantees the switch/case already covers all the possible values
with cases 0, 1, 2 and 3.
Silent clang by adding a useless default case to the switch.
While there, fix the indentation of the switch/case accordingly to
OpenOCD coding style.
Change-Id: I0ae316754ce7d091dd8366bf314b8e6ee780e313
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 7de4b1202d ("target/mips32: add cpu info detection")
Reviewed-on: https://review.openocd.org/c/openocd/+/8065
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Commit e370e06b72 ("target: Deprecate 'array2mem' and
'mem2array''") has already replaced the deprecated root versions
of commands mem2array and array2mem with TCL proc's that use
'read_memory' and 'write_memory'. It has left the deprecated code
of the target's version of the commands because the effort to code
the TCL replacement was not considered valuable.
To drop the last jim_handler commands, I consider much easier and
less error-prone to code them in TCL instead of converting the
deprecated code to COMMAND_HANDLER.
Drop the code in target.c and extend the TCL proc's.
While there, add the TCL procs to _telnet_autocomplete_skip.
Change-Id: I97d2370d8af479434ddf5af68541f90913982bc0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8052
Tested-by: jenkins
When requested by the core code (handle_breakpoints = true),
arc_resume() should be able to advance over a potential breakpoint set
at the resume address instead of getting stuck in one place. This is
achieved by removing the breakpoint, executing one instruction,
resetting the breakpoint, then proceeding forward as normal.
With this patch applied, openocd is now able to resume from a
breakpoint halt when debugging ARCv2 targets via telnet.
This has previously been committed to the Zephyr project's openocd repo
(see https://github.com/zephyrproject-rtos/openocd/pull/31).
Change-Id: I17dba0dcea311d394b303c587bc2dfaa99d67859
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7817
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Presently, we rely on gdb to restore break/watchpoints upon resuming
execution in arc_resume(). To match this behavior in absence of gdb
(more specifically, when handle_breakpoints is true), this patch
explicitly re-enables all breakpoints and watchpoints in arc_resume().
This has previously been committed to the Zephyr project's openocd repo
(see https://github.com/zephyrproject-rtos/openocd/pull/31).
Change-Id: I59e9c91270ef0b5fd19cfc570663dc67a6022dbd
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7816
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
For Armv8.1-M based cores, detect if the core implements the optional
M-profile vector extension (MVE), using MVFR1 register.
While at there rework armv7m->fp_feature detection based on MVFR0
and MVFR1 registers.
Change-Id: I92d5b1759aea9f7561d285f46acdec51d6efb7b4
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6950
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The target esirisc does not free the allocated memory resources,
causing memory leaks at OpenOCD exit.
Add esirisc_free_reg_cache() and esirisc_deinit_target() and use
them to free all the allocated resources.
Change-Id: I17b8ebff54906fa25a37f2d96c01d010a98cffbd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8094
Tested-by: jenkins
Reviewed-by: Steven Stallion <sstallion@gmail.com>
The function in question does not need to change target state. It is a
target-type-dependant function, however, IMHO, it is safe to assume that
any target type would not need to change type-independant state of a
target to figure out the arch.
Change-Id: I607cb3aee6529cd5a97bc1200a0226cf6ef43caf
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8093
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
There are quite a lot of "getters" in target interface.
They do not change target structure, nevertheless the structure is
passed to these functions via a plain pointer.
The intention is to clarify the purpouse of these functions by passing
the `target` structure as a pointer to constant data.
Change-Id: Ida4a798da94938753b86a293a308d93b091d1bf3
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8092
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This reverts commits 2e920a212f and
8dbb1250f5.
The reason is, after `openocd_is_shutdown_pending()` becomes true,
arbitrary command may be executed:
* In `target_destroy()` and the corresponding
`target->type->deinit_target()`.
* In user-specifyed `pre_shutdown_commands` list.
Change-Id: Icd00d1d954cd45e255880a6f76c3a74c098d6a17
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
The reason for the change is a conflict: `dcsr[5]` is `dcsr.v` in
current spec, but it is `dcsr.debugint` in 0.11. This causes `priv`
register to be read incorrectly.
Change-Id: If2d8fdcd8536afa4c7149c453101b00ce0df1ce0
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
There was an error in `dm_read`/`dm_write`: DMI address was checked
against DM registers disregarding DM base address.
To solve the issue `dmi_address()` function was introduced.
Change-Id: Ia3be619417b5f5b53db5dfe302db05170d6787c9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
The motivalion for the change:
* `riscv_hart_count()` is used only once to print the value into the log
during exmination.
* The returned value is a bit confusing: it's not the total number of
targets on the TAP. It is the number of targets accessable through the
same DM. So the name of the function is misleading.
* This value is already reported on `-d3` level.
So the function seems redundant and can be safely removed.
Change-Id: Iac9021af59ba8dba2cfb6b9dd15eebc98fe42a08
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
The function is used for commands:
- jtag configure
- jtag cget
While there, add the missing .usage field.
Change-Id: I97ddc4898259ddb7fd2d057a997f33a6f4b0e2a8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8058
Tested-by: jenkins
clang build triggers an error for an uninitialized value of the
variable 'instr'.
This is a false positive, as the macro
#define MIPS32_CONFIG3_ISA_MASK (3 << MIPS32_CONFIG3_ISA_SHIFT)
guarantees the switch/case already covers all the possible values
with cases 0, 1, 2 and 3.
Silent clang by adding a useless default case to the switch.
While there, fix the indentation of the switch/case accordingly to
OpenOCD coding style.
Change-Id: I0ae316754ce7d091dd8366bf314b8e6ee780e313
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 7de4b1202d ("target/mips32: add cpu info detection")
Reviewed-on: https://review.openocd.org/c/openocd/+/8065
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Commit e370e06b72 ("target: Deprecate 'array2mem' and
'mem2array''") has already replaced the deprecated root versions
of commands mem2array and array2mem with TCL proc's that use
'read_memory' and 'write_memory'. It has left the deprecated code
of the target's version of the commands because the effort to code
the TCL replacement was not considered valuable.
To drop the last jim_handler commands, I consider much easier and
less error-prone to code them in TCL instead of converting the
deprecated code to COMMAND_HANDLER.
Drop the code in target.c and extend the TCL proc's.
While there, add the TCL procs to _telnet_autocomplete_skip.
Change-Id: I97d2370d8af479434ddf5af68541f90913982bc0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8052
Tested-by: jenkins
When requested by the core code (handle_breakpoints = true),
arc_resume() should be able to advance over a potential breakpoint set
at the resume address instead of getting stuck in one place. This is
achieved by removing the breakpoint, executing one instruction,
resetting the breakpoint, then proceeding forward as normal.
With this patch applied, openocd is now able to resume from a
breakpoint halt when debugging ARCv2 targets via telnet.
This has previously been committed to the Zephyr project's openocd repo
(see https://github.com/zephyrproject-rtos/openocd/pull/31).
Change-Id: I17dba0dcea311d394b303c587bc2dfaa99d67859
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7817
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Presently, we rely on gdb to restore break/watchpoints upon resuming
execution in arc_resume(). To match this behavior in absence of gdb
(more specifically, when handle_breakpoints is true), this patch
explicitly re-enables all breakpoints and watchpoints in arc_resume().
This has previously been committed to the Zephyr project's openocd repo
(see https://github.com/zephyrproject-rtos/openocd/pull/31).
Change-Id: I59e9c91270ef0b5fd19cfc570663dc67a6022dbd
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7816
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
For Armv8.1-M based cores, detect if the core implements the optional
M-profile vector extension (MVE), using MVFR1 register.
While at there rework armv7m->fp_feature detection based on MVFR0
and MVFR1 registers.
Change-Id: I92d5b1759aea9f7561d285f46acdec51d6efb7b4
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6950
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
In loops that typically take longer time to complete, check if there is
a pending shutdown request. If so, terminate the loop.
This allows to respond to a signal requesting a shutdown during some
loops which do not return control to main OpenOCD loop.
Change-Id: Iace0b58eddde1237832d0f9333a7c7b930565674
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Based on Daniel Goehring's [1] and Peter Collingbourne's [2] work.
Probe for support of 8, 16 bit and if the large data extension is available
also probe for 64, 128 and 256 bit operations.
Probe for the ability of packing 8 and 16 bit data
(formerly probed in mem_ap_init()). The probe is integrated to
mem_ap_read/write() routines and takes place just before the first memory
access of the specific size.
Add 64, 128 and 256 bit MEM-AP read/writes.
Introduce specific error codes for unsupported transfer size
and for unsupported packing.
Change-Id: I180c4ef17d2fc3189e8e2f14bafd22d857f29608
Link: 7191: target/adiv5: add MEM-AP 64-bit access support | https://review.openocd.org/c/openocd/+/7191
Link: 7436: arm_adi_v5: Support reads wider than 32 bits | https://review.openocd.org/c/openocd/+/7436
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7576
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Prevent packed writes with Nuvoton NPCX quirks because the workaround
uses all byte lanes for one byte or halfword and thus precludes packing.
Eliminate quirk code for size 4 as it is equivalent to the common code.
Make the quirk code for sizes 2 and 1 easier readable.
Change-Id: I72324e56a49b4712bd3769e03dce01427d9fcd73
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7575
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Introduce ti_be_lane_xor for byte lane correction
and use common code for both quirk and regular conversion.
The same lane correction takes place in both mem_ap_read/write()
- it was obfuscated in original code with different bitwise and arithmetic
operations.
Change-Id: I6a30672b908770323d30813a714e06ab8695fe26
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7574
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Update mips32 instructions, add barrier and sync related insts.
Add SYNC and barrier instruction blocks for memory access safety.
These instructions are not supported on Lexra and/or MIPSr1 CPUs,
detections were added and they will be executed conditionally.
Rework mips32_pracc_read/write_regs function.
Checkpatch-ignore: MACRO_ARG_REUSE
Change-Id: Ib14112f37ff1f060b1633df73d671a6b09bb2178
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7865
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add detection for mips cpu types by using prid.
Add cpuinfo command for inspecting more verbose info.
Add MIPS Architecture specs in openocd docs.
Change-Id: I28573b7c51783628db986bad0e226dcc399b4fa6
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7912
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Some devices with an internal multi-tap JTAG router require a vendor
specific bypass instruction to bypass the master TAP when addressing
slave taps internal to the same device. On these devices the standard
bypass instruction bypasses the whole device.
Change-Id: I4506f0e67c9e4dfe39b7fa18c63d67900313e594
Signed-off-by: Henrik Nordström <henrik.nordstrom@addiva.se>
Reviewed-on: https://review.openocd.org/c/openocd/+/8041
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
swd_connect_multidrop() sent DORMANT_TO_SWD and called
swd_multidrop_select_inner(). DORMANT_TO_SWD sequence ends
with a LINE_RESET sequence.
swd_multidrop_select_inner() sent LINE_RESET sequence again.
It was useless in this case.
swd_connect_multidrop() emited JTAG_TO_DORMANT and DORMANT_TO_SWD
sequences before connecting each DAP in SWD multidrop bus.
It is sufficient to emit JTAG_TO_DORMANT and DORMANT_TO_SWD
just once and emit the shorter LINE_RESET instead for subsequent DAPs.
Introduce a global variable swd_multidrop_in_swd_state
and use it to control what sequence is emitted.
In case of reconnect after an error, always use the full switch
JTAG_TO_DORMANT and DORMANT_TO_SWD.
Change-Id: Iba21620f6a9680793208bf398960ed0eb59df3b1
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7218
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
SWD multidrop requires some initialization once before connecting
all daps. Provide an optional pre-connect dap operation.
Change-Id: I778215c512c56423a425dda80ab19a739f22f285
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7542
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The original code supported ADIv5 only, just one SELECT register
with some reserved bits - the pseudo value DP_SELECT_INVALID was
just fine to indicate the DP SELECT register is in an unknown state.
Added ADIv6 support required DP SELECT and SELECT1 registers
without reserved bits. Therefore DP_SELECT_INVALID value became
reachable as a (fortunately not really used) ADIv6 AP ADDR.
JTAG DPBANKSEL setting support introduced with ADIv6 does not
honor DP_SELECT_INVALID correctly: required select value
gets compared to DP_SELECT_INVALID value and the most common zero
bank does not trigger DP SELECT write.
DP banked registers need just to set DP SELECT. ADIv6 AP register
addressing scheme may use both DP SELECT and SELECT1. This further
complicates using a single invalid value.
Moreover the difference how the SWD line reset influences
DPBANKSEL field between ADIv5 and ADIv6 deserves better handling
than setting select cache to zero and then to DP_SELECT_INVALID
in a very specific code positions.
Introduce bool flags indicating the validity of each SELECT
register and one SWD specific for DPBANKSEL field.
Use the latter to prevent selecting DP BANK before taking
the connection out of reset by reading DPIDR.
Treat DP SELECT and SELECT1 individually in ADIv6 64-bit mode.
Update comments to reflect the difference between ADIv5 and ADIv6
in SWD line reset.
Change-Id: Ibbb0b06cb592be072571218b666566a13d8dff0e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7541
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In loops that typically take longer time to complete, check if there is
a pending shutdown request. If so, terminate the loop.
This allows to respond to a signal requesting a shutdown during some
loops which do not return control to main OpenOCD loop.
Change-Id: Iace0b58eddde1237832d0f9333a7c7b930565674
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8032
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
While at it, fix some coding style issues.
Change-Id: I8196045f46ce043ed0d28cb95470132b3a7de1bb
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8039
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The field backup_working_area is always used as a boolean value.
Use bool type for backup_working_area.
Change-Id: I55c68d717dbbe9e5caf60fd1db368527c6d1b995
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8036
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
I don't think there are any real bugs here, but at least this gives us a
clean slate moving forward.
Change-Id: I29c6c398c28dfe580f9a2deb3bdbcfc491a2ceb6
Signed-off-by: Tim Newsome <tim@sifive.com>
These messages helps to clarify current status of examination process
Change-Id: I5d93903c4680deed2c1bf707d8f7ef0b48ffdc9a
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8013
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This functionality can be useful for;
1-ESP flashing code to load flasher stub on target and
write/read/erase flash.
2-ESP GCOV command uses some of these functions to run
onboard routines to dump coverage info.
This is high level api for the Espressif xtensa and riscv targets
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I5e618b960bb6566ee618d4ba261f51af97a7cb0e
Reviewed-on: https://review.openocd.org/c/openocd/+/7759
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The goal of this commit is to provide more robust error handling in
`write_memory_progbuf()`. This is achieved by rewriting it in a fashion
similar to `read_memory_progbuf()`.
The motivation is: some instability in `load_image` was encountered. No
stable reproduction could be obtained, so the root cause was not
determined. Therefore, it was decided to clean-up the code, that may be
implicated in such failures.
Examples of unhanded errors in the code prior to this commit:
* Most of `dmi_write()` return values are discarded.
* If `dm_read()` on `abstractcs` failed (line 4546), `abstractauto` was
not cleared.
Furthermore, the structure of the code was quite complicated, which made
it hard to analyze and reason whether or not all possible failures are
handled properly.
Change-Id: I8a100b686e594855fbf34acf5ccf0e1550f18869
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Anatoly Parshintsev
Jan Matyas
Evgeniy Naydanov
Parshintsev Anatoly
Evgeniy Naydanov
Antonio Borneo
Marc Schink
Ian Thompson
Aleksey Lotosh
Walter Ji
Emmanuel Blot
Tomas Vanek
Erhan Kurubas
Sevan Janiyan
Kirill Radkin
Jan Matyas
Evgeniy Didin
Tarek BOCHKATI
Henrik Nordström
Peter Collingbourne
Tim Newsome
Karl Palsson