Merge up to 9659a9b5e2 from upstream
Change-Id: I2fda9689d3465b3d8c8f3459b1ed954cb1d70fdc
This commit is contained in:
Evgeniy Naydanov
commit
16e7adbd9c
|
|
@ -0,0 +1,189 @@
|
|||
Valid-License-Identifier: Apache-2.0
|
||||
SPDX-URL: https://spdx.org/licenses/Apache-2.0.html
|
||||
Usage-Guide:
|
||||
Do NOT use on OpenOCD code. The Apache-2.0 is not GPL2 compatible. It may only
|
||||
be used for dual-licensed files where the other license is GPL2 compatible.
|
||||
If you end up using this it MUST be used together with a GPL2 compatible
|
||||
license using "OR".
|
||||
It may also be used for stand-alone code NOT linked within the OpenOCD binary
|
||||
but distributed with OpenOCD.
|
||||
To use the Apache License version 2.0 put the following SPDX tag/value
|
||||
pair into a comment according to the placement guidelines in the
|
||||
licensing rules documentation:
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
License-Text:
|
||||
|
||||
Apache License
|
||||
|
||||
Version 2.0, January 2004
|
||||
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
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||||
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||||
1. Definitions.
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"License" shall mean the terms and conditions for use, reproduction, and
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END OF TERMS AND CONDITIONS
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@ -72,6 +72,7 @@ EXTRA_DIST += \
|
|||
LICENSES/preferred/GPL-2.0 \
|
||||
LICENSES/preferred/LGPL-2.1 \
|
||||
LICENSES/preferred/MIT \
|
||||
LICENSES/stand-alone/Apache-2.0 \
|
||||
LICENSES/stand-alone/GPL-3.0 \
|
||||
tools/logger.pl \
|
||||
tools/rlink_make_speed_table \
|
||||
|
|
|
|||
|
|
@ -1,4 +1,13 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
/*
|
||||
* The original version of this file did not reported any license nor
|
||||
* copyright, but the author clearly stated that:
|
||||
* "This file should be linked along with the [uC/OS-III user's] project
|
||||
* to enable RTOS support for uC/OS-III."
|
||||
* Such statement implies the willing to have this file's license compatible
|
||||
* with the license Apache 2.0 of uC/OS-III.
|
||||
*/
|
||||
|
||||
/*
|
||||
* uC/OS-III does not provide a fixed layout for OS_TCB, which makes it
|
||||
|
|
|
|||
|
|
@ -168,7 +168,7 @@ static int angie_load_firmware_and_renumerate(struct angie *device, const char *
|
|||
static int angie_load_firmware(struct angie *device, const char *filename);
|
||||
static int angie_load_bitstream(struct angie *device, const char *filename);
|
||||
static int angie_i2c_write(struct angie *device, uint8_t *i2c_data, uint8_t i2c_data_size);
|
||||
static void angie_io_extender_config(struct angie *device, uint8_t i2c_adr, uint8_t cfg_value, uint8_t value);
|
||||
static int angie_io_extender_config(struct angie *device, uint8_t i2c_adr, uint8_t cfg_value);
|
||||
static int angie_write_firmware_section(struct angie *device,
|
||||
struct image *firmware_image, int section_index);
|
||||
|
||||
|
|
@ -262,8 +262,10 @@ static int angie_usb_open(struct angie *device)
|
|||
|
||||
int ret = jtag_libusb_open(vids, pids, NULL, &usb_device_handle, NULL);
|
||||
|
||||
if (ret != ERROR_OK)
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Could not find and open ANGIE");
|
||||
return ret;
|
||||
}
|
||||
|
||||
device->usb_device_handle = usb_device_handle;
|
||||
device->type = ANGIE;
|
||||
|
|
@ -281,8 +283,10 @@ static int angie_usb_open(struct angie *device)
|
|||
static int angie_usb_close(struct angie *device)
|
||||
{
|
||||
if (device->usb_device_handle) {
|
||||
if (libusb_release_interface(device->usb_device_handle, 0) != 0)
|
||||
if (libusb_release_interface(device->usb_device_handle, 0) != 0) {
|
||||
LOG_ERROR("Could not release interface 0");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
jtag_libusb_close(device->usb_device_handle);
|
||||
device->usb_device_handle = NULL;
|
||||
|
|
@ -383,8 +387,10 @@ static int angie_load_firmware(struct angie *device, const char *filename)
|
|||
/* Download all sections in the image to ANGIE */
|
||||
for (unsigned int i = 0; i < angie_firmware_image.num_sections; i++) {
|
||||
ret = angie_write_firmware_section(device, &angie_firmware_image, i);
|
||||
if (ret != ERROR_OK)
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Could not write firmware section");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
image_close(&angie_firmware_image);
|
||||
|
|
@ -477,7 +483,7 @@ static int angie_load_bitstream(struct angie *device, const char *filename)
|
|||
ret = jtag_libusb_control_transfer(device->usb_device_handle,
|
||||
0x00, 0xB1, 0, 0, NULL, 0, LIBUSB_TIMEOUT_MS, &transferred);
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_INFO("error cfgclose");
|
||||
LOG_ERROR("Failed cfgclose");
|
||||
/* Abort if libusb sent less data than requested */
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
|
@ -509,12 +515,10 @@ static int angie_i2c_write(struct angie *device, uint8_t *i2c_data, uint8_t i2c_
|
|||
i2c_data_size + 2, 1000, &transferred);
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Error in i2c clock gen configuration : ret ERROR");
|
||||
angie_quit();
|
||||
return ret;
|
||||
}
|
||||
if (transferred != i2c_data_size + 2) {
|
||||
LOG_ERROR("Error in i2c clock gen configuration : bytes transferred");
|
||||
angie_quit();
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
|
|
@ -524,7 +528,6 @@ static int angie_i2c_write(struct angie *device, uint8_t *i2c_data, uint8_t i2c_
|
|||
ret = jtag_libusb_bulk_write(device->usb_device_handle, 0x88, buffer_received, 1, 1000, &transferred);
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Error in i2c clock gen configuration : ret ERROR");
|
||||
angie_quit();
|
||||
return ret;
|
||||
}
|
||||
return ERROR_OK;
|
||||
|
|
@ -541,13 +544,15 @@ static int angie_i2c_write(struct angie *device, uint8_t *i2c_data, uint8_t i2c_
|
|||
* @return on success: ERROR_OK
|
||||
* @return on failure: ERROR_FAIL
|
||||
*/
|
||||
static void angie_io_extender_config(struct angie *device, uint8_t i2c_adr, uint8_t cfg_value, uint8_t value)
|
||||
static int angie_io_extender_config(struct angie *device, uint8_t i2c_adr, uint8_t cfg_value)
|
||||
{
|
||||
uint8_t ioconfig[3] = {i2c_adr, 3, cfg_value};
|
||||
angie_i2c_write(device, ioconfig, 3);
|
||||
uint8_t iovalue[3] = {i2c_adr, 1, value};
|
||||
angie_i2c_write(device, iovalue, 3);
|
||||
int ret = angie_i2c_write(device, ioconfig, 3);
|
||||
if (ret != ERROR_OK)
|
||||
return ret;
|
||||
|
||||
usleep(500);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -851,19 +856,27 @@ static int angie_execute_queued_commands(struct angie *device, int timeout_ms)
|
|||
/* Send packet to ANGIE */
|
||||
ret = jtag_libusb_bulk_write(device->usb_device_handle, device->ep_out,
|
||||
(char *)buffer, count_out, timeout_ms, &transferred);
|
||||
if (ret != ERROR_OK)
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Libusb bulk write queued commands failed.");
|
||||
return ret;
|
||||
if (transferred != count_out)
|
||||
}
|
||||
if (transferred != count_out) {
|
||||
LOG_ERROR("Libusb bulk write queued commands failed: transferred byte count");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
/* Wait for response if commands contain IN payload data */
|
||||
if (count_in > 0) {
|
||||
ret = jtag_libusb_bulk_write(device->usb_device_handle, device->ep_in,
|
||||
(char *)buffer, count_in, timeout_ms, &transferred);
|
||||
if (ret != ERROR_OK)
|
||||
return ret;
|
||||
if (transferred != count_in)
|
||||
return ERROR_FAIL;
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Libusb bulk write input payload data failed");
|
||||
return ret;
|
||||
}
|
||||
if (transferred != count_in) {
|
||||
LOG_ERROR("Libusb bulk write input payload data failed: transferred byte count");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
/* Write back IN payload data */
|
||||
index_in = 0;
|
||||
|
|
@ -2230,7 +2243,6 @@ static int angie_init(void)
|
|||
|
||||
ret = angie_usb_open(angie_handle);
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Could not open ANGIE device");
|
||||
free(angie_handle);
|
||||
angie_handle = NULL;
|
||||
return ret;
|
||||
|
|
@ -2249,10 +2261,10 @@ static int angie_init(void)
|
|||
|
||||
if (download_firmware) {
|
||||
LOG_INFO("Loading ANGIE firmware. This is reversible by power-cycling ANGIE device.");
|
||||
|
||||
if (libusb_claim_interface(angie_handle->usb_device_handle, 0) != LIBUSB_SUCCESS)
|
||||
LOG_ERROR("Could not claim interface");
|
||||
|
||||
if (libusb_claim_interface(angie_handle->usb_device_handle, 0) != LIBUSB_SUCCESS) {
|
||||
LOG_ERROR("Could not claim interface 0");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
ret = angie_load_firmware_and_renumerate(angie_handle,
|
||||
ANGIE_FIRMWARE_FILE, ANGIE_RENUMERATION_DELAY_US);
|
||||
if (ret != ERROR_OK) {
|
||||
|
|
@ -2266,45 +2278,29 @@ static int angie_init(void)
|
|||
angie_quit();
|
||||
return ret;
|
||||
}
|
||||
if (libusb_claim_interface(angie_handle->usb_device_handle, 1) != LIBUSB_SUCCESS) {
|
||||
LOG_ERROR("Could not claim interface 1");
|
||||
angie_quit();
|
||||
if (libusb_release_interface(angie_handle->usb_device_handle, 0) != LIBUSB_SUCCESS) {
|
||||
LOG_ERROR("Fail release interface 0");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
angie_io_extender_config(angie_handle, 0x22, 0xFF, 0xFF);
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Could not configure io extender 22");
|
||||
angie_quit();
|
||||
return ret;
|
||||
if (libusb_claim_interface(angie_handle->usb_device_handle, 1) != LIBUSB_SUCCESS) {
|
||||
LOG_ERROR("Could not claim interface 1");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
angie_io_extender_config(angie_handle, 0x23, 0xFF, 0xFF);
|
||||
/* Configure io extender 23: all input */
|
||||
ret = angie_io_extender_config(angie_handle, 0x23, 0xFF);
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Could not configure io extender 23");
|
||||
angie_quit();
|
||||
return ret;
|
||||
}
|
||||
angie_io_extender_config(angie_handle, 0x24, 0x1F, 0x9F);
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Could not configure io extender 24");
|
||||
angie_quit();
|
||||
return ret;
|
||||
}
|
||||
angie_io_extender_config(angie_handle, 0x25, 0x07, 0x00);
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Could not configure io extender 25");
|
||||
angie_quit();
|
||||
return ret;
|
||||
}
|
||||
if (libusb_release_interface(angie_handle->usb_device_handle, 1) != LIBUSB_SUCCESS) {
|
||||
LOG_ERROR("Fail release interface 1");
|
||||
angie_quit();
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
} else {
|
||||
LOG_INFO("ANGIE device is already running ANGIE firmware");
|
||||
}
|
||||
|
||||
/* Get ANGIE USB IN/OUT endpoints and claim the interface */
|
||||
/* Get ANGIE USB IN/OUT endpoints and claim the interface 0 */
|
||||
ret = jtag_libusb_choose_interface(angie_handle->usb_device_handle,
|
||||
&angie_handle->ep_in, &angie_handle->ep_out, 0xFF, 0, 0, -1);
|
||||
if (ret != ERROR_OK) {
|
||||
|
|
@ -2319,6 +2315,7 @@ static int angie_init(void)
|
|||
/* Issue one test command with short timeout */
|
||||
ret = angie_append_test_cmd(angie_handle);
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Append test command failed.");
|
||||
angie_quit();
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -2345,14 +2342,16 @@ static int angie_init(void)
|
|||
|
||||
angie_clear_queue(angie_handle);
|
||||
|
||||
/* Execute get signals command */
|
||||
ret = angie_append_get_signals_cmd(angie_handle);
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Append get signals command failed");
|
||||
angie_quit();
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = angie_execute_queued_commands(angie_handle, 200);
|
||||
if (ret != ERROR_OK) {
|
||||
LOG_ERROR("Execute get signals command failed");
|
||||
angie_quit();
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -362,7 +362,7 @@ static int cmsis_dap_usb_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p
|
|||
if (err)
|
||||
LOG_WARNING("could not claim interface: %s", libusb_strerror(err));
|
||||
|
||||
dap->bdata = malloc(sizeof(struct cmsis_dap_backend_data));
|
||||
dap->bdata = calloc(1, sizeof(struct cmsis_dap_backend_data));
|
||||
if (!dap->bdata) {
|
||||
LOG_ERROR("unable to allocate memory");
|
||||
libusb_release_interface(dev_handle, interface_num);
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@
|
|||
#include "helper/log.h"
|
||||
#include "helper/list.h"
|
||||
|
||||
#define VD_VERSION 46
|
||||
#define VD_VERSION 48
|
||||
#define VD_BUFFER_LEN 4024
|
||||
#define VD_CHEADER_LEN 24
|
||||
#define VD_SHEADER_LEN 16
|
||||
|
|
@ -66,7 +66,8 @@
|
|||
* @brief List of transactor types
|
||||
*/
|
||||
enum {
|
||||
VD_BFM_JTDP = 0x0001, /* transactor DAP JTAG DP */
|
||||
VD_BFM_TPIU = 0x0000, /* transactor trace TPIU */
|
||||
VD_BFM_DAP6 = 0x0001, /* transactor DAP ADI V6 */
|
||||
VD_BFM_SWDP = 0x0002, /* transactor DAP SWD DP */
|
||||
VD_BFM_AHB = 0x0003, /* transactor AMBA AHB */
|
||||
VD_BFM_APB = 0x0004, /* transactor AMBA APB */
|
||||
|
|
@ -253,6 +254,11 @@ static int vdebug_socket_open(char *server_addr, uint32_t port)
|
|||
hsock = socket(AF_INET, SOCK_STREAM, IPPROTO_IP);
|
||||
if (hsock == INVALID_SOCKET)
|
||||
rc = vdebug_socket_error();
|
||||
#elif defined __CYGWIN__
|
||||
/* SO_RCVLOWAT unsupported on CYGWIN */
|
||||
hsock = socket(AF_INET, SOCK_STREAM, IPPROTO_IP);
|
||||
if (hsock < 0)
|
||||
rc = errno;
|
||||
#else
|
||||
uint32_t rcvwat = VD_SHEADER_LEN; /* size of the rcv header, as rcv min watermark */
|
||||
hsock = socket(AF_INET, SOCK_STREAM, IPPROTO_IP);
|
||||
|
|
@ -462,14 +468,14 @@ static int vdebug_run_reg_queue(int hsock, struct vd_shm *pm, unsigned int count
|
|||
for (unsigned int j = 0; j < num; j++)
|
||||
memcpy(&data[j * awidth], &pm->rd8[(rwords + j) * awidth], awidth);
|
||||
}
|
||||
LOG_DEBUG_IO("read %04x AS:%02x RG:%02x O:%05x @%03x D:%08x", le_to_h_u16(pm->wid) - count + req,
|
||||
aspace, addr, (vdc.trans_first << 14) | (vdc.trans_last << 15), waddr,
|
||||
LOG_DEBUG("read %04x AS:%1x RG:%1x O:%05x @%03x D:%08x", le_to_h_u16(pm->wid) - count + req,
|
||||
aspace, addr << 2, (vdc.trans_first << 14) | (vdc.trans_last << 15), waddr,
|
||||
(num ? le_to_h_u32(&pm->rd8[rwords * 4]) : 0xdead));
|
||||
rwords += num * wwidth;
|
||||
waddr += sizeof(uint64_t) / 4; /* waddr past header */
|
||||
} else {
|
||||
LOG_DEBUG_IO("write %04x AS:%02x RG:%02x O:%05x @%03x D:%08x", le_to_h_u16(pm->wid) - count + req,
|
||||
aspace, addr, (vdc.trans_first << 14) | (vdc.trans_last << 15), waddr,
|
||||
LOG_DEBUG("write %04x AS:%1x RG:%1x O:%05x @%03x D:%08x", le_to_h_u16(pm->wid) - count + req,
|
||||
aspace, addr << 2, (vdc.trans_first << 14) | (vdc.trans_last << 15), waddr,
|
||||
le_to_h_u32(&pm->wd8[(waddr + num + 1) * 4]));
|
||||
waddr += sizeof(uint64_t) / 4 + (num * wwidth * awidth + 3) / 4;
|
||||
}
|
||||
|
|
@ -513,7 +519,7 @@ static int vdebug_open(int hsock, struct vd_shm *pm, const char *path,
|
|||
rc = VD_ERR_VERSION;
|
||||
} else {
|
||||
pm->cmd = VD_CMD_CONNECT;
|
||||
pm->type = type; /* BFM type to connect to, here JTAG */
|
||||
pm->type = type; /* BFM type to connect to */
|
||||
h_u32_to_le(pm->rwdata, sig_mask | VD_SIG_BUF | (VD_SIG_BUF << 16));
|
||||
h_u16_to_le(pm->wbytes, strlen(path) + 1);
|
||||
h_u16_to_le(pm->rbytes, 12);
|
||||
|
|
@ -917,7 +923,7 @@ static int vdebug_reset(int trst, int srst)
|
|||
|
||||
static int vdebug_jtag_tms_seq(const uint8_t *tms, int num, uint8_t f_flush)
|
||||
{
|
||||
LOG_INFO("tms len:%d tms:%x", num, *tms);
|
||||
LOG_DEBUG_IO("tms len:%d tms:%x", num, *tms);
|
||||
|
||||
return vdebug_jtag_shift_tap(vdc.hsocket, pbuf, num, *tms, 0, NULL, 0, 0, NULL, f_flush);
|
||||
}
|
||||
|
|
@ -925,7 +931,7 @@ static int vdebug_jtag_tms_seq(const uint8_t *tms, int num, uint8_t f_flush)
|
|||
static int vdebug_jtag_path_move(struct pathmove_command *cmd, uint8_t f_flush)
|
||||
{
|
||||
uint8_t tms[DIV_ROUND_UP(cmd->num_states, 8)];
|
||||
LOG_INFO("path num states %d", cmd->num_states);
|
||||
LOG_DEBUG_IO("path num states %d", cmd->num_states);
|
||||
|
||||
memset(tms, 0, DIV_ROUND_UP(cmd->num_states, 8));
|
||||
|
||||
|
|
@ -945,7 +951,7 @@ static int vdebug_jtag_tlr(tap_state_t state, uint8_t f_flush)
|
|||
tap_state_t cur = tap_get_state();
|
||||
uint8_t tms_pre = tap_get_tms_path(cur, state);
|
||||
uint8_t num_pre = tap_get_tms_path_len(cur, state);
|
||||
LOG_INFO("tlr from %x to %x", cur, state);
|
||||
LOG_DEBUG_IO("tlr from %x to %x", cur, state);
|
||||
if (cur != state) {
|
||||
rc = vdebug_jtag_shift_tap(vdc.hsocket, pbuf, num_pre, tms_pre, 0, NULL, 0, 0, NULL, f_flush);
|
||||
tap_set_state(state);
|
||||
|
|
@ -965,7 +971,7 @@ static int vdebug_jtag_scan(struct scan_command *cmd, uint8_t f_flush)
|
|||
uint8_t tms_post = tap_get_tms_path(state, cmd->end_state);
|
||||
uint8_t num_post = tap_get_tms_path_len(state, cmd->end_state);
|
||||
int num_bits = jtag_scan_size(cmd);
|
||||
LOG_DEBUG("scan len:%d fields:%d ir/!dr:%d state cur:%x end:%x",
|
||||
LOG_DEBUG_IO("scan len:%d fields:%d ir/!dr:%d state cur:%x end:%x",
|
||||
num_bits, cmd->num_fields, cmd->ir_scan, cur, cmd->end_state);
|
||||
for (int i = 0; i < cmd->num_fields; i++) {
|
||||
uint8_t cur_num_pre = i == 0 ? num_pre : 0;
|
||||
|
|
@ -991,7 +997,7 @@ static int vdebug_jtag_runtest(int cycles, tap_state_t state, uint8_t f_flush)
|
|||
tap_state_t cur = tap_get_state();
|
||||
uint8_t tms_pre = tap_get_tms_path(cur, state);
|
||||
uint8_t num_pre = tap_get_tms_path_len(cur, state);
|
||||
LOG_DEBUG("idle len:%d state cur:%x end:%x", cycles, cur, state);
|
||||
LOG_DEBUG_IO("idle len:%d state cur:%x end:%x", cycles, cur, state);
|
||||
int rc = vdebug_jtag_shift_tap(vdc.hsocket, pbuf, num_pre, tms_pre, cycles, NULL, 0, 0, NULL, f_flush);
|
||||
if (cur != state)
|
||||
tap_set_state(state);
|
||||
|
|
@ -1001,7 +1007,7 @@ static int vdebug_jtag_runtest(int cycles, tap_state_t state, uint8_t f_flush)
|
|||
|
||||
static int vdebug_jtag_stableclocks(int num, uint8_t f_flush)
|
||||
{
|
||||
LOG_INFO("stab len:%d state cur:%x", num, tap_get_state());
|
||||
LOG_DEBUG("stab len:%d state cur:%x", num, tap_get_state());
|
||||
|
||||
return vdebug_jtag_shift_tap(vdc.hsocket, pbuf, 0, 0, num, NULL, 0, 0, NULL, f_flush);
|
||||
}
|
||||
|
|
@ -1076,6 +1082,41 @@ static int vdebug_jtag_execute_queue(void)
|
|||
return rc;
|
||||
}
|
||||
|
||||
static int vdebug_dap_bankselect(struct adiv5_ap *ap, unsigned int reg)
|
||||
{
|
||||
int rc = ERROR_OK;
|
||||
uint64_t sel;
|
||||
|
||||
if (is_adiv6(ap->dap)) {
|
||||
sel = ap->ap_num | (reg & 0x00000FF0);
|
||||
if (sel != (ap->dap->select & ~0xfull)) {
|
||||
sel |= ap->dap->select & DP_SELECT_DPBANK;
|
||||
if (ap->dap->asize > 32)
|
||||
sel |= (DP_SELECT1 >> 4) & DP_SELECT_DPBANK;
|
||||
ap->dap->select = sel;
|
||||
ap->dap->select_valid = true;
|
||||
rc = vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, (uint32_t)sel, VD_ASPACE_DP, 0);
|
||||
if (rc == ERROR_OK) {
|
||||
ap->dap->select_valid = true;
|
||||
if (ap->dap->asize > 32)
|
||||
rc = vdebug_reg_write(vdc.hsocket, pbuf, (DP_SELECT1 & DP_SELECT_DPBANK) >> 2,
|
||||
(uint32_t)(sel >> 32), VD_ASPACE_DP, 0);
|
||||
if (rc == ERROR_OK)
|
||||
ap->dap->select1_valid = true;
|
||||
}
|
||||
}
|
||||
} else { /* ADIv5 */
|
||||
sel = (ap->ap_num << 24) | (reg & ADIV5_DP_SELECT_APBANK);
|
||||
if (sel != ap->dap->select) {
|
||||
ap->dap->select = sel;
|
||||
rc = vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, (uint32_t)sel, VD_ASPACE_DP, 0);
|
||||
if (rc == ERROR_OK)
|
||||
ap->dap->select_valid = true;
|
||||
}
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int vdebug_dap_connect(struct adiv5_dap *dap)
|
||||
{
|
||||
return dap_dp_init(dap);
|
||||
|
|
@ -1088,20 +1129,29 @@ static int vdebug_dap_send_sequence(struct adiv5_dap *dap, enum swd_special_seq
|
|||
|
||||
static int vdebug_dap_queue_dp_read(struct adiv5_dap *dap, unsigned int reg, uint32_t *data)
|
||||
{
|
||||
if (reg != DP_SELECT && reg != DP_RDBUFF
|
||||
&& (!dap->select_valid || ((reg >> 4) & DP_SELECT_DPBANK) != (dap->select & DP_SELECT_DPBANK))) {
|
||||
dap->select = (dap->select & ~DP_SELECT_DPBANK) | ((reg >> 4) & DP_SELECT_DPBANK);
|
||||
vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, dap->select, VD_ASPACE_DP, 0);
|
||||
dap->select_valid = true;
|
||||
}
|
||||
return vdebug_reg_read(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, data, VD_ASPACE_DP, 0);
|
||||
}
|
||||
|
||||
static int vdebug_dap_queue_dp_write(struct adiv5_dap *dap, unsigned int reg, uint32_t data)
|
||||
{
|
||||
if (reg != DP_SELECT && reg != DP_RDBUFF
|
||||
&& (!dap->select_valid || ((reg >> 4) & DP_SELECT_DPBANK) != (dap->select & DP_SELECT_DPBANK))) {
|
||||
dap->select = (dap->select & ~DP_SELECT_DPBANK) | ((reg >> 4) & DP_SELECT_DPBANK);
|
||||
vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, dap->select, VD_ASPACE_DP, 0);
|
||||
dap->select_valid = true;
|
||||
}
|
||||
return vdebug_reg_write(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, data, VD_ASPACE_DP, 0);
|
||||
}
|
||||
|
||||
static int vdebug_dap_queue_ap_read(struct adiv5_ap *ap, unsigned int reg, uint32_t *data)
|
||||
{
|
||||
if ((reg & ADIV5_DP_SELECT_APBANK) != ap->dap->select) {
|
||||
vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, reg & ADIV5_DP_SELECT_APBANK, VD_ASPACE_DP, 0);
|
||||
ap->dap->select = reg & ADIV5_DP_SELECT_APBANK;
|
||||
}
|
||||
vdebug_dap_bankselect(ap, reg);
|
||||
|
||||
vdebug_reg_read(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, NULL, VD_ASPACE_AP, 0);
|
||||
|
||||
|
|
@ -1110,11 +1160,7 @@ static int vdebug_dap_queue_ap_read(struct adiv5_ap *ap, unsigned int reg, uint3
|
|||
|
||||
static int vdebug_dap_queue_ap_write(struct adiv5_ap *ap, unsigned int reg, uint32_t data)
|
||||
{
|
||||
if ((reg & ADIV5_DP_SELECT_APBANK) != ap->dap->select) {
|
||||
vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, reg & ADIV5_DP_SELECT_APBANK, VD_ASPACE_DP, 0);
|
||||
ap->dap->select = reg & ADIV5_DP_SELECT_APBANK;
|
||||
}
|
||||
|
||||
vdebug_dap_bankselect(ap, reg);
|
||||
return vdebug_reg_write(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, data, VD_ASPACE_AP, 0);
|
||||
}
|
||||
|
||||
|
|
@ -1170,7 +1216,7 @@ COMMAND_HANDLER(vdebug_set_bfm)
|
|||
break;
|
||||
}
|
||||
if (transport_is_dapdirect_swd())
|
||||
vdc.bfm_type = VD_BFM_SWDP;
|
||||
vdc.bfm_type = strstr(vdc.bfm_path, "dap6") ? VD_BFM_DAP6 : VD_BFM_SWDP;
|
||||
else
|
||||
vdc.bfm_type = VD_BFM_JTAG;
|
||||
LOG_DEBUG("bfm_path: %s clk_period %ups", vdc.bfm_path, vdc.bfm_period);
|
||||
|
|
|
|||
|
|
@ -127,7 +127,8 @@ static const struct command_registration hl_transport_jtag_subcommand_handlers[]
|
|||
{
|
||||
.name = "cget",
|
||||
.mode = COMMAND_EXEC,
|
||||
.jim_handler = jim_jtag_configure,
|
||||
.handler = handle_jtag_configure,
|
||||
.usage = "",
|
||||
},
|
||||
{
|
||||
.name = "names",
|
||||
|
|
|
|||
197
src/jtag/tcl.c
197
src/jtag/tcl.c
|
|
@ -41,7 +41,7 @@
|
|||
* Holds support for accessing JTAG-specific mechanisms from TCl scripts.
|
||||
*/
|
||||
|
||||
static const struct jim_nvp nvp_jtag_tap_event[] = {
|
||||
static const struct nvp nvp_jtag_tap_event[] = {
|
||||
{ .value = JTAG_TRST_ASSERTED, .name = "post-reset" },
|
||||
{ .value = JTAG_TAP_EVENT_SETUP, .name = "setup" },
|
||||
{ .value = JTAG_TAP_EVENT_ENABLE, .name = "tap-enable" },
|
||||
|
|
@ -259,123 +259,104 @@ enum jtag_tap_cfg_param {
|
|||
JCFG_IDCODE,
|
||||
};
|
||||
|
||||
static struct jim_nvp nvp_config_opts[] = {
|
||||
static struct nvp nvp_config_opts[] = {
|
||||
{ .name = "-event", .value = JCFG_EVENT },
|
||||
{ .name = "-idcode", .value = JCFG_IDCODE },
|
||||
|
||||
{ .name = NULL, .value = -1 }
|
||||
};
|
||||
|
||||
static int jtag_tap_configure_event(struct jim_getopt_info *goi, struct jtag_tap *tap)
|
||||
static int jtag_tap_set_event(struct command_context *cmd_ctx, struct jtag_tap *tap,
|
||||
const struct nvp *event, Jim_Obj *body)
|
||||
{
|
||||
if (goi->argc == 0) {
|
||||
Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-event <event-name> ...");
|
||||
return JIM_ERR;
|
||||
}
|
||||
struct jtag_tap_event_action *jteap = tap->event_action;
|
||||
|
||||
struct jim_nvp *n;
|
||||
int e = jim_getopt_nvp(goi, nvp_jtag_tap_event, &n);
|
||||
if (e != JIM_OK) {
|
||||
jim_getopt_nvp_unknown(goi, nvp_jtag_tap_event, 1);
|
||||
return e;
|
||||
}
|
||||
|
||||
if (goi->isconfigure) {
|
||||
if (goi->argc != 1) {
|
||||
Jim_WrongNumArgs(goi->interp,
|
||||
goi->argc,
|
||||
goi->argv,
|
||||
"-event <event-name> <event-body>");
|
||||
return JIM_ERR;
|
||||
}
|
||||
} else {
|
||||
if (goi->argc != 0) {
|
||||
Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-event <event-name>");
|
||||
return JIM_ERR;
|
||||
}
|
||||
}
|
||||
|
||||
struct jtag_tap_event_action *jteap = tap->event_action;
|
||||
/* replace existing event body */
|
||||
bool found = false;
|
||||
while (jteap) {
|
||||
if (jteap->event == (enum jtag_event)n->value) {
|
||||
found = true;
|
||||
if (jteap->event == (enum jtag_event)event->value)
|
||||
break;
|
||||
}
|
||||
jteap = jteap->next;
|
||||
}
|
||||
|
||||
Jim_SetEmptyResult(goi->interp);
|
||||
|
||||
if (goi->isconfigure) {
|
||||
if (!found)
|
||||
jteap = calloc(1, sizeof(*jteap));
|
||||
else if (jteap->body)
|
||||
Jim_DecrRefCount(goi->interp, jteap->body);
|
||||
|
||||
jteap->interp = goi->interp;
|
||||
jteap->event = n->value;
|
||||
|
||||
Jim_Obj *o;
|
||||
jim_getopt_obj(goi, &o);
|
||||
jteap->body = Jim_DuplicateObj(goi->interp, o);
|
||||
Jim_IncrRefCount(jteap->body);
|
||||
|
||||
if (!found) {
|
||||
/* add to head of event list */
|
||||
jteap->next = tap->event_action;
|
||||
tap->event_action = jteap;
|
||||
if (!jteap) {
|
||||
jteap = calloc(1, sizeof(*jteap));
|
||||
if (!jteap) {
|
||||
LOG_ERROR("Out of memory");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
} else if (found) {
|
||||
jteap->interp = goi->interp;
|
||||
Jim_SetResult(goi->interp,
|
||||
Jim_DuplicateObj(goi->interp, jteap->body));
|
||||
|
||||
/* add to head of event list */
|
||||
jteap->next = tap->event_action;
|
||||
tap->event_action = jteap;
|
||||
} else {
|
||||
Jim_DecrRefCount(cmd_ctx->interp, jteap->body);
|
||||
}
|
||||
return JIM_OK;
|
||||
|
||||
jteap->interp = cmd_ctx->interp;
|
||||
jteap->event = (enum jtag_event)event->value;
|
||||
jteap->body = Jim_DuplicateObj(cmd_ctx->interp, body);
|
||||
Jim_IncrRefCount(jteap->body);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int jtag_tap_configure_cmd(struct jim_getopt_info *goi, struct jtag_tap *tap)
|
||||
__COMMAND_HANDLER(handle_jtag_configure)
|
||||
{
|
||||
/* parse config or cget options */
|
||||
while (goi->argc > 0) {
|
||||
Jim_SetEmptyResult(goi->interp);
|
||||
bool is_configure = !strcmp(CMD_NAME, "configure");
|
||||
|
||||
struct jim_nvp *n;
|
||||
int e = jim_getopt_nvp(goi, nvp_config_opts, &n);
|
||||
if (e != JIM_OK) {
|
||||
jim_getopt_nvp_unknown(goi, nvp_config_opts, 0);
|
||||
return e;
|
||||
}
|
||||
if (CMD_ARGC < (is_configure ? 3 : 2))
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
|
||||
/* FIXME: rework jtag_tap_by_jim_obj */
|
||||
struct jtag_tap *tap = jtag_tap_by_jim_obj(CMD_CTX->interp, CMD_JIMTCL_ARGV[0]);
|
||||
if (!tap)
|
||||
return ERROR_FAIL;
|
||||
|
||||
for (unsigned int i = 1; i < CMD_ARGC; i++) {
|
||||
const struct nvp *n = nvp_name2value(nvp_config_opts, CMD_ARGV[i]);
|
||||
switch (n->value) {
|
||||
case JCFG_EVENT:
|
||||
e = jtag_tap_configure_event(goi, tap);
|
||||
if (e != JIM_OK)
|
||||
return e;
|
||||
break;
|
||||
case JCFG_IDCODE:
|
||||
if (goi->isconfigure) {
|
||||
Jim_SetResultFormatted(goi->interp,
|
||||
"not settable: %s", n->name);
|
||||
return JIM_ERR;
|
||||
} else {
|
||||
if (goi->argc != 0) {
|
||||
Jim_WrongNumArgs(goi->interp,
|
||||
goi->argc, goi->argv,
|
||||
"NO PARAMS");
|
||||
return JIM_ERR;
|
||||
case JCFG_EVENT:
|
||||
if (i + (is_configure ? 3 : 2) >= CMD_ARGC) {
|
||||
command_print(CMD, "wrong # args: should be \"-event <event-name>%s\"",
|
||||
is_configure ? " <event-body>" : "");
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
|
||||
const struct nvp *event = nvp_name2value(nvp_jtag_tap_event, CMD_ARGV[i + 1]);
|
||||
if (!event->name) {
|
||||
nvp_unknown_command_print(CMD, nvp_jtag_tap_event, CMD_ARGV[i], CMD_ARGV[i + 1]);
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
|
||||
if (is_configure) {
|
||||
int retval = jtag_tap_set_event(CMD_CTX, tap, event, CMD_JIMTCL_ARGV[i + 2]);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
} else {
|
||||
struct jtag_tap_event_action *jteap = tap->event_action;
|
||||
while (jteap) {
|
||||
if (jteap->event == (enum jtag_event)event->value) {
|
||||
command_print(CMD, "%s", Jim_GetString(jteap->body, NULL));
|
||||
break;
|
||||
}
|
||||
jteap = jteap->next;
|
||||
}
|
||||
Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, tap->idcode));
|
||||
break;
|
||||
default:
|
||||
Jim_SetResultFormatted(goi->interp, "unknown value: %s", n->name);
|
||||
return JIM_ERR;
|
||||
}
|
||||
|
||||
i += is_configure ? 2 : 1;
|
||||
break;
|
||||
case JCFG_IDCODE:
|
||||
if (is_configure) {
|
||||
command_print(CMD, "not settable: %s", n->name);
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
command_print(CMD, "0x%08x", tap->idcode);
|
||||
break;
|
||||
default:
|
||||
nvp_unknown_command_print(CMD, nvp_config_opts, NULL, CMD_ARGV[i]);
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
}
|
||||
|
||||
return JIM_OK;
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
#define NTAP_OPT_IRLEN 0
|
||||
|
|
@ -558,7 +539,7 @@ static void jtag_tap_handle_event(struct jtag_tap *tap, enum jtag_event e)
|
|||
if (jteap->event != e)
|
||||
continue;
|
||||
|
||||
struct jim_nvp *nvp = jim_nvp_value2name_simple(nvp_jtag_tap_event, e);
|
||||
const struct nvp *nvp = nvp_value2name(nvp_jtag_tap_event, e);
|
||||
LOG_DEBUG("JTAG tap: %s event: %d (%s)\n\taction: %s",
|
||||
tap->dotted_name, e, nvp->name,
|
||||
Jim_GetString(jteap->body, NULL));
|
||||
|
|
@ -675,30 +656,6 @@ __COMMAND_HANDLER(handle_jtag_tap_enabler)
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int jim_jtag_configure(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
|
||||
{
|
||||
struct command *c = jim_to_command(interp);
|
||||
const char *cmd_name = c->name;
|
||||
struct jim_getopt_info goi;
|
||||
jim_getopt_setup(&goi, interp, argc-1, argv + 1);
|
||||
goi.isconfigure = !strcmp(cmd_name, "configure");
|
||||
if (goi.argc < 2 + goi.isconfigure) {
|
||||
Jim_WrongNumArgs(goi.interp, 0, NULL,
|
||||
"<tap_name> <attribute> ...");
|
||||
return JIM_ERR;
|
||||
}
|
||||
|
||||
struct jtag_tap *t;
|
||||
|
||||
Jim_Obj *o;
|
||||
jim_getopt_obj(&goi, &o);
|
||||
t = jtag_tap_by_jim_obj(goi.interp, o);
|
||||
if (!t)
|
||||
return JIM_ERR;
|
||||
|
||||
return jtag_tap_configure_cmd(&goi, t);
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(handle_jtag_names)
|
||||
{
|
||||
if (CMD_ARGC != 0)
|
||||
|
|
@ -793,7 +750,7 @@ static const struct command_registration jtag_subcommand_handlers[] = {
|
|||
{
|
||||
.name = "configure",
|
||||
.mode = COMMAND_ANY,
|
||||
.jim_handler = jim_jtag_configure,
|
||||
.handler = handle_jtag_configure,
|
||||
.help = "Provide a Tcl handler for the specified "
|
||||
"TAP event.",
|
||||
.usage = "tap_name '-event' event_name handler",
|
||||
|
|
@ -801,7 +758,7 @@ static const struct command_registration jtag_subcommand_handlers[] = {
|
|||
{
|
||||
.name = "cget",
|
||||
.mode = COMMAND_EXEC,
|
||||
.jim_handler = jim_jtag_configure,
|
||||
.handler = handle_jtag_configure,
|
||||
.help = "Return any Tcl handler for the specified "
|
||||
"TAP event.",
|
||||
.usage = "tap_name '-event' event_name",
|
||||
|
|
|
|||
|
|
@ -20,8 +20,7 @@
|
|||
|
||||
#include <helper/command.h>
|
||||
|
||||
int jim_jtag_configure(Jim_Interp *interp, int argc,
|
||||
Jim_Obj * const *argv);
|
||||
__COMMAND_HANDLER(handle_jtag_configure);
|
||||
__COMMAND_HANDLER(handle_jtag_tap_enabler);
|
||||
|
||||
#endif /* OPENOCD_JTAG_TCL_H */
|
||||
|
|
|
|||
|
|
@ -118,7 +118,8 @@ static const struct command_registration dapdirect_jtag_subcommand_handlers[] =
|
|||
{
|
||||
.name = "cget",
|
||||
.mode = COMMAND_EXEC,
|
||||
.jim_handler = jim_jtag_configure,
|
||||
.handler = handle_jtag_configure,
|
||||
.usage = "",
|
||||
},
|
||||
{
|
||||
.name = "names",
|
||||
|
|
|
|||
|
|
@ -257,7 +257,7 @@ struct arm {
|
|||
};
|
||||
|
||||
/** Convert target handle to generic ARM target state handle. */
|
||||
static inline struct arm *target_to_arm(struct target *target)
|
||||
static inline struct arm *target_to_arm(const struct target *target)
|
||||
{
|
||||
assert(target);
|
||||
return target->arch_info;
|
||||
|
|
@ -293,11 +293,11 @@ extern const struct command_registration arm_command_handlers[];
|
|||
extern const struct command_registration arm_all_profiles_command_handlers[];
|
||||
|
||||
int arm_arch_state(struct target *target);
|
||||
const char *arm_get_gdb_arch(struct target *target);
|
||||
const char *arm_get_gdb_arch(const struct target *target);
|
||||
int arm_get_gdb_reg_list(struct target *target,
|
||||
struct reg **reg_list[], int *reg_list_size,
|
||||
enum target_register_class reg_class);
|
||||
const char *armv8_get_gdb_arch(struct target *target);
|
||||
const char *armv8_get_gdb_arch(const struct target *target);
|
||||
int armv8_get_gdb_reg_list(struct target *target,
|
||||
struct reg **reg_list[], int *reg_list_size,
|
||||
enum target_register_class reg_class);
|
||||
|
|
|
|||
|
|
@ -1264,7 +1264,7 @@ const struct command_registration arm_command_handlers[] = {
|
|||
* same way as a gdb for arm. This can be changed later on. User can still
|
||||
* set the specific architecture variant with the gdb command.
|
||||
*/
|
||||
const char *arm_get_gdb_arch(struct target *target)
|
||||
const char *arm_get_gdb_arch(const struct target *target)
|
||||
{
|
||||
return "arm";
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1865,7 +1865,7 @@ const struct command_registration armv8_command_handlers[] = {
|
|||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
||||
const char *armv8_get_gdb_arch(struct target *target)
|
||||
const char *armv8_get_gdb_arch(const struct target *target)
|
||||
{
|
||||
struct arm *arm = target_to_arm(target);
|
||||
return arm->core_state == ARM_STATE_AARCH64 ? "aarch64" : "arm";
|
||||
|
|
|
|||
|
|
@ -1248,7 +1248,7 @@ static int esirisc_arch_state(struct target *target)
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static const char *esirisc_get_gdb_arch(struct target *target)
|
||||
static const char *esirisc_get_gdb_arch(const struct target *target)
|
||||
{
|
||||
struct esirisc_common *esirisc = target_to_esirisc(target);
|
||||
|
||||
|
|
@ -1486,6 +1486,32 @@ static struct reg_cache *esirisc_build_reg_cache(struct target *target)
|
|||
return cache;
|
||||
}
|
||||
|
||||
static void esirisc_free_reg_cache(struct target *target)
|
||||
{
|
||||
struct esirisc_common *esirisc = target_to_esirisc(target);
|
||||
struct reg_cache *cache = esirisc->reg_cache;
|
||||
struct reg *reg_list = cache->reg_list;
|
||||
|
||||
for (int i = 0; i < esirisc->num_regs; ++i) {
|
||||
struct reg *reg = reg_list + esirisc_regs[i].number;
|
||||
|
||||
free(reg->arch_info);
|
||||
free(reg->value);
|
||||
free(reg->reg_data_type);
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < ARRAY_SIZE(esirisc_csrs); ++i) {
|
||||
struct reg *reg = reg_list + esirisc_csrs[i].number;
|
||||
|
||||
free(reg->arch_info);
|
||||
free(reg->value);
|
||||
free(reg->reg_data_type);
|
||||
}
|
||||
|
||||
free(reg_list);
|
||||
free(cache);
|
||||
}
|
||||
|
||||
static int esirisc_identify(struct target *target)
|
||||
{
|
||||
struct esirisc_common *esirisc = target_to_esirisc(target);
|
||||
|
|
@ -1584,6 +1610,19 @@ static int esirisc_init_target(struct command_context *cmd_ctx, struct target *t
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static void esirisc_deinit_target(struct target *target)
|
||||
{
|
||||
struct esirisc_common *esirisc = target_to_esirisc(target);
|
||||
|
||||
if (!target_was_examined(target))
|
||||
return;
|
||||
|
||||
esirisc_free_reg_cache(target);
|
||||
|
||||
free(esirisc->gdb_arch);
|
||||
free(esirisc);
|
||||
}
|
||||
|
||||
static int esirisc_examine(struct target *target)
|
||||
{
|
||||
struct esirisc_common *esirisc = target_to_esirisc(target);
|
||||
|
|
@ -1822,5 +1861,6 @@ struct target_type esirisc_target = {
|
|||
|
||||
.target_create = esirisc_target_create,
|
||||
.init_target = esirisc_init_target,
|
||||
.deinit_target = esirisc_deinit_target,
|
||||
.examine = esirisc_examine,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -106,7 +106,7 @@ struct esirisc_reg {
|
|||
int (*write)(struct reg *reg);
|
||||
};
|
||||
|
||||
static inline struct esirisc_common *target_to_esirisc(struct target *target)
|
||||
static inline struct esirisc_common *target_to_esirisc(const struct target *target)
|
||||
{
|
||||
return (struct esirisc_common *)target->arch_info;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -182,7 +182,7 @@ static struct reg_arch_type mem_ap_reg_arch_type = {
|
|||
.set = mem_ap_reg_set,
|
||||
};
|
||||
|
||||
static const char *mem_ap_get_gdb_arch(struct target *target)
|
||||
static const char *mem_ap_get_gdb_arch(const struct target *target)
|
||||
{
|
||||
return "arm";
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2639,7 +2639,7 @@ static int riscv_write_memory(struct target *target, target_addr_t address,
|
|||
return tt->write_memory(target, physical_addr, size, count, buffer);
|
||||
}
|
||||
|
||||
static const char *riscv_get_gdb_arch(struct target *target)
|
||||
static const char *riscv_get_gdb_arch(const struct target *target)
|
||||
{
|
||||
switch (riscv_xlen(target)) {
|
||||
case 32:
|
||||
|
|
|
|||
|
|
@ -1158,7 +1158,7 @@ static int stm8_write_core_reg(struct target *target, unsigned int num)
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static const char *stm8_get_gdb_arch(struct target *target)
|
||||
static const char *stm8_get_gdb_arch(const struct target *target)
|
||||
{
|
||||
return "stm8";
|
||||
}
|
||||
|
|
|
|||
|
|
@ -245,7 +245,7 @@ static const struct nvp nvp_reset_modes[] = {
|
|||
{ .name = NULL, .value = -1 },
|
||||
};
|
||||
|
||||
const char *debug_reason_name(struct target *t)
|
||||
const char *debug_reason_name(const struct target *t)
|
||||
{
|
||||
const char *cp;
|
||||
|
||||
|
|
@ -258,7 +258,7 @@ const char *debug_reason_name(struct target *t)
|
|||
return cp;
|
||||
}
|
||||
|
||||
const char *target_state_name(struct target *t)
|
||||
const char *target_state_name(const struct target *t)
|
||||
{
|
||||
const char *cp;
|
||||
cp = nvp_value2name(nvp_target_state, t->state)->name;
|
||||
|
|
@ -743,7 +743,7 @@ int target_examine(void)
|
|||
return retval;
|
||||
}
|
||||
|
||||
const char *target_type_name(struct target *target)
|
||||
const char *target_type_name(const struct target *target)
|
||||
{
|
||||
return target->type->name;
|
||||
}
|
||||
|
|
@ -1368,7 +1368,7 @@ int target_hit_watchpoint(struct target *target,
|
|||
return target->type->hit_watchpoint(target, hit_watchpoint);
|
||||
}
|
||||
|
||||
const char *target_get_gdb_arch(struct target *target)
|
||||
const char *target_get_gdb_arch(const struct target *target)
|
||||
{
|
||||
if (!target->type->get_gdb_arch)
|
||||
return NULL;
|
||||
|
|
@ -1408,7 +1408,7 @@ int target_get_gdb_reg_list_noread(struct target *target,
|
|||
return target_get_gdb_reg_list(target, reg_list, reg_list_size, reg_class);
|
||||
}
|
||||
|
||||
bool target_supports_gdb_connection(struct target *target)
|
||||
bool target_supports_gdb_connection(const struct target *target)
|
||||
{
|
||||
/*
|
||||
* exclude all the targets that don't provide get_gdb_reg_list
|
||||
|
|
@ -4853,7 +4853,7 @@ static int target_jim_set_reg(Jim_Interp *interp, int argc,
|
|||
/**
|
||||
* Returns true only if the target has a handler for the specified event.
|
||||
*/
|
||||
bool target_has_event_action(struct target *target, enum target_event event)
|
||||
bool target_has_event_action(const struct target *target, enum target_event event)
|
||||
{
|
||||
struct target_event_action *teap;
|
||||
|
||||
|
|
|
|||
|
|
@ -228,19 +228,19 @@ struct gdb_fileio_info {
|
|||
};
|
||||
|
||||
/** Returns a description of the endianness for the specified target. */
|
||||
static inline const char *target_endianness(struct target *target)
|
||||
static inline const char *target_endianness(const struct target *target)
|
||||
{
|
||||
return (target->endianness == TARGET_ENDIAN_UNKNOWN) ? "unknown" :
|
||||
(target->endianness == TARGET_BIG_ENDIAN) ? "big endian" : "little endian";
|
||||
}
|
||||
|
||||
/** Returns the instance-specific name of the specified target. */
|
||||
static inline const char *target_name(struct target *target)
|
||||
static inline const char *target_name(const struct target *target)
|
||||
{
|
||||
return target->cmd_name;
|
||||
}
|
||||
|
||||
const char *debug_reason_name(struct target *t);
|
||||
const char *debug_reason_name(const struct target *t);
|
||||
|
||||
enum target_event {
|
||||
|
||||
|
|
@ -307,7 +307,7 @@ struct target_event_action {
|
|||
struct target_event_action *next;
|
||||
};
|
||||
|
||||
bool target_has_event_action(struct target *target, enum target_event event);
|
||||
bool target_has_event_action(const struct target *target, enum target_event event);
|
||||
|
||||
struct target_event_callback {
|
||||
int (*callback)(struct target *target, enum target_event event, void *priv);
|
||||
|
|
@ -427,7 +427,7 @@ struct target *get_target(const char *id);
|
|||
* This routine is a wrapper for the target->type->name field.
|
||||
* Note that this is not an instance-specific name for his target.
|
||||
*/
|
||||
const char *target_type_name(struct target *target);
|
||||
const char *target_type_name(const struct target *target);
|
||||
|
||||
/**
|
||||
* Examine the specified @a target, letting it perform any
|
||||
|
|
@ -507,7 +507,7 @@ int target_hit_watchpoint(struct target *target,
|
|||
*
|
||||
* This routine is a wrapper for target->type->get_gdb_arch.
|
||||
*/
|
||||
const char *target_get_gdb_arch(struct target *target);
|
||||
const char *target_get_gdb_arch(const struct target *target);
|
||||
|
||||
/**
|
||||
* Obtain the registers for GDB.
|
||||
|
|
@ -533,7 +533,7 @@ int target_get_gdb_reg_list_noread(struct target *target,
|
|||
*
|
||||
* Some target do not implement the necessary code required by GDB.
|
||||
*/
|
||||
bool target_supports_gdb_connection(struct target *target);
|
||||
bool target_supports_gdb_connection(const struct target *target);
|
||||
|
||||
/**
|
||||
* Step the target.
|
||||
|
|
@ -700,7 +700,7 @@ unsigned target_address_bits(struct target *target);
|
|||
unsigned int target_data_bits(struct target *target);
|
||||
|
||||
/** Return the *name* of this targets current state */
|
||||
const char *target_state_name(struct target *target);
|
||||
const char *target_state_name(const struct target *target);
|
||||
|
||||
/** Return the *name* of a target event enumeration value */
|
||||
const char *target_event_name(enum target_event event);
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@ struct target_type {
|
|||
* if dynamic allocation is used for this value, it must be managed by
|
||||
* the target, ideally by caching the result for subsequent calls.
|
||||
*/
|
||||
const char *(*get_gdb_arch)(struct target *target);
|
||||
const char *(*get_gdb_arch)(const struct target *target);
|
||||
|
||||
/**
|
||||
* Target register access for GDB. Do @b not call this function
|
||||
|
|
|
|||
|
|
@ -3442,7 +3442,7 @@ void xtensa_target_deinit(struct target *target)
|
|||
free(xtensa->core_config);
|
||||
}
|
||||
|
||||
const char *xtensa_get_gdb_arch(struct target *target)
|
||||
const char *xtensa_get_gdb_arch(const struct target *target)
|
||||
{
|
||||
return "xtensa";
|
||||
}
|
||||
|
|
@ -3459,8 +3459,8 @@ static COMMAND_HELPER(xtensa_cmd_exe_do, struct target *target)
|
|||
const char *parm = CMD_ARGV[0];
|
||||
unsigned int parm_len = strlen(parm);
|
||||
if ((parm_len >= 64) || (parm_len & 1)) {
|
||||
LOG_ERROR("Invalid parameter length (%d): must be even, < 64 characters", parm_len);
|
||||
return ERROR_FAIL;
|
||||
command_print(CMD, "Invalid parameter length (%d): must be even, < 64 characters", parm_len);
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
|
||||
uint8_t ops[32];
|
||||
|
|
@ -3480,7 +3480,7 @@ static COMMAND_HELPER(xtensa_cmd_exe_do, struct target *target)
|
|||
*/
|
||||
int status = xtensa_write_dirty_registers(target);
|
||||
if (status != ERROR_OK) {
|
||||
LOG_ERROR("%s: Failed to write back register cache.", target_name(target));
|
||||
command_print(CMD, "%s: Failed to write back register cache.", target_name(target));
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
xtensa_reg_val_t exccause = xtensa_reg_get(target, XT_REG_IDX_EXCCAUSE);
|
||||
|
|
@ -3498,18 +3498,18 @@ static COMMAND_HELPER(xtensa_cmd_exe_do, struct target *target)
|
|||
xtensa_queue_exec_ins_wide(xtensa, ops, oplen); /* Handles endian-swap */
|
||||
status = xtensa_dm_queue_execute(&xtensa->dbg_mod);
|
||||
if (status != ERROR_OK) {
|
||||
LOG_TARGET_ERROR(target, "exec: queue error %d", status);
|
||||
command_print(CMD, "exec: queue error %d", status);
|
||||
} else {
|
||||
status = xtensa_core_status_check(target);
|
||||
if (status != ERROR_OK)
|
||||
LOG_TARGET_ERROR(target, "exec: status error %d", status);
|
||||
command_print(CMD, "exec: status error %d", status);
|
||||
}
|
||||
|
||||
/* Reread register cache and restore saved regs after instruction execution */
|
||||
if (xtensa_fetch_all_regs(target) != ERROR_OK)
|
||||
LOG_TARGET_ERROR(target, "post-exec: register fetch error");
|
||||
command_print(CMD, "post-exec: register fetch error");
|
||||
if (status != ERROR_OK) {
|
||||
LOG_TARGET_ERROR(target, "post-exec: EXCCAUSE 0x%02" PRIx32,
|
||||
command_print(CMD, "post-exec: EXCCAUSE 0x%02" PRIx32,
|
||||
xtensa_reg_get(target, XT_REG_IDX_EXCCAUSE));
|
||||
}
|
||||
xtensa_reg_set(target, XT_REG_IDX_EXCCAUSE, exccause);
|
||||
|
|
@ -3534,8 +3534,8 @@ COMMAND_HELPER(xtensa_cmd_xtdef_do, struct xtensa *xtensa)
|
|||
} else if (strcasecmp(core_name, "NX") == 0) {
|
||||
xtensa->core_config->core_type = XT_NX;
|
||||
} else {
|
||||
LOG_ERROR("xtdef [LX|NX]\n");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
command_print(CMD, "xtdef [LX|NX]\n");
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -3592,7 +3592,7 @@ COMMAND_HELPER(xtensa_cmd_xtopt_do, struct xtensa *xtensa)
|
|||
if (!xtensa_cmd_xtopt_legal_val("excmlevel", opt_val, 1, 6))
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
if (!xtensa->core_config->high_irq.enabled) {
|
||||
LOG_ERROR("xtopt excmlevel requires hipriints\n");
|
||||
command_print(CMD, "xtopt excmlevel requires hipriints\n");
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
xtensa->core_config->high_irq.excm_level = opt_val;
|
||||
|
|
@ -3605,7 +3605,7 @@ COMMAND_HELPER(xtensa_cmd_xtopt_do, struct xtensa *xtensa)
|
|||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
if (!xtensa->core_config->high_irq.enabled) {
|
||||
LOG_ERROR("xtopt intlevels requires hipriints\n");
|
||||
command_print(CMD, "xtopt intlevels requires hipriints\n");
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
xtensa->core_config->high_irq.level_num = opt_val;
|
||||
|
|
@ -3662,10 +3662,8 @@ COMMAND_HELPER(xtensa_cmd_xtmem_do, struct xtensa *xtensa)
|
|||
int mem_access = 0;
|
||||
bool is_dcache = false;
|
||||
|
||||
if (CMD_ARGC == 0) {
|
||||
LOG_ERROR("xtmem <type> [parameters]\n");
|
||||
if (CMD_ARGC == 0)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
const char *mem_name = CMD_ARGV[0];
|
||||
if (strcasecmp(mem_name, "icache") == 0) {
|
||||
|
|
@ -3696,25 +3694,21 @@ COMMAND_HELPER(xtensa_cmd_xtmem_do, struct xtensa *xtensa)
|
|||
memp = &xtensa->core_config->srom;
|
||||
mem_access = XT_MEM_ACCESS_READ;
|
||||
} else {
|
||||
LOG_ERROR("xtmem types: <icache|dcache|l2cache|l2addr|iram|irom|dram|drom|sram|srom>\n");
|
||||
command_print(CMD, "xtmem types: <icache|dcache|l2cache|l2addr|iram|irom|dram|drom|sram|srom>\n");
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
|
||||
if (cachep) {
|
||||
if ((CMD_ARGC != 4) && (CMD_ARGC != 5)) {
|
||||
LOG_ERROR("xtmem <cachetype> <linebytes> <cachebytes> <ways> [writeback]\n");
|
||||
if (CMD_ARGC != 4 && CMD_ARGC != 5)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
cachep->line_size = strtoul(CMD_ARGV[1], NULL, 0);
|
||||
cachep->size = strtoul(CMD_ARGV[2], NULL, 0);
|
||||
cachep->way_count = strtoul(CMD_ARGV[3], NULL, 0);
|
||||
cachep->writeback = ((CMD_ARGC == 5) && is_dcache) ?
|
||||
strtoul(CMD_ARGV[4], NULL, 0) : 0;
|
||||
} else if (memp) {
|
||||
if (CMD_ARGC != 3) {
|
||||
LOG_ERROR("xtmem <memtype> <baseaddr> <bytes>\n");
|
||||
if (CMD_ARGC != 3)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
struct xtensa_local_mem_region_config *memcfgp = &memp->regions[memp->count];
|
||||
memcfgp->base = strtoul(CMD_ARGV[1], NULL, 0);
|
||||
memcfgp->size = strtoul(CMD_ARGV[2], NULL, 0);
|
||||
|
|
@ -3734,10 +3728,8 @@ COMMAND_HANDLER(xtensa_cmd_xtmem)
|
|||
/* xtmpu <num FG seg> <min seg size> <lockable> <executeonly> */
|
||||
COMMAND_HELPER(xtensa_cmd_xtmpu_do, struct xtensa *xtensa)
|
||||
{
|
||||
if (CMD_ARGC != 4) {
|
||||
LOG_ERROR("xtmpu <num FG seg> <min seg size> <lockable> <executeonly>\n");
|
||||
if (CMD_ARGC != 4)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
unsigned int nfgseg = strtoul(CMD_ARGV[0], NULL, 0);
|
||||
unsigned int minsegsize = strtoul(CMD_ARGV[1], NULL, 0);
|
||||
|
|
@ -3745,16 +3737,16 @@ COMMAND_HELPER(xtensa_cmd_xtmpu_do, struct xtensa *xtensa)
|
|||
unsigned int execonly = strtoul(CMD_ARGV[3], NULL, 0);
|
||||
|
||||
if ((nfgseg > 32)) {
|
||||
LOG_ERROR("<nfgseg> must be within [0..32]\n");
|
||||
command_print(CMD, "<nfgseg> must be within [0..32]\n");
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
} else if (minsegsize & (minsegsize - 1)) {
|
||||
LOG_ERROR("<minsegsize> must be a power of 2 >= 32\n");
|
||||
command_print(CMD, "<minsegsize> must be a power of 2 >= 32\n");
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
} else if (lockable > 1) {
|
||||
LOG_ERROR("<lockable> must be 0 or 1\n");
|
||||
command_print(CMD, "<lockable> must be 0 or 1\n");
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
} else if (execonly > 1) {
|
||||
LOG_ERROR("<execonly> must be 0 or 1\n");
|
||||
command_print(CMD, "<execonly> must be 0 or 1\n");
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
|
||||
|
|
@ -3775,18 +3767,16 @@ COMMAND_HANDLER(xtensa_cmd_xtmpu)
|
|||
/* xtmmu <NIREFILLENTRIES> <NDREFILLENTRIES> <IVARWAY56> <DVARWAY56> */
|
||||
COMMAND_HELPER(xtensa_cmd_xtmmu_do, struct xtensa *xtensa)
|
||||
{
|
||||
if (CMD_ARGC != 2) {
|
||||
LOG_ERROR("xtmmu <NIREFILLENTRIES> <NDREFILLENTRIES>\n");
|
||||
if (CMD_ARGC != 2)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
unsigned int nirefillentries = strtoul(CMD_ARGV[0], NULL, 0);
|
||||
unsigned int ndrefillentries = strtoul(CMD_ARGV[1], NULL, 0);
|
||||
if ((nirefillentries != 16) && (nirefillentries != 32)) {
|
||||
LOG_ERROR("<nirefillentries> must be 16 or 32\n");
|
||||
command_print(CMD, "<nirefillentries> must be 16 or 32\n");
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
} else if ((ndrefillentries != 16) && (ndrefillentries != 32)) {
|
||||
LOG_ERROR("<ndrefillentries> must be 16 or 32\n");
|
||||
command_print(CMD, "<ndrefillentries> must be 16 or 32\n");
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
|
||||
|
|
@ -3809,13 +3799,13 @@ COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa)
|
|||
if (CMD_ARGC == 1) {
|
||||
int32_t numregs = strtoul(CMD_ARGV[0], NULL, 0);
|
||||
if ((numregs <= 0) || (numregs > UINT16_MAX)) {
|
||||
LOG_ERROR("xtreg <numregs>: Invalid 'numregs' (%d)", numregs);
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
command_print(CMD, "xtreg <numregs>: Invalid 'numregs' (%d)", numregs);
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
if ((xtensa->genpkt_regs_num > 0) && (numregs < (int32_t)xtensa->genpkt_regs_num)) {
|
||||
LOG_ERROR("xtregs (%d) must be larger than numgenregs (%d) (if xtregfmt specified)",
|
||||
command_print(CMD, "xtregs (%d) must be larger than numgenregs (%d) (if xtregfmt specified)",
|
||||
numregs, xtensa->genpkt_regs_num);
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
xtensa->total_regs_num = numregs;
|
||||
xtensa->core_regs_num = 0;
|
||||
|
|
@ -3844,17 +3834,17 @@ COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa)
|
|||
const char *regname = CMD_ARGV[0];
|
||||
unsigned int regnum = strtoul(CMD_ARGV[1], NULL, 0);
|
||||
if (regnum > UINT16_MAX) {
|
||||
LOG_ERROR("<regnum> must be a 16-bit number");
|
||||
command_print(CMD, "<regnum> must be a 16-bit number");
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
|
||||
if ((xtensa->num_optregs + xtensa->core_regs_num) >= xtensa->total_regs_num) {
|
||||
if (xtensa->total_regs_num)
|
||||
LOG_ERROR("'xtreg %s 0x%04x': Too many registers (%d expected, %d core %d extended)",
|
||||
command_print(CMD, "'xtreg %s 0x%04x': Too many registers (%d expected, %d core %d extended)",
|
||||
regname, regnum,
|
||||
xtensa->total_regs_num, xtensa->core_regs_num, xtensa->num_optregs);
|
||||
else
|
||||
LOG_ERROR("'xtreg %s 0x%04x': Number of registers unspecified",
|
||||
command_print(CMD, "'xtreg %s 0x%04x': Number of registers unspecified",
|
||||
regname, regnum);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
|
@ -3934,7 +3924,7 @@ COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa)
|
|||
idx = XT_NX_REG_IDX_MESRCLR;
|
||||
if (idx < XT_NX_REG_IDX_NUM) {
|
||||
if (xtensa->nx_reg_idx[idx] != 0) {
|
||||
LOG_ERROR("nx_reg_idx[%d] previously set to %d",
|
||||
command_print(CMD, "nx_reg_idx[%d] previously set to %d",
|
||||
idx, xtensa->nx_reg_idx[idx]);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
|
@ -3981,9 +3971,9 @@ COMMAND_HELPER(xtensa_cmd_xtregfmt_do, struct xtensa *xtensa)
|
|||
if ((numgregs <= 0) ||
|
||||
((numgregs > xtensa->total_regs_num) &&
|
||||
(xtensa->total_regs_num > 0))) {
|
||||
LOG_ERROR("xtregfmt: if specified, numgregs (%d) must be <= numregs (%d)",
|
||||
command_print(CMD, "xtregfmt: if specified, numgregs (%d) must be <= numregs (%d)",
|
||||
numgregs, xtensa->total_regs_num);
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
return ERROR_COMMAND_ARGUMENT_INVALID;
|
||||
}
|
||||
xtensa->genpkt_regs_num = numgregs;
|
||||
}
|
||||
|
|
@ -4099,7 +4089,7 @@ COMMAND_HELPER(xtensa_cmd_perfmon_dump_do, struct xtensa *xtensa)
|
|||
"%-12" PRIu64 "%s",
|
||||
result.value,
|
||||
result.overflow ? " (overflow)" : "");
|
||||
LOG_INFO("%s", result_buf);
|
||||
command_print(CMD, "%s", result_buf);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
|
|
@ -4349,21 +4339,21 @@ COMMAND_HELPER(xtensa_cmd_tracedump_do, struct xtensa *xtensa, const char *fname
|
|||
}
|
||||
|
||||
memsz = trace_config.memaddr_end - trace_config.memaddr_start + 1;
|
||||
LOG_INFO("Total trace memory: %d words", memsz);
|
||||
command_print(CMD, "Total trace memory: %d words", memsz);
|
||||
if ((trace_config.addr &
|
||||
((TRAXADDR_TWRAP_MASK << TRAXADDR_TWRAP_SHIFT) | TRAXADDR_TWSAT)) == 0) {
|
||||
/*Memory hasn't overwritten itself yet. */
|
||||
wmem = trace_config.addr & TRAXADDR_TADDR_MASK;
|
||||
LOG_INFO("...but trace is only %d words", wmem);
|
||||
command_print(CMD, "...but trace is only %d words", wmem);
|
||||
if (wmem < memsz)
|
||||
memsz = wmem;
|
||||
} else {
|
||||
if (trace_config.addr & TRAXADDR_TWSAT) {
|
||||
LOG_INFO("Real trace is many times longer than that (overflow)");
|
||||
command_print(CMD, "Real trace is many times longer than that (overflow)");
|
||||
} else {
|
||||
uint32_t trc_sz = (trace_config.addr >> TRAXADDR_TWRAP_SHIFT) & TRAXADDR_TWRAP_MASK;
|
||||
trc_sz = (trc_sz * memsz) + (trace_config.addr & TRAXADDR_TADDR_MASK);
|
||||
LOG_INFO("Real trace is %d words, but the start has been truncated.", trc_sz);
|
||||
command_print(CMD, "Real trace is %d words, but the start has been truncated.", trc_sz);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -422,7 +422,7 @@ int xtensa_run_algorithm(struct target *target,
|
|||
target_addr_t entry_point, target_addr_t exit_point,
|
||||
unsigned int timeout_ms, void *arch_info);
|
||||
void xtensa_set_permissive_mode(struct target *target, bool state);
|
||||
const char *xtensa_get_gdb_arch(struct target *target);
|
||||
const char *xtensa_get_gdb_arch(const struct target *target);
|
||||
int xtensa_gdb_query_custom(struct target *target, const char *packet, char **response_p);
|
||||
|
||||
COMMAND_HELPER(xtensa_cmd_xtdef_do, struct xtensa *xtensa);
|
||||
|
|
|
|||
|
|
@ -4,10 +4,13 @@
|
|||
|
||||
source [find interface/vdebug.cfg]
|
||||
|
||||
set _CORES 2
|
||||
set _CHIPNAME a53
|
||||
set _MEMSTART 0x00000000
|
||||
set _MEMSIZE 0x1000000
|
||||
set CORES 2
|
||||
set CHIPNAME a53
|
||||
set ACCESSPORT 0
|
||||
set MEMSTART 0x00000000
|
||||
set MEMSIZE 0x1000000
|
||||
set DBGBASE {0x80810000 0x80910000}
|
||||
set CTIBASE {0x80820000 0x80920000}
|
||||
|
||||
# vdebug select transport
|
||||
transport select dapdirect_swd
|
||||
|
|
@ -19,11 +22,9 @@ adapter srst delay 5
|
|||
# BFM hierarchical path and input clk period
|
||||
vdebug bfm_path tbench.u_vd_swdp_bfm 10ns
|
||||
|
||||
# DMA Memories to access backdoor (up to 4)
|
||||
vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
|
||||
# DMA Memories to access backdoor (up to 20)
|
||||
vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
|
||||
|
||||
source [find target/swj-dp.tcl]
|
||||
|
||||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
|
||||
swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
|
||||
|
||||
source [find target/vd_aarch64.cfg]
|
||||
|
|
|
|||
|
|
@ -4,11 +4,14 @@
|
|||
|
||||
source [find interface/vdebug.cfg]
|
||||
|
||||
set _CORES 2
|
||||
set _CHIPNAME a53
|
||||
set _MEMSTART 0x00000000
|
||||
set _MEMSIZE 0x1000000
|
||||
set _CPUTAPID 0x5ba00477
|
||||
set CORES 2
|
||||
set CHIPNAME a53
|
||||
set ACCESSPORT 0
|
||||
set MEMSTART 0x00000000
|
||||
set MEMSIZE 0x1000000
|
||||
set DBGBASE {0x80810000 0x80910000}
|
||||
set CTIBASE {0x80820000 0x80920000}
|
||||
set CPUTAPID 0x5ba00477
|
||||
|
||||
# vdebug select transport
|
||||
transport select jtag
|
||||
|
|
@ -21,11 +24,10 @@ adapter srst delay 5
|
|||
# BFM hierarchical path and input clk period
|
||||
vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
|
||||
|
||||
# DMA Memories to access backdoor (up to 4)
|
||||
vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
# DMA Memories to access backdoor (up to 20)
|
||||
vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
|
||||
|
||||
jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
|
||||
jtag arp_init-reset
|
||||
|
||||
source [find target/vd_aarch64.cfg]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,30 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# Cadence virtual debug interface
|
||||
# Arm Cortex A53x2 through DAP
|
||||
|
||||
source [find interface/vdebug.cfg]
|
||||
|
||||
set CORES 4
|
||||
set CHIPNAME a75
|
||||
set ACCESSPORT 0x00040000
|
||||
set MEMSTART 0x00000000
|
||||
set MEMSIZE 0x1000000
|
||||
set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
|
||||
set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
|
||||
|
||||
# vdebug select transport
|
||||
transport select dapdirect_swd
|
||||
|
||||
# JTAG reset config, frequency and reset delay
|
||||
adapter speed 200000
|
||||
adapter srst delay 5
|
||||
|
||||
# BFM hierarchical path and input clk period
|
||||
vdebug bfm_path tbench.u_vd_dap6_bfm 2250ps
|
||||
|
||||
# DMA Memories to access backdoor (up to 20)
|
||||
#vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
|
||||
|
||||
swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
|
||||
|
||||
source [find target/vd_aarch64.cfg]
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# Cadence virtual debug interface
|
||||
# Arm Cortex A53x2 through DAP
|
||||
|
||||
source [find interface/vdebug.cfg]
|
||||
|
||||
set CORES 4
|
||||
set CHIPNAME a75
|
||||
set ACCESSPORT 0x00040000
|
||||
set MEMSTART 0x00000000
|
||||
set MEMSIZE 0x1000000
|
||||
set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
|
||||
set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
|
||||
set CPUTAPID 0x4ba06477
|
||||
|
||||
# vdebug select transport
|
||||
transport select jtag
|
||||
|
||||
# JTAG reset config, frequency and reset delay
|
||||
reset_config trst_and_srst
|
||||
adapter speed 1500000
|
||||
adapter srst delay 5
|
||||
|
||||
# BFM hierarchical path and input clk period
|
||||
vdebug bfm_path tbench.u_vd_jtag_bfm 333ps
|
||||
|
||||
jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
|
||||
jtag arp_init-reset
|
||||
|
||||
source [find target/vd_aarch64.cfg]
|
||||
|
|
@ -4,9 +4,9 @@
|
|||
|
||||
source [find interface/vdebug.cfg]
|
||||
|
||||
set _CHIPNAME m4
|
||||
set _MEMSTART 0x00000000
|
||||
set _MEMSIZE 0x10000
|
||||
set CHIPNAME m4
|
||||
set MEMSTART 0x00000000
|
||||
set MEMSIZE 0x10000
|
||||
|
||||
# vdebug select transport
|
||||
transport select dapdirect_swd
|
||||
|
|
@ -16,11 +16,9 @@ adapter srst delay 5
|
|||
# BFM hierarchical path and input clk period
|
||||
vdebug bfm_path tbench.u_vd_swdp_bfm 20ns
|
||||
|
||||
# DMA Memories to access backdoor (up to 4)
|
||||
vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE
|
||||
# DMA Memories to access backdoor (up to 20)
|
||||
vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $MEMSTART $MEMSIZE
|
||||
|
||||
source [find target/swj-dp.tcl]
|
||||
|
||||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
|
||||
swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
|
||||
|
||||
source [find target/vd_cortex_m.cfg]
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@
|
|||
|
||||
source [find interface/vdebug.cfg]
|
||||
|
||||
set _CHIPNAME m4
|
||||
set _MEMSTART 0x00000000
|
||||
set _MEMSIZE 0x10000
|
||||
set _CPUTAPID 0x4ba00477
|
||||
set CHIPNAME m4
|
||||
set MEMSTART 0x00000000
|
||||
set MEMSIZE 0x10000
|
||||
set CPUTAPID 0x4ba00477
|
||||
|
||||
# vdebug select transport
|
||||
transport select jtag
|
||||
|
|
@ -20,11 +20,10 @@ adapter srst delay 5
|
|||
# BFM hierarchical path and input clk period
|
||||
vdebug bfm_path tbench.u_vd_jtag_bfm 20ns
|
||||
|
||||
# DMA Memories to access backdoor (up to 4)
|
||||
vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
# DMA Memories to access backdoor (up to 20)
|
||||
vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $MEMSTART $MEMSIZE
|
||||
|
||||
jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
|
||||
jtag arp_init-reset
|
||||
|
||||
source [find target/vd_cortex_m.cfg]
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@
|
|||
|
||||
source [find interface/vdebug.cfg]
|
||||
|
||||
set _CHIPNAME m7
|
||||
set _MEMSTART 0x00000000
|
||||
set _MEMSIZE 0x100000
|
||||
set _CPUTAPID 0x0ba02477
|
||||
set CHIPNAME m7
|
||||
set MEMSTART 0x00000000
|
||||
set MEMSIZE 0x100000
|
||||
set CPUTAPID 0x0ba02477
|
||||
|
||||
# vdebug select JTAG transport
|
||||
transport select jtag
|
||||
|
|
@ -20,11 +20,10 @@ adapter srst delay 5
|
|||
# BFM hierarchical path and input clk period
|
||||
vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
|
||||
|
||||
# DMA Memories to access backdoor (up to 4)
|
||||
vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
# DMA Memories to access backdoor (up to 20)
|
||||
vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $MEMSTART $MEMSIZE
|
||||
|
||||
jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
|
||||
jtag arp_init-reset
|
||||
|
||||
source [find target/vd_cortex_m.cfg]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,33 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# Cadence virtual debug interface
|
||||
# for Palladium emulation systems
|
||||
#
|
||||
|
||||
source [find interface/vdebug.cfg]
|
||||
|
||||
# vdebug select JTAG transport
|
||||
transport select jtag
|
||||
|
||||
# JTAG reset config, frequency and reset delay
|
||||
reset_config trst_and_srst
|
||||
adapter speed 50000
|
||||
adapter srst delay 5
|
||||
|
||||
# Future improvement: Enable backdoor memory access
|
||||
# set _MEMSTART 0x00000000
|
||||
# set _MEMSIZE 0x100000
|
||||
|
||||
# BFM hierarchical path and input clk period
|
||||
vdebug bfm_path Testbench.VJTAG 10ns
|
||||
|
||||
# DMA Memories to access backdoor (up to 4)
|
||||
# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
|
||||
|
||||
# Configure dual-core TAP chain
|
||||
set XTENSA_NUM_CORES 2
|
||||
|
||||
# Create Xtensa target first
|
||||
source [find target/xtensa.cfg]
|
||||
|
||||
# Configure Xtensa core parameters next
|
||||
# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
|
||||
|
|
@ -13,4 +13,18 @@ reset_config trst_and_srst
|
|||
adapter speed 50000
|
||||
adapter srst delay 5
|
||||
|
||||
source [find target/vd_xtensa_jtag.cfg]
|
||||
# Future improvement: Enable backdoor memory access
|
||||
# set _MEMSTART 0x00000000
|
||||
# set _MEMSIZE 0x100000
|
||||
|
||||
# BFM hierarchical path and input clk period
|
||||
vdebug bfm_path Testbench.VJTAG 10ns
|
||||
|
||||
# DMA Memories to access backdoor (up to 4)
|
||||
# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
|
||||
|
||||
# Create Xtensa target first
|
||||
source [find target/xtensa.cfg]
|
||||
|
||||
# Configure Xtensa core parameters next
|
||||
# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
|
||||
|
|
|
|||
|
|
@ -2,36 +2,44 @@
|
|||
# Cadence virtual debug interface
|
||||
# Arm v8 64b Cortex A
|
||||
|
||||
if {![info exists _CORES]} {
|
||||
set _CORES 1
|
||||
if {![info exists CORES]} {
|
||||
set CORES 1
|
||||
}
|
||||
if {![info exists _CHIPNAME]} {
|
||||
set _CHIPNAME aarch64
|
||||
if {![info exists CHIPNAME]} {
|
||||
set CHIPNAME aarch64
|
||||
}
|
||||
if {[info exists ACCESSPORT]} {
|
||||
set _APNUM "-ap-num $ACCESSPORT"
|
||||
if { $ACCESSPORT > 0xff } {
|
||||
set _DAP6 "-adiv6"
|
||||
} else {
|
||||
set _DAP6 "-adiv5"
|
||||
}
|
||||
} else {
|
||||
set _APNUM ""
|
||||
}
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
set _CTINAME $_CHIPNAME.cti
|
||||
|
||||
set DBGBASE {0x80810000 0x80910000}
|
||||
set CTIBASE {0x80820000 0x80920000}
|
||||
set _TARGETNAME $CHIPNAME.cpu
|
||||
set _CTINAME $CHIPNAME.cti
|
||||
set _DAPNAME $CHIPNAME.dap
|
||||
|
||||
dap create $_CHIPNAME.dap -chain-position $_TARGETNAME
|
||||
$_CHIPNAME.dap apsel 1
|
||||
dap create $_DAPNAME $_DAP6 -chain-position $_TARGETNAME
|
||||
|
||||
for { set _core 0 } { $_core < $_CORES } { incr _core } \
|
||||
for { set _core 0 } { $_core < $CORES } { incr _core } \
|
||||
{
|
||||
cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 -baseaddr [lindex $CTIBASE $_core]
|
||||
set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
|
||||
-dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
|
||||
set _cmd "cti create $_CTINAME.$_core -dap $_DAPNAME $_APNUM -baseaddr [lindex $CTIBASE $_core]"
|
||||
eval $_cmd
|
||||
set _cmd "target create $_TARGETNAME.$_core aarch64 -dap $_DAPNAME $_APNUM -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
|
||||
if { $_core != 0 } {
|
||||
# non-boot core examination may fail
|
||||
set _command "$_command -defer-examine"
|
||||
set _smp_command "$_smp_command $_TARGETNAME.$_core"
|
||||
set _cmd "$_cmd -defer-examine"
|
||||
set _smp_cmd "$_smp_cmd $_TARGETNAME.$_core"
|
||||
} else {
|
||||
set _smp_command "target smp $_TARGETNAME.$_core"
|
||||
set _smp_cmd "target smp $_TARGETNAME.$_core"
|
||||
}
|
||||
eval $_command
|
||||
eval $_cmd
|
||||
}
|
||||
eval $_smp_command
|
||||
eval $_smp_cmd
|
||||
|
||||
# default target is core 0
|
||||
targets $_TARGETNAME.0
|
||||
set _TARGETCUR $_TARGETNAME.0
|
||||
targets $_TARGETCUR
|
||||
|
|
|
|||
|
|
@ -2,11 +2,12 @@
|
|||
# Cadence virtual debug interface
|
||||
# ARM Cortex M
|
||||
|
||||
if {![info exists _CHIPNAME]} {
|
||||
set _CHIPNAME cortex_m
|
||||
if {![info exists CHIPNAME]} {
|
||||
set CHIPNAME cortex_m
|
||||
}
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
set _TARGETNAME $CHIPNAME.cpu
|
||||
set _DAPNAME $CHIPNAME.dap
|
||||
|
||||
dap create $_CHIPNAME.dap -chain-position $_TARGETNAME
|
||||
dap create $_DAPNAME -chain-position $_TARGETNAME
|
||||
|
||||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
|
||||
target create $_TARGETNAME cortex_m -dap $_DAPNAME
|
||||
|
|
|
|||
|
|
@ -2,246 +2,254 @@
|
|||
# OpenOCD configuration file for Xtensa HiFi DSP in NXP RT600 target
|
||||
|
||||
|
||||
# Core instance default definition
|
||||
if { [info exists XTNAME] } {
|
||||
set _XTNAME $XTNAME
|
||||
} else {
|
||||
set _XTNAME xtensa.cpu
|
||||
}
|
||||
|
||||
|
||||
# Core definition and ABI
|
||||
xtensa xtdef LX
|
||||
xtensa xtopt arnum 32
|
||||
xtensa xtopt windowed 1
|
||||
$_XTNAME xtensa xtdef LX
|
||||
$_XTNAME xtensa xtopt arnum 32
|
||||
$_XTNAME xtensa xtopt windowed 1
|
||||
|
||||
|
||||
# Exception/Interrupt Options
|
||||
xtensa xtopt exceptions 1
|
||||
xtensa xtopt hipriints 1
|
||||
xtensa xtopt intlevels 4
|
||||
xtensa xtopt excmlevel 2
|
||||
$_XTNAME xtensa xtopt exceptions 1
|
||||
$_XTNAME xtensa xtopt hipriints 1
|
||||
$_XTNAME xtensa xtopt intlevels 4
|
||||
$_XTNAME xtensa xtopt excmlevel 2
|
||||
|
||||
|
||||
# Cache Options
|
||||
xtensa xtmem icache 256 32768 4
|
||||
xtensa xtmem dcache 256 65536 4 1
|
||||
$_XTNAME xtensa xtmem icache 256 32768 4
|
||||
$_XTNAME xtensa xtmem dcache 256 65536 4 1
|
||||
|
||||
|
||||
# Memory Options
|
||||
xtensa xtmem iram 0x24020000 65536
|
||||
xtensa xtmem dram 0x24000000 65536
|
||||
xtensa xtmem sram 0x00000000 603979776
|
||||
$_XTNAME xtensa xtmem iram 0x24020000 65536
|
||||
$_XTNAME xtensa xtmem dram 0x24000000 65536
|
||||
$_XTNAME xtensa xtmem sram 0x00000000 603979776
|
||||
|
||||
|
||||
# Memory Protection/Translation Options
|
||||
|
||||
|
||||
# Debug Options
|
||||
xtensa xtopt debuglevel 4
|
||||
xtensa xtopt ibreaknum 2
|
||||
xtensa xtopt dbreaknum 2
|
||||
$_XTNAME xtensa xtopt debuglevel 4
|
||||
$_XTNAME xtensa xtopt ibreaknum 2
|
||||
$_XTNAME xtensa xtopt dbreaknum 2
|
||||
|
||||
|
||||
# Core Registers
|
||||
xtensa xtregs 208
|
||||
xtensa xtreg pc 0x0020
|
||||
xtensa xtreg ar0 0x0100
|
||||
xtensa xtreg ar1 0x0101
|
||||
xtensa xtreg ar2 0x0102
|
||||
xtensa xtreg ar3 0x0103
|
||||
xtensa xtreg ar4 0x0104
|
||||
xtensa xtreg ar5 0x0105
|
||||
xtensa xtreg ar6 0x0106
|
||||
xtensa xtreg ar7 0x0107
|
||||
xtensa xtreg ar8 0x0108
|
||||
xtensa xtreg ar9 0x0109
|
||||
xtensa xtreg ar10 0x010a
|
||||
xtensa xtreg ar11 0x010b
|
||||
xtensa xtreg ar12 0x010c
|
||||
xtensa xtreg ar13 0x010d
|
||||
xtensa xtreg ar14 0x010e
|
||||
xtensa xtreg ar15 0x010f
|
||||
xtensa xtreg ar16 0x0110
|
||||
xtensa xtreg ar17 0x0111
|
||||
xtensa xtreg ar18 0x0112
|
||||
xtensa xtreg ar19 0x0113
|
||||
xtensa xtreg ar20 0x0114
|
||||
xtensa xtreg ar21 0x0115
|
||||
xtensa xtreg ar22 0x0116
|
||||
xtensa xtreg ar23 0x0117
|
||||
xtensa xtreg ar24 0x0118
|
||||
xtensa xtreg ar25 0x0119
|
||||
xtensa xtreg ar26 0x011a
|
||||
xtensa xtreg ar27 0x011b
|
||||
xtensa xtreg ar28 0x011c
|
||||
xtensa xtreg ar29 0x011d
|
||||
xtensa xtreg ar30 0x011e
|
||||
xtensa xtreg ar31 0x011f
|
||||
xtensa xtreg lbeg 0x0200
|
||||
xtensa xtreg lend 0x0201
|
||||
xtensa xtreg lcount 0x0202
|
||||
xtensa xtreg sar 0x0203
|
||||
xtensa xtreg prefctl 0x0228
|
||||
xtensa xtreg windowbase 0x0248
|
||||
xtensa xtreg windowstart 0x0249
|
||||
xtensa xtreg configid0 0x02b0
|
||||
xtensa xtreg configid1 0x02d0
|
||||
xtensa xtreg ps 0x02e6
|
||||
xtensa xtreg threadptr 0x03e7
|
||||
xtensa xtreg br 0x0204
|
||||
xtensa xtreg scompare1 0x020c
|
||||
xtensa xtreg acclo 0x0210
|
||||
xtensa xtreg acchi 0x0211
|
||||
xtensa xtreg m0 0x0220
|
||||
xtensa xtreg m1 0x0221
|
||||
xtensa xtreg m2 0x0222
|
||||
xtensa xtreg m3 0x0223
|
||||
xtensa xtreg expstate 0x03e6
|
||||
xtensa xtreg f64r_lo 0x03ea
|
||||
xtensa xtreg f64r_hi 0x03eb
|
||||
xtensa xtreg f64s 0x03ec
|
||||
xtensa xtreg ae_ovf_sar 0x03f0
|
||||
xtensa xtreg ae_bithead 0x03f1
|
||||
xtensa xtreg ae_ts_fts_bu_bp 0x03f2
|
||||
xtensa xtreg ae_cw_sd_no 0x03f3
|
||||
xtensa xtreg ae_cbegin0 0x03f6
|
||||
xtensa xtreg ae_cend0 0x03f7
|
||||
xtensa xtreg ae_cbegin1 0x03f8
|
||||
xtensa xtreg ae_cend1 0x03f9
|
||||
xtensa xtreg aed0 0x1010
|
||||
xtensa xtreg aed1 0x1011
|
||||
xtensa xtreg aed2 0x1012
|
||||
xtensa xtreg aed3 0x1013
|
||||
xtensa xtreg aed4 0x1014
|
||||
xtensa xtreg aed5 0x1015
|
||||
xtensa xtreg aed6 0x1016
|
||||
xtensa xtreg aed7 0x1017
|
||||
xtensa xtreg aed8 0x1018
|
||||
xtensa xtreg aed9 0x1019
|
||||
xtensa xtreg aed10 0x101a
|
||||
xtensa xtreg aed11 0x101b
|
||||
xtensa xtreg aed12 0x101c
|
||||
xtensa xtreg aed13 0x101d
|
||||
xtensa xtreg aed14 0x101e
|
||||
xtensa xtreg aed15 0x101f
|
||||
xtensa xtreg u0 0x1020
|
||||
xtensa xtreg u1 0x1021
|
||||
xtensa xtreg u2 0x1022
|
||||
xtensa xtreg u3 0x1023
|
||||
xtensa xtreg aep0 0x1024
|
||||
xtensa xtreg aep1 0x1025
|
||||
xtensa xtreg aep2 0x1026
|
||||
xtensa xtreg aep3 0x1027
|
||||
xtensa xtreg fcr_fsr 0x1029
|
||||
xtensa xtreg mmid 0x0259
|
||||
xtensa xtreg ibreakenable 0x0260
|
||||
xtensa xtreg memctl 0x0261
|
||||
xtensa xtreg atomctl 0x0263
|
||||
xtensa xtreg ddr 0x0268
|
||||
xtensa xtreg ibreaka0 0x0280
|
||||
xtensa xtreg ibreaka1 0x0281
|
||||
xtensa xtreg dbreaka0 0x0290
|
||||
xtensa xtreg dbreaka1 0x0291
|
||||
xtensa xtreg dbreakc0 0x02a0
|
||||
xtensa xtreg dbreakc1 0x02a1
|
||||
xtensa xtreg epc1 0x02b1
|
||||
xtensa xtreg epc2 0x02b2
|
||||
xtensa xtreg epc3 0x02b3
|
||||
xtensa xtreg epc4 0x02b4
|
||||
xtensa xtreg epc5 0x02b5
|
||||
xtensa xtreg depc 0x02c0
|
||||
xtensa xtreg eps2 0x02c2
|
||||
xtensa xtreg eps3 0x02c3
|
||||
xtensa xtreg eps4 0x02c4
|
||||
xtensa xtreg eps5 0x02c5
|
||||
xtensa xtreg excsave1 0x02d1
|
||||
xtensa xtreg excsave2 0x02d2
|
||||
xtensa xtreg excsave3 0x02d3
|
||||
xtensa xtreg excsave4 0x02d4
|
||||
xtensa xtreg excsave5 0x02d5
|
||||
xtensa xtreg cpenable 0x02e0
|
||||
xtensa xtreg interrupt 0x02e2
|
||||
xtensa xtreg intset 0x02e2
|
||||
xtensa xtreg intclear 0x02e3
|
||||
xtensa xtreg intenable 0x02e4
|
||||
xtensa xtreg vecbase 0x02e7
|
||||
xtensa xtreg exccause 0x02e8
|
||||
xtensa xtreg debugcause 0x02e9
|
||||
xtensa xtreg ccount 0x02ea
|
||||
xtensa xtreg prid 0x02eb
|
||||
xtensa xtreg icount 0x02ec
|
||||
xtensa xtreg icountlevel 0x02ed
|
||||
xtensa xtreg excvaddr 0x02ee
|
||||
xtensa xtreg ccompare0 0x02f0
|
||||
xtensa xtreg ccompare1 0x02f1
|
||||
xtensa xtreg misc0 0x02f4
|
||||
xtensa xtreg misc1 0x02f5
|
||||
xtensa xtreg pwrctl 0x2024
|
||||
xtensa xtreg pwrstat 0x2025
|
||||
xtensa xtreg eristat 0x2026
|
||||
xtensa xtreg cs_itctrl 0x2027
|
||||
xtensa xtreg cs_claimset 0x2028
|
||||
xtensa xtreg cs_claimclr 0x2029
|
||||
xtensa xtreg cs_lockaccess 0x202a
|
||||
xtensa xtreg cs_lockstatus 0x202b
|
||||
xtensa xtreg cs_authstatus 0x202c
|
||||
xtensa xtreg pmg 0x203b
|
||||
xtensa xtreg pmpc 0x203c
|
||||
xtensa xtreg pm0 0x203d
|
||||
xtensa xtreg pm1 0x203e
|
||||
xtensa xtreg pmctrl0 0x203f
|
||||
xtensa xtreg pmctrl1 0x2040
|
||||
xtensa xtreg pmstat0 0x2041
|
||||
xtensa xtreg pmstat1 0x2042
|
||||
xtensa xtreg ocdid 0x2043
|
||||
xtensa xtreg ocd_dcrclr 0x2044
|
||||
xtensa xtreg ocd_dcrset 0x2045
|
||||
xtensa xtreg ocd_dsr 0x2046
|
||||
xtensa xtreg a0 0x0000
|
||||
xtensa xtreg a1 0x0001
|
||||
xtensa xtreg a2 0x0002
|
||||
xtensa xtreg a3 0x0003
|
||||
xtensa xtreg a4 0x0004
|
||||
xtensa xtreg a5 0x0005
|
||||
xtensa xtreg a6 0x0006
|
||||
xtensa xtreg a7 0x0007
|
||||
xtensa xtreg a8 0x0008
|
||||
xtensa xtreg a9 0x0009
|
||||
xtensa xtreg a10 0x000a
|
||||
xtensa xtreg a11 0x000b
|
||||
xtensa xtreg a12 0x000c
|
||||
xtensa xtreg a13 0x000d
|
||||
xtensa xtreg a14 0x000e
|
||||
xtensa xtreg a15 0x000f
|
||||
xtensa xtreg b0 0x0010
|
||||
xtensa xtreg b1 0x0011
|
||||
xtensa xtreg b2 0x0012
|
||||
xtensa xtreg b3 0x0013
|
||||
xtensa xtreg b4 0x0014
|
||||
xtensa xtreg b5 0x0015
|
||||
xtensa xtreg b6 0x0016
|
||||
xtensa xtreg b7 0x0017
|
||||
xtensa xtreg b8 0x0018
|
||||
xtensa xtreg b9 0x0019
|
||||
xtensa xtreg b10 0x001a
|
||||
xtensa xtreg b11 0x001b
|
||||
xtensa xtreg b12 0x001c
|
||||
xtensa xtreg b13 0x001d
|
||||
xtensa xtreg b14 0x001e
|
||||
xtensa xtreg b15 0x001f
|
||||
xtensa xtreg psintlevel 0x2006
|
||||
xtensa xtreg psum 0x2007
|
||||
xtensa xtreg pswoe 0x2008
|
||||
xtensa xtreg psexcm 0x2009
|
||||
xtensa xtreg pscallinc 0x200a
|
||||
xtensa xtreg psowb 0x200b
|
||||
xtensa xtreg acc 0x200c
|
||||
xtensa xtreg dbnum 0x2011
|
||||
xtensa xtreg ae_overflow 0x2014
|
||||
xtensa xtreg ae_sar 0x2015
|
||||
xtensa xtreg ae_cwrap 0x2016
|
||||
xtensa xtreg ae_bitptr 0x2017
|
||||
xtensa xtreg ae_bitsused 0x2018
|
||||
xtensa xtreg ae_tablesize 0x2019
|
||||
xtensa xtreg ae_first_ts 0x201a
|
||||
xtensa xtreg ae_nextoffset 0x201b
|
||||
xtensa xtreg ae_searchdone 0x201c
|
||||
xtensa xtreg roundmode 0x201d
|
||||
xtensa xtreg invalidflag 0x201e
|
||||
xtensa xtreg divzeroflag 0x201f
|
||||
xtensa xtreg overflowflag 0x2020
|
||||
xtensa xtreg underflowflag 0x2021
|
||||
xtensa xtreg inexactflag 0x2022
|
||||
$_XTNAME xtensa xtregs 208
|
||||
$_XTNAME xtensa xtreg pc 0x0020
|
||||
$_XTNAME xtensa xtreg ar0 0x0100
|
||||
$_XTNAME xtensa xtreg ar1 0x0101
|
||||
$_XTNAME xtensa xtreg ar2 0x0102
|
||||
$_XTNAME xtensa xtreg ar3 0x0103
|
||||
$_XTNAME xtensa xtreg ar4 0x0104
|
||||
$_XTNAME xtensa xtreg ar5 0x0105
|
||||
$_XTNAME xtensa xtreg ar6 0x0106
|
||||
$_XTNAME xtensa xtreg ar7 0x0107
|
||||
$_XTNAME xtensa xtreg ar8 0x0108
|
||||
$_XTNAME xtensa xtreg ar9 0x0109
|
||||
$_XTNAME xtensa xtreg ar10 0x010a
|
||||
$_XTNAME xtensa xtreg ar11 0x010b
|
||||
$_XTNAME xtensa xtreg ar12 0x010c
|
||||
$_XTNAME xtensa xtreg ar13 0x010d
|
||||
$_XTNAME xtensa xtreg ar14 0x010e
|
||||
$_XTNAME xtensa xtreg ar15 0x010f
|
||||
$_XTNAME xtensa xtreg ar16 0x0110
|
||||
$_XTNAME xtensa xtreg ar17 0x0111
|
||||
$_XTNAME xtensa xtreg ar18 0x0112
|
||||
$_XTNAME xtensa xtreg ar19 0x0113
|
||||
$_XTNAME xtensa xtreg ar20 0x0114
|
||||
$_XTNAME xtensa xtreg ar21 0x0115
|
||||
$_XTNAME xtensa xtreg ar22 0x0116
|
||||
$_XTNAME xtensa xtreg ar23 0x0117
|
||||
$_XTNAME xtensa xtreg ar24 0x0118
|
||||
$_XTNAME xtensa xtreg ar25 0x0119
|
||||
$_XTNAME xtensa xtreg ar26 0x011a
|
||||
$_XTNAME xtensa xtreg ar27 0x011b
|
||||
$_XTNAME xtensa xtreg ar28 0x011c
|
||||
$_XTNAME xtensa xtreg ar29 0x011d
|
||||
$_XTNAME xtensa xtreg ar30 0x011e
|
||||
$_XTNAME xtensa xtreg ar31 0x011f
|
||||
$_XTNAME xtensa xtreg lbeg 0x0200
|
||||
$_XTNAME xtensa xtreg lend 0x0201
|
||||
$_XTNAME xtensa xtreg lcount 0x0202
|
||||
$_XTNAME xtensa xtreg sar 0x0203
|
||||
$_XTNAME xtensa xtreg prefctl 0x0228
|
||||
$_XTNAME xtensa xtreg windowbase 0x0248
|
||||
$_XTNAME xtensa xtreg windowstart 0x0249
|
||||
$_XTNAME xtensa xtreg configid0 0x02b0
|
||||
$_XTNAME xtensa xtreg configid1 0x02d0
|
||||
$_XTNAME xtensa xtreg ps 0x02e6
|
||||
$_XTNAME xtensa xtreg threadptr 0x03e7
|
||||
$_XTNAME xtensa xtreg br 0x0204
|
||||
$_XTNAME xtensa xtreg scompare1 0x020c
|
||||
$_XTNAME xtensa xtreg acclo 0x0210
|
||||
$_XTNAME xtensa xtreg acchi 0x0211
|
||||
$_XTNAME xtensa xtreg m0 0x0220
|
||||
$_XTNAME xtensa xtreg m1 0x0221
|
||||
$_XTNAME xtensa xtreg m2 0x0222
|
||||
$_XTNAME xtensa xtreg m3 0x0223
|
||||
$_XTNAME xtensa xtreg expstate 0x03e6
|
||||
$_XTNAME xtensa xtreg f64r_lo 0x03ea
|
||||
$_XTNAME xtensa xtreg f64r_hi 0x03eb
|
||||
$_XTNAME xtensa xtreg f64s 0x03ec
|
||||
$_XTNAME xtensa xtreg ae_ovf_sar 0x03f0
|
||||
$_XTNAME xtensa xtreg ae_bithead 0x03f1
|
||||
$_XTNAME xtensa xtreg ae_ts_fts_bu_bp 0x03f2
|
||||
$_XTNAME xtensa xtreg ae_cw_sd_no 0x03f3
|
||||
$_XTNAME xtensa xtreg ae_cbegin0 0x03f6
|
||||
$_XTNAME xtensa xtreg ae_cend0 0x03f7
|
||||
$_XTNAME xtensa xtreg ae_cbegin1 0x03f8
|
||||
$_XTNAME xtensa xtreg ae_cend1 0x03f9
|
||||
$_XTNAME xtensa xtreg aed0 0x1010
|
||||
$_XTNAME xtensa xtreg aed1 0x1011
|
||||
$_XTNAME xtensa xtreg aed2 0x1012
|
||||
$_XTNAME xtensa xtreg aed3 0x1013
|
||||
$_XTNAME xtensa xtreg aed4 0x1014
|
||||
$_XTNAME xtensa xtreg aed5 0x1015
|
||||
$_XTNAME xtensa xtreg aed6 0x1016
|
||||
$_XTNAME xtensa xtreg aed7 0x1017
|
||||
$_XTNAME xtensa xtreg aed8 0x1018
|
||||
$_XTNAME xtensa xtreg aed9 0x1019
|
||||
$_XTNAME xtensa xtreg aed10 0x101a
|
||||
$_XTNAME xtensa xtreg aed11 0x101b
|
||||
$_XTNAME xtensa xtreg aed12 0x101c
|
||||
$_XTNAME xtensa xtreg aed13 0x101d
|
||||
$_XTNAME xtensa xtreg aed14 0x101e
|
||||
$_XTNAME xtensa xtreg aed15 0x101f
|
||||
$_XTNAME xtensa xtreg u0 0x1020
|
||||
$_XTNAME xtensa xtreg u1 0x1021
|
||||
$_XTNAME xtensa xtreg u2 0x1022
|
||||
$_XTNAME xtensa xtreg u3 0x1023
|
||||
$_XTNAME xtensa xtreg aep0 0x1024
|
||||
$_XTNAME xtensa xtreg aep1 0x1025
|
||||
$_XTNAME xtensa xtreg aep2 0x1026
|
||||
$_XTNAME xtensa xtreg aep3 0x1027
|
||||
$_XTNAME xtensa xtreg fcr_fsr 0x1029
|
||||
$_XTNAME xtensa xtreg mmid 0x0259
|
||||
$_XTNAME xtensa xtreg ibreakenable 0x0260
|
||||
$_XTNAME xtensa xtreg memctl 0x0261
|
||||
$_XTNAME xtensa xtreg atomctl 0x0263
|
||||
$_XTNAME xtensa xtreg ddr 0x0268
|
||||
$_XTNAME xtensa xtreg ibreaka0 0x0280
|
||||
$_XTNAME xtensa xtreg ibreaka1 0x0281
|
||||
$_XTNAME xtensa xtreg dbreaka0 0x0290
|
||||
$_XTNAME xtensa xtreg dbreaka1 0x0291
|
||||
$_XTNAME xtensa xtreg dbreakc0 0x02a0
|
||||
$_XTNAME xtensa xtreg dbreakc1 0x02a1
|
||||
$_XTNAME xtensa xtreg epc1 0x02b1
|
||||
$_XTNAME xtensa xtreg epc2 0x02b2
|
||||
$_XTNAME xtensa xtreg epc3 0x02b3
|
||||
$_XTNAME xtensa xtreg epc4 0x02b4
|
||||
$_XTNAME xtensa xtreg epc5 0x02b5
|
||||
$_XTNAME xtensa xtreg depc 0x02c0
|
||||
$_XTNAME xtensa xtreg eps2 0x02c2
|
||||
$_XTNAME xtensa xtreg eps3 0x02c3
|
||||
$_XTNAME xtensa xtreg eps4 0x02c4
|
||||
$_XTNAME xtensa xtreg eps5 0x02c5
|
||||
$_XTNAME xtensa xtreg excsave1 0x02d1
|
||||
$_XTNAME xtensa xtreg excsave2 0x02d2
|
||||
$_XTNAME xtensa xtreg excsave3 0x02d3
|
||||
$_XTNAME xtensa xtreg excsave4 0x02d4
|
||||
$_XTNAME xtensa xtreg excsave5 0x02d5
|
||||
$_XTNAME xtensa xtreg cpenable 0x02e0
|
||||
$_XTNAME xtensa xtreg interrupt 0x02e2
|
||||
$_XTNAME xtensa xtreg intset 0x02e2
|
||||
$_XTNAME xtensa xtreg intclear 0x02e3
|
||||
$_XTNAME xtensa xtreg intenable 0x02e4
|
||||
$_XTNAME xtensa xtreg vecbase 0x02e7
|
||||
$_XTNAME xtensa xtreg exccause 0x02e8
|
||||
$_XTNAME xtensa xtreg debugcause 0x02e9
|
||||
$_XTNAME xtensa xtreg ccount 0x02ea
|
||||
$_XTNAME xtensa xtreg prid 0x02eb
|
||||
$_XTNAME xtensa xtreg icount 0x02ec
|
||||
$_XTNAME xtensa xtreg icountlevel 0x02ed
|
||||
$_XTNAME xtensa xtreg excvaddr 0x02ee
|
||||
$_XTNAME xtensa xtreg ccompare0 0x02f0
|
||||
$_XTNAME xtensa xtreg ccompare1 0x02f1
|
||||
$_XTNAME xtensa xtreg misc0 0x02f4
|
||||
$_XTNAME xtensa xtreg misc1 0x02f5
|
||||
$_XTNAME xtensa xtreg pwrctl 0x2024
|
||||
$_XTNAME xtensa xtreg pwrstat 0x2025
|
||||
$_XTNAME xtensa xtreg eristat 0x2026
|
||||
$_XTNAME xtensa xtreg cs_itctrl 0x2027
|
||||
$_XTNAME xtensa xtreg cs_claimset 0x2028
|
||||
$_XTNAME xtensa xtreg cs_claimclr 0x2029
|
||||
$_XTNAME xtensa xtreg cs_lockaccess 0x202a
|
||||
$_XTNAME xtensa xtreg cs_lockstatus 0x202b
|
||||
$_XTNAME xtensa xtreg cs_authstatus 0x202c
|
||||
$_XTNAME xtensa xtreg pmg 0x203b
|
||||
$_XTNAME xtensa xtreg pmpc 0x203c
|
||||
$_XTNAME xtensa xtreg pm0 0x203d
|
||||
$_XTNAME xtensa xtreg pm1 0x203e
|
||||
$_XTNAME xtensa xtreg pmctrl0 0x203f
|
||||
$_XTNAME xtensa xtreg pmctrl1 0x2040
|
||||
$_XTNAME xtensa xtreg pmstat0 0x2041
|
||||
$_XTNAME xtensa xtreg pmstat1 0x2042
|
||||
$_XTNAME xtensa xtreg ocdid 0x2043
|
||||
$_XTNAME xtensa xtreg ocd_dcrclr 0x2044
|
||||
$_XTNAME xtensa xtreg ocd_dcrset 0x2045
|
||||
$_XTNAME xtensa xtreg ocd_dsr 0x2046
|
||||
$_XTNAME xtensa xtreg a0 0x0000
|
||||
$_XTNAME xtensa xtreg a1 0x0001
|
||||
$_XTNAME xtensa xtreg a2 0x0002
|
||||
$_XTNAME xtensa xtreg a3 0x0003
|
||||
$_XTNAME xtensa xtreg a4 0x0004
|
||||
$_XTNAME xtensa xtreg a5 0x0005
|
||||
$_XTNAME xtensa xtreg a6 0x0006
|
||||
$_XTNAME xtensa xtreg a7 0x0007
|
||||
$_XTNAME xtensa xtreg a8 0x0008
|
||||
$_XTNAME xtensa xtreg a9 0x0009
|
||||
$_XTNAME xtensa xtreg a10 0x000a
|
||||
$_XTNAME xtensa xtreg a11 0x000b
|
||||
$_XTNAME xtensa xtreg a12 0x000c
|
||||
$_XTNAME xtensa xtreg a13 0x000d
|
||||
$_XTNAME xtensa xtreg a14 0x000e
|
||||
$_XTNAME xtensa xtreg a15 0x000f
|
||||
$_XTNAME xtensa xtreg b0 0x0010
|
||||
$_XTNAME xtensa xtreg b1 0x0011
|
||||
$_XTNAME xtensa xtreg b2 0x0012
|
||||
$_XTNAME xtensa xtreg b3 0x0013
|
||||
$_XTNAME xtensa xtreg b4 0x0014
|
||||
$_XTNAME xtensa xtreg b5 0x0015
|
||||
$_XTNAME xtensa xtreg b6 0x0016
|
||||
$_XTNAME xtensa xtreg b7 0x0017
|
||||
$_XTNAME xtensa xtreg b8 0x0018
|
||||
$_XTNAME xtensa xtreg b9 0x0019
|
||||
$_XTNAME xtensa xtreg b10 0x001a
|
||||
$_XTNAME xtensa xtreg b11 0x001b
|
||||
$_XTNAME xtensa xtreg b12 0x001c
|
||||
$_XTNAME xtensa xtreg b13 0x001d
|
||||
$_XTNAME xtensa xtreg b14 0x001e
|
||||
$_XTNAME xtensa xtreg b15 0x001f
|
||||
$_XTNAME xtensa xtreg psintlevel 0x2006
|
||||
$_XTNAME xtensa xtreg psum 0x2007
|
||||
$_XTNAME xtensa xtreg pswoe 0x2008
|
||||
$_XTNAME xtensa xtreg psexcm 0x2009
|
||||
$_XTNAME xtensa xtreg pscallinc 0x200a
|
||||
$_XTNAME xtensa xtreg psowb 0x200b
|
||||
$_XTNAME xtensa xtreg acc 0x200c
|
||||
$_XTNAME xtensa xtreg dbnum 0x2011
|
||||
$_XTNAME xtensa xtreg ae_overflow 0x2014
|
||||
$_XTNAME xtensa xtreg ae_sar 0x2015
|
||||
$_XTNAME xtensa xtreg ae_cwrap 0x2016
|
||||
$_XTNAME xtensa xtreg ae_bitptr 0x2017
|
||||
$_XTNAME xtensa xtreg ae_bitsused 0x2018
|
||||
$_XTNAME xtensa xtreg ae_tablesize 0x2019
|
||||
$_XTNAME xtensa xtreg ae_first_ts 0x201a
|
||||
$_XTNAME xtensa xtreg ae_nextoffset 0x201b
|
||||
$_XTNAME xtensa xtreg ae_searchdone 0x201c
|
||||
$_XTNAME xtensa xtreg roundmode 0x201d
|
||||
$_XTNAME xtensa xtreg invalidflag 0x201e
|
||||
$_XTNAME xtensa xtreg divzeroflag 0x201f
|
||||
$_XTNAME xtensa xtreg overflowflag 0x2020
|
||||
$_XTNAME xtensa xtreg underflowflag 0x2021
|
||||
$_XTNAME xtensa xtreg inexactflag 0x2022
|
||||
|
|
|
|||
|
|
@ -1,166 +1,175 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# OpenOCD configuration file for Xtensa xt8 target
|
||||
|
||||
|
||||
# Core instance default definition
|
||||
if { [info exists XTNAME] } {
|
||||
set _XTNAME $XTNAME
|
||||
} else {
|
||||
set _XTNAME xtensa
|
||||
}
|
||||
|
||||
|
||||
# Core definition and ABI
|
||||
xtensa xtdef LX
|
||||
xtensa xtopt arnum 32
|
||||
xtensa xtopt windowed 1
|
||||
$_XTNAME xtensa xtdef LX
|
||||
$_XTNAME xtensa xtopt arnum 32
|
||||
$_XTNAME xtensa xtopt windowed 1
|
||||
|
||||
|
||||
# Exception/Interrupt Options
|
||||
xtensa xtopt exceptions 1
|
||||
xtensa xtopt hipriints 1
|
||||
xtensa xtopt intlevels 3
|
||||
xtensa xtopt excmlevel 1
|
||||
$_XTNAME xtensa xtopt exceptions 1
|
||||
$_XTNAME xtensa xtopt hipriints 1
|
||||
$_XTNAME xtensa xtopt intlevels 3
|
||||
$_XTNAME xtensa xtopt excmlevel 1
|
||||
|
||||
|
||||
# Cache Options
|
||||
xtensa xtmem icache 16 1024 1
|
||||
xtensa xtmem dcache 16 1024 1 1
|
||||
$_XTNAME xtensa xtmem icache 16 1024 1
|
||||
$_XTNAME xtensa xtmem dcache 16 1024 1 1
|
||||
|
||||
|
||||
# Memory Options
|
||||
xtensa xtmem iram 0x40000000 1048576
|
||||
xtensa xtmem dram 0x3ff00000 262144
|
||||
xtensa xtmem srom 0x50000000 131072
|
||||
xtensa xtmem sram 0x60000000 4194304
|
||||
$_XTNAME xtensa xtmem iram 0x40000000 1048576
|
||||
$_XTNAME xtensa xtmem dram 0x3ff00000 262144
|
||||
$_XTNAME xtensa xtmem srom 0x50000000 131072
|
||||
$_XTNAME xtensa xtmem sram 0x60000000 4194304
|
||||
|
||||
|
||||
# Memory Protection/Translation Options
|
||||
|
||||
|
||||
# Debug Options
|
||||
xtensa xtopt debuglevel 3
|
||||
xtensa xtopt ibreaknum 2
|
||||
xtensa xtopt dbreaknum 2
|
||||
$_XTNAME xtensa xtopt debuglevel 3
|
||||
$_XTNAME xtensa xtopt ibreaknum 2
|
||||
$_XTNAME xtensa xtopt dbreaknum 2
|
||||
|
||||
|
||||
# Core Registers
|
||||
xtensa xtregs 127
|
||||
xtensa xtreg a0 0x0000
|
||||
xtensa xtreg a1 0x0001
|
||||
xtensa xtreg a2 0x0002
|
||||
xtensa xtreg a3 0x0003
|
||||
xtensa xtreg a4 0x0004
|
||||
xtensa xtreg a5 0x0005
|
||||
xtensa xtreg a6 0x0006
|
||||
xtensa xtreg a7 0x0007
|
||||
xtensa xtreg a8 0x0008
|
||||
xtensa xtreg a9 0x0009
|
||||
xtensa xtreg a10 0x000a
|
||||
xtensa xtreg a11 0x000b
|
||||
xtensa xtreg a12 0x000c
|
||||
xtensa xtreg a13 0x000d
|
||||
xtensa xtreg a14 0x000e
|
||||
xtensa xtreg a15 0x000f
|
||||
xtensa xtreg pc 0x0020
|
||||
xtensa xtreg ar0 0x0100
|
||||
xtensa xtreg ar1 0x0101
|
||||
xtensa xtreg ar2 0x0102
|
||||
xtensa xtreg ar3 0x0103
|
||||
xtensa xtreg ar4 0x0104
|
||||
xtensa xtreg ar5 0x0105
|
||||
xtensa xtreg ar6 0x0106
|
||||
xtensa xtreg ar7 0x0107
|
||||
xtensa xtreg ar8 0x0108
|
||||
xtensa xtreg ar9 0x0109
|
||||
xtensa xtreg ar10 0x010a
|
||||
xtensa xtreg ar11 0x010b
|
||||
xtensa xtreg ar12 0x010c
|
||||
xtensa xtreg ar13 0x010d
|
||||
xtensa xtreg ar14 0x010e
|
||||
xtensa xtreg ar15 0x010f
|
||||
xtensa xtreg ar16 0x0110
|
||||
xtensa xtreg ar17 0x0111
|
||||
xtensa xtreg ar18 0x0112
|
||||
xtensa xtreg ar19 0x0113
|
||||
xtensa xtreg ar20 0x0114
|
||||
xtensa xtreg ar21 0x0115
|
||||
xtensa xtreg ar22 0x0116
|
||||
xtensa xtreg ar23 0x0117
|
||||
xtensa xtreg ar24 0x0118
|
||||
xtensa xtreg ar25 0x0119
|
||||
xtensa xtreg ar26 0x011a
|
||||
xtensa xtreg ar27 0x011b
|
||||
xtensa xtreg ar28 0x011c
|
||||
xtensa xtreg ar29 0x011d
|
||||
xtensa xtreg ar30 0x011e
|
||||
xtensa xtreg ar31 0x011f
|
||||
xtensa xtreg lbeg 0x0200
|
||||
xtensa xtreg lend 0x0201
|
||||
xtensa xtreg lcount 0x0202
|
||||
xtensa xtreg sar 0x0203
|
||||
xtensa xtreg windowbase 0x0248
|
||||
xtensa xtreg windowstart 0x0249
|
||||
xtensa xtreg configid0 0x02b0
|
||||
xtensa xtreg configid1 0x02d0
|
||||
xtensa xtreg ps 0x02e6
|
||||
xtensa xtreg expstate 0x03e6
|
||||
xtensa xtreg mmid 0x0259
|
||||
xtensa xtreg ibreakenable 0x0260
|
||||
xtensa xtreg ddr 0x0268
|
||||
xtensa xtreg ibreaka0 0x0280
|
||||
xtensa xtreg ibreaka1 0x0281
|
||||
xtensa xtreg dbreaka0 0x0290
|
||||
xtensa xtreg dbreaka1 0x0291
|
||||
xtensa xtreg dbreakc0 0x02a0
|
||||
xtensa xtreg dbreakc1 0x02a1
|
||||
xtensa xtreg epc1 0x02b1
|
||||
xtensa xtreg epc2 0x02b2
|
||||
xtensa xtreg epc3 0x02b3
|
||||
xtensa xtreg depc 0x02c0
|
||||
xtensa xtreg eps2 0x02c2
|
||||
xtensa xtreg eps3 0x02c3
|
||||
xtensa xtreg excsave1 0x02d1
|
||||
xtensa xtreg excsave2 0x02d2
|
||||
xtensa xtreg excsave3 0x02d3
|
||||
xtensa xtreg interrupt 0x02e2
|
||||
xtensa xtreg intset 0x02e2
|
||||
xtensa xtreg intclear 0x02e3
|
||||
xtensa xtreg intenable 0x02e4
|
||||
xtensa xtreg exccause 0x02e8
|
||||
xtensa xtreg debugcause 0x02e9
|
||||
xtensa xtreg ccount 0x02ea
|
||||
xtensa xtreg icount 0x02ec
|
||||
xtensa xtreg icountlevel 0x02ed
|
||||
xtensa xtreg excvaddr 0x02ee
|
||||
xtensa xtreg ccompare0 0x02f0
|
||||
xtensa xtreg ccompare1 0x02f1
|
||||
xtensa xtreg pwrctl 0x200f
|
||||
xtensa xtreg pwrstat 0x2010
|
||||
xtensa xtreg eristat 0x2011
|
||||
xtensa xtreg cs_itctrl 0x2012
|
||||
xtensa xtreg cs_claimset 0x2013
|
||||
xtensa xtreg cs_claimclr 0x2014
|
||||
xtensa xtreg cs_lockaccess 0x2015
|
||||
xtensa xtreg cs_lockstatus 0x2016
|
||||
xtensa xtreg cs_authstatus 0x2017
|
||||
xtensa xtreg fault_info 0x2026
|
||||
xtensa xtreg trax_id 0x2027
|
||||
xtensa xtreg trax_control 0x2028
|
||||
xtensa xtreg trax_status 0x2029
|
||||
xtensa xtreg trax_data 0x202a
|
||||
xtensa xtreg trax_address 0x202b
|
||||
xtensa xtreg trax_pctrigger 0x202c
|
||||
xtensa xtreg trax_pcmatch 0x202d
|
||||
xtensa xtreg trax_delay 0x202e
|
||||
xtensa xtreg trax_memstart 0x202f
|
||||
xtensa xtreg trax_memend 0x2030
|
||||
xtensa xtreg pmg 0x203e
|
||||
xtensa xtreg pmpc 0x203f
|
||||
xtensa xtreg pm0 0x2040
|
||||
xtensa xtreg pm1 0x2041
|
||||
xtensa xtreg pmctrl0 0x2042
|
||||
xtensa xtreg pmctrl1 0x2043
|
||||
xtensa xtreg pmstat0 0x2044
|
||||
xtensa xtreg pmstat1 0x2045
|
||||
xtensa xtreg ocdid 0x2046
|
||||
xtensa xtreg ocd_dcrclr 0x2047
|
||||
xtensa xtreg ocd_dcrset 0x2048
|
||||
xtensa xtreg ocd_dsr 0x2049
|
||||
xtensa xtreg psintlevel 0x2003
|
||||
xtensa xtreg psum 0x2004
|
||||
xtensa xtreg pswoe 0x2005
|
||||
xtensa xtreg psexcm 0x2006
|
||||
xtensa xtreg pscallinc 0x2007
|
||||
xtensa xtreg psowb 0x2008
|
||||
$_XTNAME xtensa xtregs 127
|
||||
$_XTNAME xtensa xtreg a0 0x0000
|
||||
$_XTNAME xtensa xtreg a1 0x0001
|
||||
$_XTNAME xtensa xtreg a2 0x0002
|
||||
$_XTNAME xtensa xtreg a3 0x0003
|
||||
$_XTNAME xtensa xtreg a4 0x0004
|
||||
$_XTNAME xtensa xtreg a5 0x0005
|
||||
$_XTNAME xtensa xtreg a6 0x0006
|
||||
$_XTNAME xtensa xtreg a7 0x0007
|
||||
$_XTNAME xtensa xtreg a8 0x0008
|
||||
$_XTNAME xtensa xtreg a9 0x0009
|
||||
$_XTNAME xtensa xtreg a10 0x000a
|
||||
$_XTNAME xtensa xtreg a11 0x000b
|
||||
$_XTNAME xtensa xtreg a12 0x000c
|
||||
$_XTNAME xtensa xtreg a13 0x000d
|
||||
$_XTNAME xtensa xtreg a14 0x000e
|
||||
$_XTNAME xtensa xtreg a15 0x000f
|
||||
$_XTNAME xtensa xtreg pc 0x0020
|
||||
$_XTNAME xtensa xtreg ar0 0x0100
|
||||
$_XTNAME xtensa xtreg ar1 0x0101
|
||||
$_XTNAME xtensa xtreg ar2 0x0102
|
||||
$_XTNAME xtensa xtreg ar3 0x0103
|
||||
$_XTNAME xtensa xtreg ar4 0x0104
|
||||
$_XTNAME xtensa xtreg ar5 0x0105
|
||||
$_XTNAME xtensa xtreg ar6 0x0106
|
||||
$_XTNAME xtensa xtreg ar7 0x0107
|
||||
$_XTNAME xtensa xtreg ar8 0x0108
|
||||
$_XTNAME xtensa xtreg ar9 0x0109
|
||||
$_XTNAME xtensa xtreg ar10 0x010a
|
||||
$_XTNAME xtensa xtreg ar11 0x010b
|
||||
$_XTNAME xtensa xtreg ar12 0x010c
|
||||
$_XTNAME xtensa xtreg ar13 0x010d
|
||||
$_XTNAME xtensa xtreg ar14 0x010e
|
||||
$_XTNAME xtensa xtreg ar15 0x010f
|
||||
$_XTNAME xtensa xtreg ar16 0x0110
|
||||
$_XTNAME xtensa xtreg ar17 0x0111
|
||||
$_XTNAME xtensa xtreg ar18 0x0112
|
||||
$_XTNAME xtensa xtreg ar19 0x0113
|
||||
$_XTNAME xtensa xtreg ar20 0x0114
|
||||
$_XTNAME xtensa xtreg ar21 0x0115
|
||||
$_XTNAME xtensa xtreg ar22 0x0116
|
||||
$_XTNAME xtensa xtreg ar23 0x0117
|
||||
$_XTNAME xtensa xtreg ar24 0x0118
|
||||
$_XTNAME xtensa xtreg ar25 0x0119
|
||||
$_XTNAME xtensa xtreg ar26 0x011a
|
||||
$_XTNAME xtensa xtreg ar27 0x011b
|
||||
$_XTNAME xtensa xtreg ar28 0x011c
|
||||
$_XTNAME xtensa xtreg ar29 0x011d
|
||||
$_XTNAME xtensa xtreg ar30 0x011e
|
||||
$_XTNAME xtensa xtreg ar31 0x011f
|
||||
$_XTNAME xtensa xtreg lbeg 0x0200
|
||||
$_XTNAME xtensa xtreg lend 0x0201
|
||||
$_XTNAME xtensa xtreg lcount 0x0202
|
||||
$_XTNAME xtensa xtreg sar 0x0203
|
||||
$_XTNAME xtensa xtreg windowbase 0x0248
|
||||
$_XTNAME xtensa xtreg windowstart 0x0249
|
||||
$_XTNAME xtensa xtreg configid0 0x02b0
|
||||
$_XTNAME xtensa xtreg configid1 0x02d0
|
||||
$_XTNAME xtensa xtreg ps 0x02e6
|
||||
$_XTNAME xtensa xtreg expstate 0x03e6
|
||||
$_XTNAME xtensa xtreg mmid 0x0259
|
||||
$_XTNAME xtensa xtreg ibreakenable 0x0260
|
||||
$_XTNAME xtensa xtreg ddr 0x0268
|
||||
$_XTNAME xtensa xtreg ibreaka0 0x0280
|
||||
$_XTNAME xtensa xtreg ibreaka1 0x0281
|
||||
$_XTNAME xtensa xtreg dbreaka0 0x0290
|
||||
$_XTNAME xtensa xtreg dbreaka1 0x0291
|
||||
$_XTNAME xtensa xtreg dbreakc0 0x02a0
|
||||
$_XTNAME xtensa xtreg dbreakc1 0x02a1
|
||||
$_XTNAME xtensa xtreg epc1 0x02b1
|
||||
$_XTNAME xtensa xtreg epc2 0x02b2
|
||||
$_XTNAME xtensa xtreg epc3 0x02b3
|
||||
$_XTNAME xtensa xtreg depc 0x02c0
|
||||
$_XTNAME xtensa xtreg eps2 0x02c2
|
||||
$_XTNAME xtensa xtreg eps3 0x02c3
|
||||
$_XTNAME xtensa xtreg excsave1 0x02d1
|
||||
$_XTNAME xtensa xtreg excsave2 0x02d2
|
||||
$_XTNAME xtensa xtreg excsave3 0x02d3
|
||||
$_XTNAME xtensa xtreg interrupt 0x02e2
|
||||
$_XTNAME xtensa xtreg intset 0x02e2
|
||||
$_XTNAME xtensa xtreg intclear 0x02e3
|
||||
$_XTNAME xtensa xtreg intenable 0x02e4
|
||||
$_XTNAME xtensa xtreg exccause 0x02e8
|
||||
$_XTNAME xtensa xtreg debugcause 0x02e9
|
||||
$_XTNAME xtensa xtreg ccount 0x02ea
|
||||
$_XTNAME xtensa xtreg icount 0x02ec
|
||||
$_XTNAME xtensa xtreg icountlevel 0x02ed
|
||||
$_XTNAME xtensa xtreg excvaddr 0x02ee
|
||||
$_XTNAME xtensa xtreg ccompare0 0x02f0
|
||||
$_XTNAME xtensa xtreg ccompare1 0x02f1
|
||||
$_XTNAME xtensa xtreg pwrctl 0x200f
|
||||
$_XTNAME xtensa xtreg pwrstat 0x2010
|
||||
$_XTNAME xtensa xtreg eristat 0x2011
|
||||
$_XTNAME xtensa xtreg cs_itctrl 0x2012
|
||||
$_XTNAME xtensa xtreg cs_claimset 0x2013
|
||||
$_XTNAME xtensa xtreg cs_claimclr 0x2014
|
||||
$_XTNAME xtensa xtreg cs_lockaccess 0x2015
|
||||
$_XTNAME xtensa xtreg cs_lockstatus 0x2016
|
||||
$_XTNAME xtensa xtreg cs_authstatus 0x2017
|
||||
$_XTNAME xtensa xtreg fault_info 0x2026
|
||||
$_XTNAME xtensa xtreg trax_id 0x2027
|
||||
$_XTNAME xtensa xtreg trax_control 0x2028
|
||||
$_XTNAME xtensa xtreg trax_status 0x2029
|
||||
$_XTNAME xtensa xtreg trax_data 0x202a
|
||||
$_XTNAME xtensa xtreg trax_address 0x202b
|
||||
$_XTNAME xtensa xtreg trax_pctrigger 0x202c
|
||||
$_XTNAME xtensa xtreg trax_pcmatch 0x202d
|
||||
$_XTNAME xtensa xtreg trax_delay 0x202e
|
||||
$_XTNAME xtensa xtreg trax_memstart 0x202f
|
||||
$_XTNAME xtensa xtreg trax_memend 0x2030
|
||||
$_XTNAME xtensa xtreg pmg 0x203e
|
||||
$_XTNAME xtensa xtreg pmpc 0x203f
|
||||
$_XTNAME xtensa xtreg pm0 0x2040
|
||||
$_XTNAME xtensa xtreg pm1 0x2041
|
||||
$_XTNAME xtensa xtreg pmctrl0 0x2042
|
||||
$_XTNAME xtensa xtreg pmctrl1 0x2043
|
||||
$_XTNAME xtensa xtreg pmstat0 0x2044
|
||||
$_XTNAME xtensa xtreg pmstat1 0x2045
|
||||
$_XTNAME xtensa xtreg ocdid 0x2046
|
||||
$_XTNAME xtensa xtreg ocd_dcrclr 0x2047
|
||||
$_XTNAME xtensa xtreg ocd_dcrset 0x2048
|
||||
$_XTNAME xtensa xtreg ocd_dsr 0x2049
|
||||
$_XTNAME xtensa xtreg psintlevel 0x2003
|
||||
$_XTNAME xtensa xtreg psum 0x2004
|
||||
$_XTNAME xtensa xtreg pswoe 0x2005
|
||||
$_XTNAME xtensa xtreg psexcm 0x2006
|
||||
$_XTNAME xtensa xtreg pscallinc 0x2007
|
||||
$_XTNAME xtensa xtreg psowb 0x2008
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
set xtensa_ids { 0x120034e5 0x120134e5
|
||||
0x209034e5 0x209134e5 0x209234e5 0x209334e5 0x209434e5 0x209534e5 0x209634e5 0x209734e5
|
||||
0x20a034e5 0x20a134e5 0x20a234e5 0x20a334e5 0x20a434e5 0x20a534e5 0x20a634e5 0x20a734e5 0x20a834e5
|
||||
0x20b034e5 }
|
||||
0x20b034e5 0x20b33ac5 0x20b33ac7 }
|
||||
set expected_xtensa_ids {}
|
||||
foreach i $xtensa_ids {
|
||||
lappend expected_xtensa_ids -expected-id $i
|
||||
|
|
@ -23,6 +23,12 @@ if { [info exists CPUTAPID] } {
|
|||
set _CPUTAPARGLIST [join $expected_xtensa_ids]
|
||||
}
|
||||
|
||||
if { [info exists XTENSA_NUM_CORES] } {
|
||||
set _XTENSA_NUM_CORES $XTENSA_NUM_CORES
|
||||
} else {
|
||||
set _XTENSA_NUM_CORES 1
|
||||
}
|
||||
|
||||
set _TARGETNAME $_CHIPNAME
|
||||
set _CPU0NAME cpu
|
||||
set _TAPNAME $_CHIPNAME.$_CPU0NAME
|
||||
|
|
@ -40,12 +46,25 @@ if { [info exists XTENSA_DAP] } {
|
|||
} else {
|
||||
target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap
|
||||
}
|
||||
} else {
|
||||
} elseif { $_XTENSA_NUM_CORES > 1 } {
|
||||
# JTAG direct (without DAP)
|
||||
for {set i 0} {$i < $_XTENSA_NUM_CORES} {incr i} {
|
||||
set _LCPUNAME $_CPU0NAME$i
|
||||
set _LTAPNAME $_CHIPNAME.$_LCPUNAME
|
||||
eval jtag newtap $_CHIPNAME $_LCPUNAME -irlen 5 $_CPUTAPARGLIST
|
||||
target create $_LTAPNAME xtensa -chain-position $_LTAPNAME -coreid $i
|
||||
|
||||
$_LTAPNAME configure -event reset-assert-post { soft_reset_halt }
|
||||
}
|
||||
} else {
|
||||
# JTAG direct (without DAP) - for legacy xtensa-config-XXX.cfg format
|
||||
eval jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 $_CPUTAPARGLIST
|
||||
target create $_TARGETNAME xtensa -chain-position $_TAPNAME
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
|
||||
if { $_XTENSA_NUM_CORES == 1 } {
|
||||
# DAP and single-core legacy JTAG
|
||||
$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
|
||||
}
|
||||
|
||||
gdb_report_register_access_error enable
|
||||
|
|
|
|||
Loading…
Reference in New Issue