target/mips32: optimize pracc access
Update mips32 instructions, add barrier and sync related insts. Add SYNC and barrier instruction blocks for memory access safety. These instructions are not supported on Lexra and/or MIPSr1 CPUs, detections were added and they will be executed conditionally. Rework mips32_pracc_read/write_regs function. Checkpatch-ignore: MACRO_ARG_REUSE Change-Id: Ib14112f37ff1f060b1633df73d671a6b09bb2178 Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7865 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Walter Ji
Antonio Borneo
parent
019bf5f83c
commit
b123128737
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@ -796,6 +796,44 @@ static const struct cpu_entry *mips32_find_cpu_by_prid(uint32_t prid)
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return &mips32_cpu_entry[MIPS32_NUM_CPU_ENTRIES - 1];
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}
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static bool mips32_cpu_is_lexra(struct mips_ejtag *ejtag_info)
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{
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return (ejtag_info->prid & PRID_COMP_MASK) == PRID_COMP_LEXRA;
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}
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static int mips32_cpu_get_release(struct mips_ejtag *ejtag_info)
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{
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return (ejtag_info->config[0] & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
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}
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/**
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* mips32_cpu_support_sync - Checks CPU supports ordering
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* @param[in] ejtag_info: MIPS EJTAG information structure.
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*
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* @brief MIPS ISA implemented on Lexra CPUs is MIPS-I, similar to R3000,
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* which does not have the SYNC instruction alone with unaligned
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* load/store instructions.
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*
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* @returns true if current CPU supports sync instruction(CPU is not Lexra)
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*/
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bool mips32_cpu_support_sync(struct mips_ejtag *ejtag_info)
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{
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return !mips32_cpu_is_lexra(ejtag_info);
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}
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/**
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* mips32_cpu_support_hazard_barrier - Checks CPU supports hazard barrier
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* @param[in] ejtag_info: MIPS EJTAG information structure.
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*
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* @brief hazard barrier instructions EHB and *.HB was introduced to MIPS from release 2.
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*
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* @returns true if current CPU supports hazard barrier(release > 1)
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*/
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bool mips32_cpu_support_hazard_barrier(struct mips_ejtag *ejtag_info)
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{
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return mips32_cpu_get_release(ejtag_info) > MIPS32_RELEASE_1;
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}
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/**
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* mips32_cpu_probe - Detects processor type and applies necessary quirks.
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* @param[in] target: The target CPU to probe.
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@ -454,6 +454,7 @@ struct mips32_algorithm {
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#define MIPS32_OP_BEQ 0x04u
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#define MIPS32_OP_BGTZ 0x07u
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#define MIPS32_OP_BNE 0x05u
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#define MIPS32_OP_ADD 0x20u
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#define MIPS32_OP_ADDI 0x08u
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#define MIPS32_OP_AND 0x24u
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#define MIPS32_OP_CACHE 0x2Fu
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@ -481,6 +482,7 @@ struct mips32_algorithm {
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#define MIPS32_OP_SRA 0x03u
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#define MIPS32_OP_SYNCI 0x1Fu
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#define MIPS32_OP_SLL 0x00u
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#define MIPS32_OP_SLLV 0x04u
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#define MIPS32_OP_SLTI 0x0Au
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#define MIPS32_OP_MOVN 0x0Bu
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@ -490,8 +492,11 @@ struct mips32_algorithm {
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#define MIPS32_OP_SPECIAL2 0x07u
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#define MIPS32_OP_SPECIAL3 0x1Fu
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#define MIPS32_COP0_MF 0x00u
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#define MIPS32_COP0_MT 0x04u
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#define MIPS32_COP_MF 0x00u
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#define MIPS32_COP_CF 0x02u
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#define MIPS32_COP_MFH 0x03u
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#define MIPS32_COP_MT 0x04u
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#define MIPS32_COP_MTH 0x07u
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#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) \
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(((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | ((rd) << 11) | ((shamt) << 6) | (funct))
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@ -500,6 +505,7 @@ struct mips32_algorithm {
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#define MIPS32_J_INST(opcode, addr) (((opcode) << 26) | (addr))
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#define MIPS32_ISA_NOP 0
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#define MIPS32_ISA_ADD(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADD)
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#define MIPS32_ISA_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
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#define MIPS32_ISA_ADDIU(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDIU, src, tar, val)
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#define MIPS32_ISA_ADDU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDU)
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@ -513,6 +519,7 @@ struct mips32_algorithm {
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#define MIPS32_ISA_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off)
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#define MIPS32_ISA_J(tar) MIPS32_J_INST(MIPS32_OP_J, (0x0FFFFFFFu & (tar)) >> 2)
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#define MIPS32_ISA_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
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#define MIPS32_ISA_JRHB(reg) MIPS32_R_INST(0, reg, 0, 0, 0x10, MIPS32_OP_JR)
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#define MIPS32_ISA_LB(reg, off, base) MIPS32_I_INST(MIPS32_OP_LB, base, reg, off)
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#define MIPS32_ISA_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
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@ -520,14 +527,16 @@ struct mips32_algorithm {
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#define MIPS32_ISA_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
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#define MIPS32_ISA_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
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#define MIPS32_ISA_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
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#define MIPS32_ISA_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
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#define MIPS32_ISA_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MF, gpr, cpr, 0, sel)
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#define MIPS32_ISA_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MT, gpr, cpr, 0, sel)
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#define MIPS32_ISA_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
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#define MIPS32_ISA_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
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#define MIPS32_ISA_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
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#define MIPS32_ISA_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
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#define MIPS32_ISA_MUL(dst, src, t) MIPS32_R_INST(28, src, t, dst, 0, MIPS32_OP_MUL)
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#define MIPS32_ISA_MOVN(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_MOVN)
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#define MIPS32_ISA_OR(dst, src, val) MIPS32_R_INST(0, src, val, dst, 0, 37)
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#define MIPS32_ISA_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
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#define MIPS32_ISA_RDHWR(tar, dst) MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR)
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#define MIPS32_ISA_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
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@ -535,6 +544,7 @@ struct mips32_algorithm {
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#define MIPS32_ISA_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
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#define MIPS32_ISA_SLL(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL)
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#define MIPS32_ISA_SLLV(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLLV)
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#define MIPS32_ISA_SLTI(tar, src, val) MIPS32_I_INST(MIPS32_OP_SLTI, src, tar, val)
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#define MIPS32_ISA_SLTU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU)
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#define MIPS32_ISA_SRA(reg, src, off) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRA)
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@ -563,10 +573,12 @@ struct mips32_algorithm {
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#define MIPS16_ISA_SDBBP 0xE801u
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/*MICRO MIPS INSTRUCTIONS, see doc MD00582 */
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#define POOL32A 0X00u
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#define POOL32AXF 0x3Cu
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#define POOL32B 0x08u
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#define POOL32I 0x10u
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#define MMIPS32_POOL32A 0x00u
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#define MMIPS32_POOL32F 0x15u
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#define MMIPS32_POOL32FXF 0x3Bu
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#define MMIPS32_POOL32AXF 0x3Cu
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#define MMIPS32_POOL32B 0x08u
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#define MMIPS32_POOL32I 0x10u
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#define MMIPS32_OP_ADDI 0x04u
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#define MMIPS32_OP_ADDIU 0x0Cu
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#define MMIPS32_OP_ADDU 0x150u
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@ -578,6 +590,7 @@ struct mips32_algorithm {
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#define MMIPS32_OP_CACHE 0x06u
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#define MMIPS32_OP_J 0x35u
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#define MMIPS32_OP_JALR 0x03Cu
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#define MMIPS32_OP_JALRHB 0x07Cu
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#define MMIPS32_OP_LB 0x07u
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#define MMIPS32_OP_LBU 0x05u
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#define MMIPS32_OP_LHU 0x0Du
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@ -605,55 +618,59 @@ struct mips32_algorithm {
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#define MMIPS32_ADDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDI, tar, src, val)
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#define MMIPS32_ADDIU(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDIU, tar, src, val)
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#define MMIPS32_ADDU(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU)
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#define MMIPS32_AND(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_AND)
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#define MMIPS32_ADDU(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU)
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#define MMIPS32_AND(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_AND)
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#define MMIPS32_ANDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ANDI, tar, src, val)
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#define MMIPS32_B(off) MMIPS32_BEQ(0, 0, off)
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#define MMIPS32_BEQ(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BEQ, tar, src, off)
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#define MMIPS32_BGTZ(reg, off) MIPS32_I_INST(POOL32I, MMIPS32_OP_BGTZ, reg, off)
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#define MMIPS32_BGTZ(reg, off) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_BGTZ, reg, off)
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#define MMIPS32_BNE(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BNE, tar, src, off)
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#define MMIPS32_CACHE(op, off, base) MIPS32_R_INST(POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)
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#define MMIPS32_CACHE(op, off, base) MIPS32_R_INST(MMIPS32_POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)
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#define MMIPS32_J(tar) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1))))
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#define MMIPS32_JR(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXF)
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#define MMIPS32_JR(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALR, MMIPS32_POOL32AXF)
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#define MMIPS32_JRHB(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALRHB, MMIPS32_POOL32AXF)
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#define MMIPS32_LB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off)
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#define MMIPS32_LBU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off)
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#define MMIPS32_LHU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off)
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#define MMIPS32_LUI(reg, val) MIPS32_I_INST(POOL32I, MMIPS32_OP_LUI, reg, val)
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#define MMIPS32_LUI(reg, val) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_LUI, reg, val)
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#define MMIPS32_LW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off)
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#define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXF)
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#define MMIPS32_MFLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXF)
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#define MMIPS32_MFHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXF)
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#define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXF)
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#define MMIPS32_MTLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXF)
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#define MMIPS32_MTHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXF)
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#define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\
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MMIPS32_OP_MFC0, MMIPS32_POOL32AXF)
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#define MMIPS32_MFLO(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, MMIPS32_POOL32AXF)
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#define MMIPS32_MFHI(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, MMIPS32_POOL32AXF)
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#define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\
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MMIPS32_OP_MTC0, MMIPS32_POOL32AXF)
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#define MMIPS32_MTLO(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, MMIPS32_POOL32AXF)
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#define MMIPS32_MTHI(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, MMIPS32_POOL32AXF)
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#define MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN)
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#define MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN)
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#define MMIPS32_NOP 0
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#define MMIPS32_ORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val)
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#define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXF)
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#define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(MMIPS32_POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, MMIPS32_POOL32AXF)
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#define MMIPS32_SB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off)
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#define MMIPS32_SH(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off)
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#define MMIPS32_SW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off)
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#define MMIPS32_SRL(reg, src, off) MIPS32_R_INST(POOL32A, reg, src, off, 0, MMIPS32_OP_SRL)
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#define MMIPS32_SLTU(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU)
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#define MMIPS32_SYNCI(off, base) MIPS32_I_INST(POOL32I, MMIPS32_OP_SYNCI, base, off)
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#define MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL)
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#define MMIPS32_SRL(reg, src, off) MIPS32_R_INST(MMIPS32_POOL32A, reg, src, off, 0, MMIPS32_OP_SRL)
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#define MMIPS32_SLTU(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU)
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#define MMIPS32_SYNCI(off, base) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_SYNCI, base, off)
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#define MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL)
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#define MMIPS32_SLLV(dst, src, sa) MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLLV)
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#define MMIPS32_SLTI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val)
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#define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXF) */
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#define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1ADu, MMIPS32_POOL32AXF) */
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#define MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR)
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#define MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(MMIPS32_POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR)
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#define MMIPS32_XORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val)
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#define MMIPS32_SYNCI_STEP 0x1u /* reg num od address step size to be used with synci instruction */
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/* ejtag specific instructions */
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#define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXF) */
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#define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXF) */
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#define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x38D, MMIPS32_POOL32AXF) */
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#define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1BD, MMIPS32_POOL32AXF) */
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#define MMIPS16_SDBBP 0x46C0u /* POOL16C instr */
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/* instruction code with isa selection */
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@ -672,6 +689,7 @@ struct mips32_algorithm {
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#define MIPS32_J(isa, tar) (isa ? MMIPS32_J(tar) : MIPS32_ISA_J(tar))
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#define MIPS32_JR(isa, reg) (isa ? MMIPS32_JR(reg) : MIPS32_ISA_JR(reg))
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#define MIPS32_JRHB(isa, reg) (isa ? MMIPS32_JRHB(reg) : MIPS32_ISA_JRHB(reg))
|
||||
#define MIPS32_LB(isa, reg, off, base) (isa ? MMIPS32_LB(reg, off, base) : MIPS32_ISA_LB(reg, off, base))
|
||||
#define MIPS32_LBU(isa, reg, off, base) (isa ? MMIPS32_LBU(reg, off, base) : MIPS32_ISA_LBU(reg, off, base))
|
||||
#define MIPS32_LHU(isa, reg, off, base) (isa ? MMIPS32_LHU(reg, off, base) : MIPS32_ISA_LHU(reg, off, base))
|
||||
|
|
@ -685,6 +703,7 @@ struct mips32_algorithm {
|
|||
#define MIPS32_MTLO(isa, reg) (isa ? MMIPS32_MTLO(reg) : MIPS32_ISA_MTLO(reg))
|
||||
#define MIPS32_MTHI(isa, reg) (isa ? MMIPS32_MTHI(reg) : MIPS32_ISA_MTHI(reg))
|
||||
|
||||
#define MIPS32_MUL(isa, dst, src, t) (MIPS32_ISA_MUL(dst, src, t))
|
||||
#define MIPS32_MOVN(isa, dst, src, tar) (isa ? MMIPS32_MOVN(dst, src, tar) : MIPS32_ISA_MOVN(dst, src, tar))
|
||||
#define MIPS32_ORI(isa, tar, src, val) (isa ? MMIPS32_ORI(tar, src, val) : MIPS32_ISA_ORI(tar, src, val))
|
||||
#define MIPS32_RDHWR(isa, tar, dst) (isa ? MMIPS32_RDHWR(tar, dst) : MIPS32_ISA_RDHWR(tar, dst))
|
||||
|
|
@ -693,6 +712,8 @@ struct mips32_algorithm {
|
|||
#define MIPS32_SW(isa, reg, off, base) (isa ? MMIPS32_SW(reg, off, base) : MIPS32_ISA_SW(reg, off, base))
|
||||
|
||||
#define MIPS32_SLL(isa, dst, src, sa) (isa ? MMIPS32_SLL(dst, src, sa) : MIPS32_ISA_SLL(dst, src, sa))
|
||||
#define MIPS32_EHB(isa) (isa ? MMIPS32_SLL(0, 0, 3) : MIPS32_ISA_SLL(0, 0, 3))
|
||||
#define MIPS32_SLLV(isa, dst, src, sa) (MIPS32_ISA_SLLV(dst, src, sa))
|
||||
#define MIPS32_SLTI(isa, tar, src, val) (isa ? MMIPS32_SLTI(tar, src, val) : MIPS32_ISA_SLTI(tar, src, val))
|
||||
#define MIPS32_SLTU(isa, dst, src, tar) (isa ? MMIPS32_SLTU(dst, src, tar) : MIPS32_ISA_SLTU(dst, src, tar))
|
||||
#define MIPS32_SRL(isa, reg, src, off) (isa ? MMIPS32_SRL(reg, src, off) : MIPS32_ISA_SRL(reg, src, off))
|
||||
|
|
@ -710,6 +731,9 @@ struct mips32_algorithm {
|
|||
|
||||
#define MIPS16_SDBBP(isa) (isa ? MMIPS16_SDBBP : MIPS16_ISA_SDBBP)
|
||||
|
||||
/* ejtag specific instructions */
|
||||
#define MICRO_MIPS32_SDBBP 0x000046C0
|
||||
#define MICRO_MIPS_SDBBP 0x46C0
|
||||
/*
|
||||
* MIPS32 Config1 Register (CP0 Register 16, Select 1)
|
||||
*/
|
||||
|
|
@ -843,4 +867,7 @@ int mips32_checksum_memory(struct target *target, target_addr_t address,
|
|||
int mips32_blank_check_memory(struct target *target,
|
||||
struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
|
||||
|
||||
bool mips32_cpu_support_sync(struct mips_ejtag *ejtag_info);
|
||||
bool mips32_cpu_support_hazard_barrier(struct mips_ejtag *ejtag_info);
|
||||
|
||||
#endif /* OPENOCD_TARGET_MIPS32_H */
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@
|
|||
#include <helper/time_support.h>
|
||||
#include <jtag/adapter.h>
|
||||
|
||||
#include "mips_cpu.h"
|
||||
#include "mips32.h"
|
||||
#include "mips32_pracc.h"
|
||||
|
||||
|
|
@ -452,6 +453,8 @@ static int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, u
|
|||
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
|
||||
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16((addr + 0x8000)))); /* load $8 with modified upper addr */
|
||||
pracc_add(&ctx, 0, MIPS32_LW(ctx.isa, 8, LOWER16(addr), 8)); /* lw $8, LOWER16(addr)($8) */
|
||||
if (mips32_cpu_support_sync(ejtag_info))
|
||||
pracc_add(&ctx, 0, MIPS32_SYNC(ctx.isa));
|
||||
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT,
|
||||
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15)); /* sw $8,PRACC_OUT_OFFSET($15) */
|
||||
pracc_add_li32(&ctx, 8, ejtag_info->reg8, 0); /* restore $8 */
|
||||
|
|
@ -508,6 +511,8 @@ int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size
|
|||
else
|
||||
pracc_add(&ctx, 0, MIPS32_LBU(ctx.isa, 8, LOWER16(addr), 9));
|
||||
|
||||
if (mips32_cpu_support_sync(ejtag_info))
|
||||
pracc_add(&ctx, 0, MIPS32_SYNC(ctx.isa));
|
||||
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + i * 4, /* store $8 at param out */
|
||||
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + i * 4, 15));
|
||||
addr += size;
|
||||
|
|
@ -550,6 +555,8 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_r
|
|||
pracc_queue_init(&ctx);
|
||||
|
||||
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
|
||||
if (mips32_cpu_support_hazard_barrier(ejtag_info))
|
||||
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
|
||||
pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 8, cp0_reg, cp0_sel)); /* move cp0 reg / sel to $8 */
|
||||
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT,
|
||||
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */
|
||||
|
|
@ -571,6 +578,8 @@ int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_r
|
|||
pracc_add_li32(&ctx, 15, val, 0); /* Load val to $15 */
|
||||
|
||||
pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, cp0_reg, cp0_sel)); /* write $15 to cp0 reg / sel */
|
||||
if (mips32_cpu_support_hazard_barrier(ejtag_info))
|
||||
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
|
||||
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
|
||||
pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0)); /* restore $15 from DeSave */
|
||||
|
||||
|
|
@ -786,6 +795,7 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz
|
|||
if ((KSEGX(addr) == KSEG1) || ((addr >= 0xff200000) && (addr <= 0xff3fffff)))
|
||||
return retval; /*Nothing to do*/
|
||||
|
||||
/* Reads Config0 */
|
||||
mips32_cp0_read(ejtag_info, &conf, 16, 0);
|
||||
|
||||
switch (KSEGX(addr)) {
|
||||
|
|
@ -813,11 +823,28 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz
|
|||
uint32_t start_addr = addr;
|
||||
uint32_t end_addr = addr + count * size;
|
||||
uint32_t rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
|
||||
if (rel > 1) {
|
||||
LOG_DEBUG("Unknown release in cache code");
|
||||
/* FIXME: In MIPS Release 6, the encoding of CACHE instr has changed */
|
||||
if (rel > MIPS32_RELEASE_2) {
|
||||
LOG_DEBUG("Unsupported MIPS Release ( > 5)");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
retval = mips32_pracc_synchronize_cache(ejtag_info, start_addr, end_addr, cached, rel);
|
||||
} else {
|
||||
struct pracc_queue_info ctx = {.ejtag_info = ejtag_info};
|
||||
|
||||
pracc_queue_init(&ctx);
|
||||
if (mips32_cpu_support_sync(ejtag_info))
|
||||
pracc_add(&ctx, 0, MIPS32_SYNC(ctx.isa));
|
||||
if (mips32_cpu_support_hazard_barrier(ejtag_info))
|
||||
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
|
||||
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
|
||||
pracc_add(&ctx, 0, MIPS32_NOP);
|
||||
ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 1);
|
||||
if (ctx.retval != ERROR_OK) {
|
||||
LOG_ERROR("Unable to barrier");
|
||||
retval = ctx.retval;
|
||||
}
|
||||
pracc_queue_free(&ctx);
|
||||
}
|
||||
|
||||
return retval;
|
||||
|
|
@ -866,6 +893,8 @@ int mips32_pracc_write_regs(struct mips32_common *mips32)
|
|||
pracc_add(&ctx, 0, cp0_write_code[i]);
|
||||
}
|
||||
|
||||
if (mips32_cpu_support_hazard_barrier(ejtag_info))
|
||||
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
|
||||
/* load registers 2 to 31 with li32, optimize */
|
||||
for (int i = 2; i < 32; i++)
|
||||
pracc_add_li32(&ctx, i, gprs[i], 1);
|
||||
|
|
@ -1019,6 +1048,70 @@ int mips32_pracc_read_regs(struct mips32_common *mips32)
|
|||
return ctx.retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* mips32_pracc_fastdata_xfer_synchronize_cache - Synchronize cache for fast data transfer
|
||||
* @param[in] ejtag_info: EJTAG information structure
|
||||
* @param[in] addr: Starting address for cache synchronization
|
||||
* @param[in] size: Size of each data element
|
||||
* @param[in] count: Number of data elements
|
||||
*
|
||||
* @brief Synchronizes the cache for fast data transfer based on
|
||||
* the specified address and cache configuration.
|
||||
* If the region is cacheable (write-back cache or write-through cache),
|
||||
* it synchronizes the cache for the specified range.
|
||||
* The synchronization is performed using the MIPS32 cache synchronization function.
|
||||
*
|
||||
* @return ERROR_OK on success; error code on failure.
|
||||
*/
|
||||
static int mips32_pracc_fastdata_xfer_synchronize_cache(struct mips_ejtag *ejtag_info,
|
||||
uint32_t addr, int size, int count)
|
||||
{
|
||||
int retval = ERROR_OK;
|
||||
|
||||
if ((KSEGX(addr) == KSEG1) || (addr >= 0xff200000 && addr <= 0xff3fffff)) // DESEG?
|
||||
return retval; /*Nothing to do*/
|
||||
|
||||
int cached = 0;
|
||||
uint32_t conf = 0;
|
||||
|
||||
mips32_cp0_read(ejtag_info, &conf, 16, 0);
|
||||
|
||||
switch (KSEGX(addr)) {
|
||||
case KUSEG:
|
||||
cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT;
|
||||
break;
|
||||
case KSEG0:
|
||||
cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT;
|
||||
break;
|
||||
case KSEG2:
|
||||
case KSEG3:
|
||||
cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT;
|
||||
break;
|
||||
default:
|
||||
/* what ? */
|
||||
break;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check cacheability bits coherency algorithm
|
||||
* is the region cacheable or uncached.
|
||||
* If cacheable we have to synchronize the cache
|
||||
*/
|
||||
if (cached == 3 || cached == 0) { /* Write back cache or write through cache */
|
||||
uint32_t start_addr = addr;
|
||||
uint32_t end_addr = addr + count * size;
|
||||
uint32_t rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
|
||||
/* FIXME: In MIPS Release 6, the encoding of CACHE instr has changed */
|
||||
if (rel > MIPS32_RELEASE_2) {
|
||||
LOG_DEBUG("Unsupported MIPS Release ( > 5)");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
retval = mips32_pracc_synchronize_cache(ejtag_info, start_addr, end_addr, cached, rel);
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* fastdata upload/download requires an initialized working area
|
||||
* to load the download code; it should not be called otherwise
|
||||
* fetch order from the fastdata area
|
||||
|
|
@ -1039,13 +1132,17 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
|
|||
/* start of fastdata area in t0 */
|
||||
MIPS32_LUI(isa, 8, UPPER16(MIPS32_PRACC_FASTDATA_AREA)),
|
||||
MIPS32_ORI(isa, 8, 8, LOWER16(MIPS32_PRACC_FASTDATA_AREA)),
|
||||
MIPS32_LW(isa, 9, 0, 8), /* start addr in t1 */
|
||||
MIPS32_LW(isa, 10, 0, 8), /* end addr to t2 */
|
||||
/* loop: */
|
||||
MIPS32_LW(isa, 9, 0, 8), /* start addr in t1 */
|
||||
mips32_cpu_support_sync(ejtag_info) ? MIPS32_SYNC(isa) : MIPS32_NOP, /* barrier for ordering */
|
||||
MIPS32_LW(isa, 10, 0, 8), /* end addr to t2 */
|
||||
mips32_cpu_support_sync(ejtag_info) ? MIPS32_SYNC(isa) : MIPS32_NOP, /* barrier for ordering */
|
||||
/* loop: */
|
||||
write_t ? MIPS32_LW(isa, 11, 0, 8) : MIPS32_LW(isa, 11, 0, 9), /* from xfer area : from memory */
|
||||
write_t ? MIPS32_SW(isa, 11, 0, 9) : MIPS32_SW(isa, 11, 0, 8), /* to memory : to xfer area */
|
||||
|
||||
MIPS32_BNE(isa, 10, 9, NEG16(3 << isa)), /* bne $t2,t1,loop */
|
||||
mips32_cpu_support_sync(ejtag_info) ? MIPS32_SYNC(isa) : MIPS32_NOP, /* barrier for ordering */
|
||||
|
||||
MIPS32_BNE(isa, 10, 9, NEG16(4 << isa)), /* bne $t2,t1,loop */
|
||||
MIPS32_ADDI(isa, 9, 9, 4), /* addi t1,t1,4 */
|
||||
|
||||
MIPS32_LW(isa, 8, MIPS32_FASTDATA_HANDLER_SIZE - 4, 15),
|
||||
|
|
@ -1055,7 +1152,9 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
|
|||
|
||||
MIPS32_LUI(isa, 15, UPPER16(MIPS32_PRACC_TEXT)),
|
||||
MIPS32_ORI(isa, 15, 15, LOWER16(MIPS32_PRACC_TEXT) | isa), /* isa bit for JR instr */
|
||||
MIPS32_JR(isa, 15), /* jr start */
|
||||
mips32_cpu_support_hazard_barrier(ejtag_info)
|
||||
? MIPS32_JRHB(isa, 15)
|
||||
: MIPS32_JR(isa, 15), /* jr start */
|
||||
MIPS32_MFC0(isa, 15, 31, 0), /* move COP0 DeSave to $15 */
|
||||
};
|
||||
|
||||
|
|
@ -1075,7 +1174,9 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
|
|||
uint32_t jmp_code[] = {
|
||||
MIPS32_LUI(isa, 15, UPPER16(source->address)), /* load addr of jump in $15 */
|
||||
MIPS32_ORI(isa, 15, 15, LOWER16(source->address) | isa), /* isa bit for JR instr */
|
||||
MIPS32_JR(isa, 15), /* jump to ram program */
|
||||
mips32_cpu_support_hazard_barrier(ejtag_info)
|
||||
? MIPS32_JRHB(isa, 15)
|
||||
: MIPS32_JR(isa, 15), /* jump to ram program */
|
||||
isa ? MIPS32_XORI(isa, 15, 15, 1) : MIPS32_NOP, /* drop isa bit, needed for LW/SW instructions */
|
||||
};
|
||||
|
||||
|
|
@ -1139,5 +1240,5 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
|
|||
if (ejtag_info->pa_addr != MIPS32_PRACC_TEXT)
|
||||
LOG_ERROR("mini program did not return to start");
|
||||
|
||||
return retval;
|
||||
return mips32_pracc_fastdata_xfer_synchronize_cache(ejtag_info, addr, 4, count);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -53,6 +53,8 @@ struct pracc_queue_info {
|
|||
struct pa_list *pracc_list; /* Code and store addresses at dmseg */
|
||||
};
|
||||
|
||||
struct mips32_common;
|
||||
|
||||
void pracc_queue_init(struct pracc_queue_info *ctx);
|
||||
void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr);
|
||||
void pracc_queue_free(struct pracc_queue_info *ctx);
|
||||
|
|
|
|||
|
|
@ -206,6 +206,7 @@ struct mips_ejtag {
|
|||
struct jtag_tap *tap;
|
||||
uint32_t impcode;
|
||||
uint32_t idcode;
|
||||
uint32_t prid;
|
||||
uint32_t ejtag_ctrl;
|
||||
int fast_access_save;
|
||||
uint32_t config_regs; /* number of config registers read */
|
||||
|
|
|
|||
Loading…
Reference in New Issue