target/xtensa: add algorithm support
Add arch level functions to execute code on the target Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I089095de6fcb9906ad8c84232fa52a77db5e6185 Reviewed-on: https://review.openocd.org/c/openocd/+/7771 Tested-by: jenkins Reviewed-by: Ian Thompson <ianst@cadence.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Erhan Kurubas
Antonio Borneo
parent
d3ffcc784d
commit
d06d8ea3e4
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@ -16,6 +16,7 @@
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#include <helper/time_support.h>
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#include <helper/align.h>
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#include <target/register.h>
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#include <target/algorithm.h>
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#include "xtensa_chip.h"
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#include "xtensa.h"
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@ -2635,6 +2636,214 @@ int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoin
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return ERROR_OK;
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}
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int xtensa_start_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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target_addr_t entry_point, target_addr_t exit_point,
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void *arch_info)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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struct xtensa_algorithm *algorithm_info = arch_info;
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int retval = ERROR_OK;
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bool usr_ps = false;
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/* NOTE: xtensa_run_algorithm requires that each algorithm uses a software breakpoint
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* at the exit point */
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if (target->state != TARGET_HALTED) {
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LOG_WARNING("Target not halted!");
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return ERROR_TARGET_NOT_HALTED;
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}
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for (unsigned int i = 0; i < xtensa->core_cache->num_regs; i++) {
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struct reg *reg = &xtensa->core_cache->reg_list[i];
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buf_cpy(reg->value, xtensa->algo_context_backup[i], reg->size);
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}
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/* save debug reason, it will be changed */
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algorithm_info->ctx_debug_reason = target->debug_reason;
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/* write mem params */
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for (int i = 0; i < num_mem_params; i++) {
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if (mem_params[i].direction != PARAM_IN) {
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retval = target_write_buffer(target, mem_params[i].address,
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mem_params[i].size,
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mem_params[i].value);
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if (retval != ERROR_OK)
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return retval;
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}
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}
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/* write reg params */
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for (int i = 0; i < num_reg_params; i++) {
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if (reg_params[i].size > 32) {
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LOG_ERROR("BUG: not supported register size (%d)", reg_params[i].size);
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return ERROR_FAIL;
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}
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struct reg *reg = register_get_by_name(xtensa->core_cache, reg_params[i].reg_name, 0);
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if (!reg) {
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LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
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return ERROR_FAIL;
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}
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if (reg->size != reg_params[i].size) {
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LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
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return ERROR_FAIL;
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}
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if (memcmp(reg_params[i].reg_name, "ps", 3)) {
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usr_ps = true;
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} else {
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unsigned int reg_id = xtensa->eps_dbglevel_idx;
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assert(reg_id < xtensa->core_cache->num_regs && "Attempt to access non-existing reg!");
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reg = &xtensa->core_cache->reg_list[reg_id];
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}
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xtensa_reg_set_value(reg, buf_get_u32(reg_params[i].value, 0, reg->size));
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reg->valid = 1;
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}
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/* ignore custom core mode if custom PS value is specified */
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if (!usr_ps) {
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unsigned int eps_reg_idx = xtensa->eps_dbglevel_idx;
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xtensa_reg_val_t ps = xtensa_reg_get(target, eps_reg_idx);
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enum xtensa_mode core_mode = XT_PS_RING_GET(ps);
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if (algorithm_info->core_mode != XT_MODE_ANY && algorithm_info->core_mode != core_mode) {
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LOG_DEBUG("setting core_mode: 0x%x", algorithm_info->core_mode);
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xtensa_reg_val_t new_ps = (ps & ~XT_PS_RING_MSK) | XT_PS_RING(algorithm_info->core_mode);
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/* save previous core mode */
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/* TODO: core_mode is not restored for now. Can be added to the end of wait_algorithm */
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algorithm_info->core_mode = core_mode;
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xtensa_reg_set(target, eps_reg_idx, new_ps);
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xtensa->core_cache->reg_list[eps_reg_idx].valid = 1;
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}
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}
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return xtensa_resume(target, 0, entry_point, 1, 1);
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}
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/** Waits for an algorithm in the target. */
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int xtensa_wait_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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target_addr_t exit_point, unsigned int timeout_ms,
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void *arch_info)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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struct xtensa_algorithm *algorithm_info = arch_info;
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int retval = ERROR_OK;
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xtensa_reg_val_t pc;
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/* NOTE: xtensa_run_algorithm requires that each algorithm uses a software breakpoint
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* at the exit point */
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retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
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/* If the target fails to halt due to the breakpoint, force a halt */
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if (retval != ERROR_OK || target->state != TARGET_HALTED) {
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retval = target_halt(target);
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if (retval != ERROR_OK)
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return retval;
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retval = target_wait_state(target, TARGET_HALTED, 500);
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if (retval != ERROR_OK)
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return retval;
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LOG_TARGET_ERROR(target, "not halted %d, pc 0x%" PRIx32 ", ps 0x%" PRIx32, retval,
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xtensa_reg_get(target, XT_REG_IDX_PC),
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xtensa_reg_get(target, xtensa->eps_dbglevel_idx));
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return ERROR_TARGET_TIMEOUT;
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}
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pc = xtensa_reg_get(target, XT_REG_IDX_PC);
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if (exit_point && pc != exit_point) {
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LOG_ERROR("failed algorithm halted at 0x%" PRIx32 ", expected " TARGET_ADDR_FMT, pc, exit_point);
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return ERROR_TARGET_TIMEOUT;
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}
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/* Copy core register values to reg_params[] */
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for (int i = 0; i < num_reg_params; i++) {
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if (reg_params[i].direction != PARAM_OUT) {
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struct reg *reg = register_get_by_name(xtensa->core_cache, reg_params[i].reg_name, 0);
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if (!reg) {
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LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
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return ERROR_FAIL;
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}
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if (reg->size != reg_params[i].size) {
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LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
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return ERROR_FAIL;
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}
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buf_set_u32(reg_params[i].value, 0, 32, xtensa_reg_get_value(reg));
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}
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}
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/* Read memory values to mem_params */
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LOG_DEBUG("Read mem params");
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for (int i = 0; i < num_mem_params; i++) {
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LOG_DEBUG("Check mem param @ " TARGET_ADDR_FMT, mem_params[i].address);
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if (mem_params[i].direction != PARAM_OUT) {
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LOG_DEBUG("Read mem param @ " TARGET_ADDR_FMT, mem_params[i].address);
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retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
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if (retval != ERROR_OK)
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return retval;
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}
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}
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/* avoid gdb keep_alive warning */
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keep_alive();
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for (int i = xtensa->core_cache->num_regs - 1; i >= 0; i--) {
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struct reg *reg = &xtensa->core_cache->reg_list[i];
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if (i == XT_REG_IDX_PS) {
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continue; /* restore mapped reg number of PS depends on NDEBUGLEVEL */
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} else if (i == XT_REG_IDX_DEBUGCAUSE) {
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/*FIXME: restoring DEBUGCAUSE causes exception when executing corresponding
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* instruction in DIR */
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LOG_DEBUG("Skip restoring register %s: 0x%8.8" PRIx32 " -> 0x%8.8" PRIx32,
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xtensa->core_cache->reg_list[i].name,
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buf_get_u32(reg->value, 0, 32),
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buf_get_u32(xtensa->algo_context_backup[i], 0, 32));
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buf_cpy(xtensa->algo_context_backup[i], reg->value, reg->size);
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xtensa->core_cache->reg_list[i].dirty = 0;
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xtensa->core_cache->reg_list[i].valid = 0;
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} else if (memcmp(xtensa->algo_context_backup[i], reg->value, reg->size / 8)) {
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if (reg->size <= 32) {
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LOG_DEBUG("restoring register %s: 0x%8.8" PRIx32 " -> 0x%8.8" PRIx32,
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xtensa->core_cache->reg_list[i].name,
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buf_get_u32(reg->value, 0, reg->size),
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buf_get_u32(xtensa->algo_context_backup[i], 0, reg->size));
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} else if (reg->size <= 64) {
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LOG_DEBUG("restoring register %s: 0x%8.8" PRIx64 " -> 0x%8.8" PRIx64,
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xtensa->core_cache->reg_list[i].name,
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buf_get_u64(reg->value, 0, reg->size),
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buf_get_u64(xtensa->algo_context_backup[i], 0, reg->size));
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} else {
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LOG_DEBUG("restoring register %s %u-bits", xtensa->core_cache->reg_list[i].name, reg->size);
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}
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buf_cpy(xtensa->algo_context_backup[i], reg->value, reg->size);
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xtensa->core_cache->reg_list[i].dirty = 1;
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xtensa->core_cache->reg_list[i].valid = 1;
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}
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}
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target->debug_reason = algorithm_info->ctx_debug_reason;
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retval = xtensa_write_dirty_registers(target);
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if (retval != ERROR_OK)
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LOG_ERROR("Failed to write dirty regs (%d)!", retval);
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return retval;
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}
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int xtensa_run_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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target_addr_t entry_point, target_addr_t exit_point,
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unsigned int timeout_ms, void *arch_info)
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{
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int retval = xtensa_start_algorithm(target,
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num_mem_params, mem_params,
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num_reg_params, reg_params,
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entry_point, exit_point,
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arch_info);
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if (retval == ERROR_OK) {
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retval = xtensa_wait_algorithm(target,
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num_mem_params, mem_params,
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num_reg_params, reg_params,
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exit_point, timeout_ms,
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arch_info);
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}
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return retval;
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}
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static int xtensa_build_reg_cache(struct target *target)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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@ -222,6 +222,16 @@ struct xtensa_sw_breakpoint {
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uint8_t insn_sz; /* 2 or 3 bytes */
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};
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/**
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* Xtensa algorithm data.
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*/
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struct xtensa_algorithm {
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/** User can set this to specify which core mode algorithm should be run in. */
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enum xtensa_mode core_mode;
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/** Used internally to backup and restore debug_reason. */
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enum target_debug_reason ctx_debug_reason;
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};
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#define XTENSA_COMMON_MAGIC 0x54E4E555U
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/**
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@ -395,6 +405,21 @@ int xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint);
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int xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint);
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int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint);
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int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoint);
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int xtensa_start_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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target_addr_t entry_point, target_addr_t exit_point,
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void *arch_info);
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int xtensa_wait_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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target_addr_t exit_point, unsigned int timeout_ms,
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void *arch_info);
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int xtensa_run_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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target_addr_t entry_point, target_addr_t exit_point,
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unsigned int timeout_ms, void *arch_info);
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void xtensa_set_permissive_mode(struct target *target, bool state);
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const char *xtensa_get_gdb_arch(struct target *target);
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int xtensa_gdb_query_custom(struct target *target, const char *packet, char **response_p);
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