target/mips32: add fpu access support
Add access to fpr and cp1 registers. GDB can now check the FPRs with `info reg f` and change them. Checkpatch-ignore: MACRO_ARG_REUSE Change-Id: I63896ab6f6737054d8108db105a13a58e1446fbc Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7866 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Walter Ji
Antonio Borneo
parent
a88db9b121
commit
01a797af14
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@ -262,6 +262,61 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
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return ERROR_OK;
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}
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/**
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* mips32_set_all_fpr_width - Set the width of all floating-point registers
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* @param[in] mips32: MIPS32 common structure
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* @param[in] fp64: Flag indicating whether to set the width to 64 bits (double precision)
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*
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* @brief Sets the width of all floating-point registers based on the specified flag.
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*/
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static void mips32_set_all_fpr_width(struct mips32_common *mips32, bool fp64)
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{
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struct reg_cache *cache = mips32->core_cache;
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struct reg *reg_list = cache->reg_list;
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int i;
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for (i = MIPS32_REGLIST_FP_INDEX; i < (MIPS32_REGLIST_FP_INDEX + MIPS32_REG_FP_COUNT); i++) {
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reg_list[i].size = fp64 ? 64 : 32;
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reg_list[i].reg_data_type->type = fp64 ? REG_TYPE_IEEE_DOUBLE : REG_TYPE_IEEE_SINGLE;
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}
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}
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/**
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* mips32_detect_fpr_mode_change - Detect changes in floating-point register mode
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* @param[in] mips32: MIPS32 common structure
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* @param[in] cp0_status: Value of the CP0 status register
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*
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* @brief Detects changes in the floating-point register mode based on the CP0 status register.
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* If changes are detected, it updates the internal state
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* and logs a warning message indicating the mode change.
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*/
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static void mips32_detect_fpr_mode_change(struct mips32_common *mips32, uint32_t cp0_status)
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{
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if (!mips32->fp_imp)
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return;
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/* CP0.Status.FR indicates the working mode of floating-point register.
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* When FP = 0, fpr can contain any 32bit data type,
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* 64bit data types are stored in even-odd register pairs.
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* When FP = 1, fpr can contain any data types.*/
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bool fpu_in_64bit = ((cp0_status & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0);
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/* CP0.Status.CU1 indicated whether CoProcessor1(which is FPU) is present. */
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bool fp_enabled = ((cp0_status & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0);
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if (mips32->fpu_in_64bit != fpu_in_64bit) {
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mips32->fpu_in_64bit = fpu_in_64bit;
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mips32_set_all_fpr_width(mips32, fpu_in_64bit);
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LOG_WARNING("** FP mode changed to %sbit, you must reconnect GDB **", fpu_in_64bit ? "64" : "32");
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}
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if (mips32->fpu_enabled != fp_enabled) {
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mips32->fpu_enabled = fp_enabled;
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const char *s = fp_enabled ? "enabled" : "disabled";
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LOG_WARNING("** FP is %s, register update %s **", s, s);
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}
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}
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static int mips32_read_core_reg(struct target *target, unsigned int num)
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{
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unsigned int cnum;
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@ -278,6 +333,8 @@ static int mips32_read_core_reg(struct target *target, unsigned int num)
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cnum = num - MIPS32_REGLIST_C0_INDEX;
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reg_value = mips32->core_regs.cp0[cnum];
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buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
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if (cnum == MIPS32_REG_C0_STATUS_INDEX)
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mips32_detect_fpr_mode_change(mips32, reg_value);
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} else if (num >= MIPS32_REGLIST_FPC_INDEX) {
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/* FPCR */
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cnum = num - MIPS32_REGLIST_FPC_INDEX;
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@ -319,6 +376,8 @@ static int mips32_write_core_reg(struct target *target, unsigned int num)
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cnum = num - MIPS32_REGLIST_C0_INDEX;
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reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
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mips32->core_regs.cp0[cnum] = (uint32_t)reg_value;
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if (cnum == MIPS32_REG_C0_STATUS_INDEX)
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mips32_detect_fpr_mode_change(mips32, reg_value);
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} else if (num >= MIPS32_REGLIST_FPC_INDEX) {
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/* FPCR */
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cnum = num - MIPS32_REGLIST_FPC_INDEX;
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@ -987,8 +1046,8 @@ static int mips32_read_config_fpu(struct mips32_common *mips32, struct mips_ejta
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mips32->fp_imp = MIPS32_FP_IMP_NONE;
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return ERROR_OK;
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}
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uint32_t status_value;
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bool status_fr, status_cu1;
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uint32_t fir_value, status_value;
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bool fpu_in_64bit, fp_enabled;
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retval = mips32_cp0_read(ejtag_info, &status_value, MIPS32_C0_STATUS, 0);
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if (retval != ERROR_OK) {
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@ -996,20 +1055,34 @@ static int mips32_read_config_fpu(struct mips32_common *mips32, struct mips_ejta
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return retval;
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}
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status_fr = (status_value >> MIPS32_CP0_STATUS_FR_SHIFT) & 0x1;
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status_cu1 = (status_value >> MIPS32_CP0_STATUS_CU1_SHIFT) & 0x1;
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if (status_cu1) {
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/* TODO: read fpu(cp1) config register for current operating mode.
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* Now its set to 32 bits by default. */
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snprintf(buf, sizeof(buf), "yes");
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fp_imp = MIPS32_FP_IMP_32;
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fpu_in_64bit = (status_value & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0;
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fp_enabled = (status_value & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0;
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if (fp_enabled) {
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retval = mips32_cp1_control_read(ejtag_info, &fir_value, 0);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to read cp1 FIR register");
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return retval;
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}
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if ((fir_value >> MIPS32_CP1_FIR_F64_SHIFT) & 0x1)
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fp_imp++;
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} else {
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/* This is the only condition that writes to buf */
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snprintf(buf, sizeof(buf), "yes, disabled");
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fp_imp = MIPS32_FP_IMP_UNKNOWN;
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}
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mips32->fpu_in_64bit = status_fr;
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mips32->fpu_enabled = status_cu1;
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mips32->fpu_in_64bit = fpu_in_64bit;
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mips32->fpu_enabled = fp_enabled;
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mips32_set_all_fpr_width(mips32, fpu_in_64bit);
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/* If fpu is not disabled, print out more information */
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if (!buf[0])
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snprintf(buf, sizeof(buf), "yes, %sbit (%s, working in %sbit)",
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fp_imp == MIPS32_FP_IMP_64 ? "64" : "32",
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fp_enabled ? "enabled" : "disabled",
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fpu_in_64bit ? "64" : "32");
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LOG_USER("FPU implemented: %s", buf);
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mips32->fp_imp = fp_imp;
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@ -459,10 +459,13 @@ struct mips32_algorithm {
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#define MIPS32_OP_AND 0x24u
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#define MIPS32_OP_CACHE 0x2Fu
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#define MIPS32_OP_COP0 0x10u
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#define MIPS32_OP_COP1 0x11u
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#define MIPS32_OP_J 0x02u
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#define MIPS32_OP_JR 0x08u
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#define MIPS32_OP_LUI 0x0Fu
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#define MIPS32_OP_LW 0x23u
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#define MIPS32_OP_LWC1 0x31u
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#define MIPS32_OP_LDC1 0x35u
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#define MIPS32_OP_LB 0x20u
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#define MIPS32_OP_LBU 0x24u
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#define MIPS32_OP_LHU 0x25u
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@ -470,6 +473,7 @@ struct mips32_algorithm {
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#define MIPS32_OP_MTHI 0x11u
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#define MIPS32_OP_MFLO 0x12u
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#define MIPS32_OP_MTLO 0x13u
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#define MIPS32_OP_MUL 0x02u
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#define MIPS32_OP_RDHWR 0x3Bu
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#define MIPS32_OP_SB 0x28u
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#define MIPS32_OP_SH 0x29u
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@ -485,6 +489,8 @@ struct mips32_algorithm {
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#define MIPS32_OP_SLLV 0x04u
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#define MIPS32_OP_SLTI 0x0Au
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#define MIPS32_OP_MOVN 0x0Bu
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#define MIPS32_OP_SWC1 0x39u
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#define MIPS32_OP_SDC1 0x3Du
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#define MIPS32_OP_REGIMM 0x01u
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#define MIPS32_OP_SDBBP 0x3Fu
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@ -517,6 +523,7 @@ struct mips32_algorithm {
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#define MIPS32_ISA_BGTZ(reg, off) MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off)
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#define MIPS32_ISA_BNE(src, tar, off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
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#define MIPS32_ISA_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off)
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#define MIPS32_ISA_CFC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_CF, gpr, cpr, 0, 0)
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#define MIPS32_ISA_J(tar) MIPS32_J_INST(MIPS32_OP_J, (0x0FFFFFFFu & (tar)) >> 2)
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#define MIPS32_ISA_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
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#define MIPS32_ISA_JRHB(reg) MIPS32_R_INST(0, reg, 0, 0, 0x10, MIPS32_OP_JR)
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@ -526,9 +533,15 @@ struct mips32_algorithm {
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#define MIPS32_ISA_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
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#define MIPS32_ISA_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
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#define MIPS32_ISA_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
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#define MIPS32_ISA_LWC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_LWC1, base, reg, off)
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#define MIPS32_ISA_LDC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_LDC1, base, reg, off)
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#define MIPS32_ISA_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MF, gpr, cpr, 0, sel)
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#define MIPS32_ISA_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MT, gpr, cpr, 0, sel)
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#define MIPS32_ISA_MFC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MF, gpr, cpr, 0, 0)
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#define MIPS32_ISA_MFHC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MFH, gpr, cpr, 0, 0)
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#define MIPS32_ISA_MTC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MT, gpr, cpr, 0, 0)
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#define MIPS32_ISA_MTHC1(gpr, cpr) MIPS32_R_INST(MIPS32_OP_COP1, MIPS32_COP_MTH, gpr, cpr, 0, 0)
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#define MIPS32_ISA_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
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#define MIPS32_ISA_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
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#define MIPS32_ISA_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
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@ -542,6 +555,8 @@ struct mips32_algorithm {
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#define MIPS32_ISA_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
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#define MIPS32_ISA_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
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#define MIPS32_ISA_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
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#define MIPS32_ISA_SWC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_SWC1, base, reg, off)
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#define MIPS32_ISA_SDC1(reg, off, base) MIPS32_I_INST(MIPS32_OP_SDC1, base, reg, off)
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#define MIPS32_ISA_SLL(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL)
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#define MIPS32_ISA_SLLV(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLLV)
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@ -588,6 +603,7 @@ struct mips32_algorithm {
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#define MMIPS32_OP_BGTZ 0x06u
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#define MMIPS32_OP_BNE 0x2Du
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#define MMIPS32_OP_CACHE 0x06u
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#define MMIPS32_OP_CFC1 0x40u
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#define MMIPS32_OP_J 0x35u
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#define MMIPS32_OP_JALR 0x03Cu
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#define MMIPS32_OP_JALRHB 0x07Cu
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@ -596,8 +612,14 @@ struct mips32_algorithm {
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#define MMIPS32_OP_LHU 0x0Du
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#define MMIPS32_OP_LUI 0x0Du
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#define MMIPS32_OP_LW 0x3Fu
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#define MMIPS32_OP_LWC1 0x27u
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#define MMIPS32_OP_LDC1 0x2Fu
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#define MMIPS32_OP_MFC0 0x03u
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#define MMIPS32_OP_MFC1 0x80u
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#define MMIPS32_OP_MFHC1 0xC0u
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#define MMIPS32_OP_MTC0 0x0Bu
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#define MMIPS32_OP_MTC1 0xA0u
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#define MMIPS32_OP_MTHC1 0xE0u
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#define MMIPS32_OP_MFLO 0x075u
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#define MMIPS32_OP_MFHI 0x035u
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#define MMIPS32_OP_MTLO 0x0F5u
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@ -608,6 +630,8 @@ struct mips32_algorithm {
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#define MMIPS32_OP_SB 0x06u
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#define MMIPS32_OP_SH 0x0Eu
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#define MMIPS32_OP_SW 0x3Eu
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#define MMIPS32_OP_SWC1 0x26u
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#define MMIPS32_OP_SDC1 0x2Eu
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#define MMIPS32_OP_SLTU 0x390u
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#define MMIPS32_OP_SLL 0x000u
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#define MMIPS32_OP_SLTI 0x24u
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@ -627,6 +651,7 @@ struct mips32_algorithm {
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#define MMIPS32_BGTZ(reg, off) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_BGTZ, reg, off)
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#define MMIPS32_BNE(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BNE, tar, src, off)
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#define MMIPS32_CACHE(op, off, base) MIPS32_R_INST(MMIPS32_POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)
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#define MMIPS32_CFC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_CFC1, MMIPS32_POOL32FXF)
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#define MMIPS32_J(tar) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1))))
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#define MMIPS32_JR(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALR, MMIPS32_POOL32AXF)
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@ -636,13 +661,19 @@ struct mips32_algorithm {
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#define MMIPS32_LHU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off)
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#define MMIPS32_LUI(reg, val) MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_LUI, reg, val)
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#define MMIPS32_LW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off)
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#define MMIPS32_LWC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LWC1, reg, base, off)
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#define MMIPS32_LDC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LDC1, reg, base, off)
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#define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\
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MMIPS32_OP_MFC0, MMIPS32_POOL32AXF)
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#define MMIPS32_MFC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MFC1, MMIPS32_POOL32FXF)
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#define MMIPS32_MFHC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MFHC1, MMIPS32_POOL32FXF)
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#define MMIPS32_MFLO(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, MMIPS32_POOL32AXF)
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#define MMIPS32_MFHI(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, MMIPS32_POOL32AXF)
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#define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\
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MMIPS32_OP_MTC0, MMIPS32_POOL32AXF)
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#define MMIPS32_MTC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MTC1, MMIPS32_POOL32FXF)
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#define MMIPS32_MTHC1(gpr, cpr) MIPS32_R_INST(MMIPS32_POOL32F, gpr, cpr, 0, MMIPS32_OP_MTHC1, MMIPS32_POOL32FXF)
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#define MMIPS32_MTLO(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, MMIPS32_POOL32AXF)
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#define MMIPS32_MTHI(reg) MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, MMIPS32_POOL32AXF)
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@ -653,6 +684,8 @@ struct mips32_algorithm {
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#define MMIPS32_SB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off)
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#define MMIPS32_SH(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off)
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#define MMIPS32_SW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off)
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#define MMIPS32_SWC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SWC1, reg, base, off)
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#define MMIPS32_SDC1(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SDC1, reg, base, off)
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#define MMIPS32_SRL(reg, src, off) MIPS32_R_INST(MMIPS32_POOL32A, reg, src, off, 0, MMIPS32_OP_SRL)
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#define MMIPS32_SLTU(dst, src, tar) MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU)
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@ -686,6 +719,7 @@ struct mips32_algorithm {
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#define MIPS32_BGTZ(isa, reg, off) (isa ? MMIPS32_BGTZ(reg, off) : MIPS32_ISA_BGTZ(reg, off))
|
||||
#define MIPS32_BNE(isa, src, tar, off) (isa ? MMIPS32_BNE(src, tar, off) : MIPS32_ISA_BNE(src, tar, off))
|
||||
#define MIPS32_CACHE(isa, op, off, base) (isa ? MMIPS32_CACHE(op, off, base) : MIPS32_ISA_CACHE(op, off, base))
|
||||
#define MIPS32_CFC1(isa, gpr, cpr) (isa ? MMIPS32_CFC1(gpr, cpr) : MIPS32_ISA_CFC1(gpr, cpr))
|
||||
|
||||
#define MIPS32_J(isa, tar) (isa ? MMIPS32_J(tar) : MIPS32_ISA_J(tar))
|
||||
#define MIPS32_JR(isa, reg) (isa ? MMIPS32_JR(reg) : MIPS32_ISA_JR(reg))
|
||||
|
|
@ -694,10 +728,15 @@ struct mips32_algorithm {
|
|||
#define MIPS32_LBU(isa, reg, off, base) (isa ? MMIPS32_LBU(reg, off, base) : MIPS32_ISA_LBU(reg, off, base))
|
||||
#define MIPS32_LHU(isa, reg, off, base) (isa ? MMIPS32_LHU(reg, off, base) : MIPS32_ISA_LHU(reg, off, base))
|
||||
#define MIPS32_LW(isa, reg, off, base) (isa ? MMIPS32_LW(reg, off, base) : MIPS32_ISA_LW(reg, off, base))
|
||||
#define MIPS32_LWC1(isa, reg, off, base) (isa ? MMIPS32_LWC1(reg, off, base) : MIPS32_ISA_LWC1(reg, off, base))
|
||||
#define MIPS32_LUI(isa, reg, val) (isa ? MMIPS32_LUI(reg, val) : MIPS32_ISA_LUI(reg, val))
|
||||
|
||||
#define MIPS32_MFC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MFC0(gpr, cpr, sel) : MIPS32_ISA_MFC0(gpr, cpr, sel))
|
||||
#define MIPS32_MTC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MTC0(gpr, cpr, sel) : MIPS32_ISA_MTC0(gpr, cpr, sel))
|
||||
#define MIPS32_MFC1(isa, gpr, cpr) (isa ? MMIPS32_MFC1(gpr, cpr) : MIPS32_ISA_MFC1(gpr, cpr))
|
||||
#define MIPS32_MFHC1(isa, gpr, cpr) (isa ? MMIPS32_MFHC1(gpr, cpr) : MIPS32_ISA_MFHC1(gpr, cpr))
|
||||
#define MIPS32_MTC1(isa, gpr, cpr) (isa ? MMIPS32_MTC1(gpr, cpr) : MIPS32_ISA_MTC1(gpr, cpr))
|
||||
#define MIPS32_MTHC1(isa, gpr, cpr) (isa ? MMIPS32_MTHC1(gpr, cpr) : MIPS32_ISA_MTHC1(gpr, cpr))
|
||||
#define MIPS32_MFLO(isa, reg) (isa ? MMIPS32_MFLO(reg) : MIPS32_ISA_MFLO(reg))
|
||||
#define MIPS32_MFHI(isa, reg) (isa ? MMIPS32_MFHI(reg) : MIPS32_ISA_MFHI(reg))
|
||||
#define MIPS32_MTLO(isa, reg) (isa ? MMIPS32_MTLO(reg) : MIPS32_ISA_MTLO(reg))
|
||||
|
|
@ -710,6 +749,8 @@ struct mips32_algorithm {
|
|||
#define MIPS32_SB(isa, reg, off, base) (isa ? MMIPS32_SB(reg, off, base) : MIPS32_ISA_SB(reg, off, base))
|
||||
#define MIPS32_SH(isa, reg, off, base) (isa ? MMIPS32_SH(reg, off, base) : MIPS32_ISA_SH(reg, off, base))
|
||||
#define MIPS32_SW(isa, reg, off, base) (isa ? MMIPS32_SW(reg, off, base) : MIPS32_ISA_SW(reg, off, base))
|
||||
#define MIPS32_SWC1(isa, reg, off, base) (isa ? MMIPS32_SWC1(reg, off, base) : MIPS32_ISA_SWC1(reg, off, base))
|
||||
#define MIPS32_SDC1(isa, reg, off, base) (isa ? MMIPS32_SDC1(reg, off, base) : MIPS32_ISA_SDC1(reg, off, base))
|
||||
|
||||
#define MIPS32_SLL(isa, dst, src, sa) (isa ? MMIPS32_SLL(dst, src, sa) : MIPS32_ISA_SLL(dst, src, sa))
|
||||
#define MIPS32_EHB(isa) (isa ? MMIPS32_SLL(0, 0, 3) : MIPS32_ISA_SLL(0, 0, 3))
|
||||
|
|
|
|||
|
|
@ -588,6 +588,26 @@ int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_r
|
|||
return ctx.retval;
|
||||
}
|
||||
|
||||
int mips32_cp1_control_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp1_c_reg)
|
||||
{
|
||||
struct pracc_queue_info ctx = {.ejtag_info = ejtag_info};
|
||||
pracc_queue_init(&ctx);
|
||||
|
||||
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */
|
||||
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
|
||||
pracc_add(&ctx, 0, MIPS32_CFC1(ctx.isa, 8, cp1_c_reg)); /* move cp1c reg to $8 */
|
||||
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT,
|
||||
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */
|
||||
pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0)); /* restore $15 from DeSave */
|
||||
pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
|
||||
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
|
||||
pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
|
||||
|
||||
ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, val, 1);
|
||||
pracc_queue_free(&ctx);
|
||||
return ctx.retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* \b mips32_pracc_sync_cache
|
||||
*
|
||||
|
|
@ -856,6 +876,9 @@ int mips32_pracc_write_regs(struct mips32_common *mips32)
|
|||
struct pracc_queue_info ctx = {.ejtag_info = ejtag_info};
|
||||
uint32_t *gprs = mips32->core_regs.gpr;
|
||||
uint32_t *c0rs = mips32->core_regs.cp0;
|
||||
bool fpu_in_64bit = ((c0rs[0] & BIT(MIPS32_CP0_STATUS_FR_SHIFT)) != 0);
|
||||
bool fp_enabled = ((c0rs[0] & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0);
|
||||
uint32_t rel = (ejtag_info->config[0] & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
|
||||
|
||||
pracc_queue_init(&ctx);
|
||||
|
||||
|
|
@ -895,6 +918,31 @@ int mips32_pracc_write_regs(struct mips32_common *mips32)
|
|||
|
||||
if (mips32_cpu_support_hazard_barrier(ejtag_info))
|
||||
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
|
||||
|
||||
/* store FPRs */
|
||||
if (mips32->fp_imp && fp_enabled) {
|
||||
uint64_t *fprs = mips32->core_regs.fpr;
|
||||
if (fpu_in_64bit) {
|
||||
for (int i = 0; i != MIPS32_REG_FP_COUNT; i++) {
|
||||
uint32_t fp_lo = fprs[i] & 0xffffffff;
|
||||
uint32_t fp_hi = (fprs[i] >> 32) & 0xffffffff;
|
||||
pracc_add_li32(&ctx, 2, fp_lo, 0);
|
||||
pracc_add_li32(&ctx, 3, fp_hi, 0);
|
||||
pracc_add(&ctx, 0, MIPS32_MTC1(ctx.isa, 2, i));
|
||||
pracc_add(&ctx, 0, MIPS32_MTHC1(ctx.isa, 3, i));
|
||||
}
|
||||
} else {
|
||||
for (int i = 0; i != MIPS32_REG_FP_COUNT; i++) {
|
||||
uint32_t fp_lo = fprs[i] & 0xffffffff;
|
||||
pracc_add_li32(&ctx, 2, fp_lo, 0);
|
||||
pracc_add(&ctx, 0, MIPS32_MTC1(ctx.isa, 2, i));
|
||||
}
|
||||
}
|
||||
|
||||
if (rel > MIPS32_RELEASE_1)
|
||||
pracc_add(&ctx, 0, MIPS32_EHB(ctx.isa));
|
||||
}
|
||||
|
||||
/* load registers 2 to 31 with li32, optimize */
|
||||
for (int i = 2; i < 32; i++)
|
||||
pracc_add_li32(&ctx, i, gprs[i], 1);
|
||||
|
|
@ -1014,6 +1062,9 @@ int mips32_pracc_read_regs(struct mips32_common *mips32)
|
|||
struct mips32_core_regs *core_regs = &mips32->core_regs;
|
||||
unsigned int offset_gpr = ((uint8_t *)&core_regs->gpr[0]) - (uint8_t *)core_regs;
|
||||
unsigned int offset_cp0 = ((uint8_t *)&core_regs->cp0[0]) - (uint8_t *)core_regs;
|
||||
unsigned int offset_fpr = ((uint8_t *)&core_regs->fpr[0]) - (uint8_t *)core_regs;
|
||||
unsigned int offset_fpcr = ((uint8_t *)&core_regs->fpcr[0]) - (uint8_t *)core_regs;
|
||||
bool fp_enabled;
|
||||
|
||||
/*
|
||||
* This procedure has to be in 2 distinctive steps, because we can
|
||||
|
|
@ -1040,11 +1091,64 @@ int mips32_pracc_read_regs(struct mips32_common *mips32)
|
|||
ejtag_info->reg8 = mips32->core_regs.gpr[8];
|
||||
ejtag_info->reg9 = mips32->core_regs.gpr[9];
|
||||
|
||||
if (ctx.retval != ERROR_OK)
|
||||
return ctx.retval;
|
||||
|
||||
/* we only care if FP is actually impl'd and if cp1 is enabled */
|
||||
/* since we already read cp0 in the prev step */
|
||||
/* now we know what's in cp0.status */
|
||||
/* TODO: Read FPRs */
|
||||
fp_enabled = (mips32->core_regs.cp0[0] & BIT(MIPS32_CP0_STATUS_CU1_SHIFT)) != 0;
|
||||
if (mips32->fp_imp && fp_enabled) {
|
||||
pracc_queue_init(&ctx);
|
||||
|
||||
mips32_pracc_store_regs_set_base_addr(&ctx);
|
||||
|
||||
/* FCSR */
|
||||
pracc_add(&ctx, 0, MIPS32_CFC1(ctx.isa, 8, 31));
|
||||
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset_fpcr,
|
||||
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_fpcr, 1));
|
||||
|
||||
/* FIR */
|
||||
pracc_add(&ctx, 0, MIPS32_CFC1(ctx.isa, 8, 0));
|
||||
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset_fpcr + 4,
|
||||
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_fpcr + 4, 1));
|
||||
|
||||
/* f0 to f31 */
|
||||
if (mips32->fpu_in_64bit) {
|
||||
for (int i = 0; i != 32; i++) {
|
||||
size_t offset = offset_fpr + (i * 8);
|
||||
/* current pracc implementation (or EJTAG itself) only supports 32b access */
|
||||
/* so there is no way to use SDC1 */
|
||||
|
||||
/* lower half */
|
||||
pracc_add(&ctx, 0, MIPS32_MFC1(ctx.isa, 8, i));
|
||||
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset,
|
||||
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset, 1));
|
||||
|
||||
/* upper half */
|
||||
pracc_add(&ctx, 0, MIPS32_MFHC1(ctx.isa, 8, i));
|
||||
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset + 4,
|
||||
MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset + 4, 1));
|
||||
}
|
||||
} else {
|
||||
for (int i = 0; i != 32; i++) {
|
||||
size_t offset = offset_fpr + (i * 8);
|
||||
pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + offset,
|
||||
MIPS32_SWC1(ctx.isa, i, PRACC_OUT_OFFSET + offset, 1));
|
||||
}
|
||||
}
|
||||
|
||||
mips32_pracc_store_regs_restore(&ctx);
|
||||
|
||||
/* jump to start */
|
||||
pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa)));
|
||||
/* load $15 in DeSave */
|
||||
pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0));
|
||||
|
||||
ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, (uint32_t *)&mips32->core_regs, 1);
|
||||
|
||||
pracc_queue_free(&ctx);
|
||||
}
|
||||
return ctx.retval;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -103,6 +103,21 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info,
|
|||
int mips32_cp0_write(struct mips_ejtag *ejtag_info,
|
||||
uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel);
|
||||
|
||||
/**
|
||||
* mips32_cp1_control_read
|
||||
*
|
||||
* @brief Simulates cfc1 ASM instruction (Move Control Word From Floating Point),
|
||||
* i.e. implements copro C1 Control Register read.
|
||||
*
|
||||
* @param[in] ejtag_info
|
||||
* @param[in] val Storage to hold read value
|
||||
* @param[in] cp1_c_reg Number of copro C1 control register we want to read
|
||||
*
|
||||
* @return ERROR_OK on Success, ERROR_FAIL otherwise
|
||||
*/
|
||||
int mips32_cp1_control_read(struct mips_ejtag *ejtag_info,
|
||||
uint32_t *val, uint32_t cp1_c_reg);
|
||||
|
||||
static inline void pracc_swap16_array(struct mips_ejtag *ejtag_info, uint32_t *buf, int count)
|
||||
{
|
||||
if (ejtag_info->isa && ejtag_info->endianness)
|
||||
|
|
|
|||
Loading…
Reference in New Issue