[NFC] target/riscv: refactor `init_registers()`
The logic in `init_registers()` was quite convoluted. Initialization of each `struct reg` field is separated into function `gdb_regno_<field_name>()`. IMHO, this makes it much easier to reason about the code. Change-Id: Id7faa1464ce026cc5025585d0a6a95a01fb39cee Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
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@ -78,6 +78,9 @@ enum gdb_regno {
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GDB_REGNO_FT11,
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GDB_REGNO_FPR31 = GDB_REGNO_FT11,
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GDB_REGNO_CSR0 = 65,
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GDB_REGNO_FCSR = CSR_FCSR + GDB_REGNO_CSR0,
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GDB_REGNO_FFLAGS = CSR_FFLAGS + GDB_REGNO_CSR0,
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GDB_REGNO_FRM = CSR_FRM + GDB_REGNO_CSR0,
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GDB_REGNO_VSTART = CSR_VSTART + GDB_REGNO_CSR0,
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GDB_REGNO_VXSAT = CSR_VXSAT + GDB_REGNO_CSR0,
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GDB_REGNO_VXRM = CSR_VXRM + GDB_REGNO_CSR0,
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@ -120,6 +123,6 @@ enum gdb_regno {
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GDB_REGNO_COUNT
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};
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const char *gdb_regno_name(struct target *target, enum gdb_regno regno);
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const char *gdb_regno_name(const struct target *target, enum gdb_regno regno);
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#endif
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File diff suppressed because it is too large
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@ -260,6 +260,9 @@ struct riscv_info {
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COMMAND_HELPER((*print_info), struct target *target);
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/* Storage for arch_info of non-custom registers. */
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riscv_reg_info_t shared_reg_info;
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/* Storage for vector register types. */
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struct reg_data_type_vector vector_uint8;
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struct reg_data_type_vector vector_uint16;
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@ -390,11 +393,14 @@ int riscv_openocd_step(
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/*** RISC-V Interface ***/
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bool riscv_supports_extension(struct target *target, char letter);
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bool riscv_supports_extension(const struct target *target, char letter);
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/* Returns XLEN for the given (or current) hart. */
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unsigned riscv_xlen(const struct target *target);
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/* Returns VLENB for the given (or current) hart. */
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unsigned int riscv_vlenb(const struct target *target);
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/*** Support functions for the RISC-V 'RTOS', which provides multihart support
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* without requiring multiple targets. */
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