Merge up to 04154af5d6 from upstream
Change-Id: I84c1566472e5416bc2a71afa5adaf63c6c7a4a75
This commit is contained in:
Evgeniy Naydanov
commit
c0791b1c9e
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@ -670,7 +670,11 @@ PKG_CHECK_MODULES([LIBFTDI], [libftdi1], [
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PKG_CHECK_MODULES([LIBFTDI], [libftdi], [use_libftdi=yes], [use_libftdi=no])
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])
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PKG_CHECK_MODULES([LIBGPIOD], [libgpiod], [use_libgpiod=yes], [use_libgpiod=no])
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PKG_CHECK_MODULES([LIBGPIOD], [libgpiod < 2.0], [
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use_libgpiod=yes
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PKG_CHECK_EXISTS([libgpiod >= 1.5],
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[AC_DEFINE([HAVE_LIBGPIOD1_FLAGS_BIAS], [1], [define if libgpiod v1 has line request flags bias])])
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], [use_libgpiod=no])
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PKG_CHECK_MODULES([LIBJAYLINK], [libjaylink >= 0.2],
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[use_libjaylink=yes], [use_libjaylink=no])
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@ -77,7 +77,12 @@ The read responses are encoded in ASCII as either digit 0 or 1.
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If the use_remote_sleep option is set to 'yes', two additional requests may
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be sent:
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D - Sleep for 1 millisecond
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d - Sleep for 1 microsecond
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Z - Sleep for 1 millisecond
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z - Sleep for 1 microsecond
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NOTE: Previously these were specified as 'D' and 'd', which conflicts with the
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"SWD write 0 0" command defined above. Adapters that implement Dd for remote
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sleep must be updated to work with Zz.
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*/
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@ -6805,6 +6805,24 @@ Note that in order for this command to take effect, the target needs to be reset
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supported.}
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@end deffn
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@deffn {Flash Driver} {eneispif}
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All versions of the KB1200 microcontrollers from ENE include internal
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flash. The eneispif flash driver supports the KB1200 family of devices. The driver
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automatically recognizes the specific version's flash parameters and
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autoconfigures itself. The flash bank starts at address 0x60000000. An optional additional
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parameter sets the address of eneispif controller, with the default address is 0x50101000.
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@example
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flash bank $_FLASHNAME eneispif 0x60000000 0 0 0 $_TARGETNAME \
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0x50101000
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# Address defaults to 0x50101000
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flash bank $_FLASHNAME eneispif 0x60000000 0 0 0 $_TARGETNAME
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@end example
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@end deffn
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@deffn {Flash Driver} {esirisc}
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Members of the eSi-RISC family may optionally include internal flash programmed
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via the eSi-TSMC Flash interface. Additional parameters are required to
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@ -28,6 +28,7 @@ NOR_DRIVERS = \
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%D%/dsp5680xx_flash.c \
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%D%/efm32.c \
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%D%/em357.c \
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%D%/eneispif.c \
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%D%/esirisc_flash.c \
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%D%/faux.c \
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%D%/fespi.c \
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@ -256,6 +256,7 @@ extern const struct flash_driver cfi_flash;
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extern const struct flash_driver dsp5680xx_flash;
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extern const struct flash_driver efm32_flash;
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extern const struct flash_driver em357_flash;
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extern const struct flash_driver eneispif_flash;
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extern const struct flash_driver esirisc_flash;
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extern const struct flash_driver faux_flash;
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extern const struct flash_driver fespi_flash;
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@ -33,6 +33,7 @@ static const struct flash_driver * const flash_drivers[] = {
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&dsp5680xx_flash,
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&efm32_flash,
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&em357_flash,
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&eneispif_flash,
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&esirisc_flash,
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&faux_flash,
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&fm3_flash,
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@ -0,0 +1,433 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2024 ENE Technology Inc.
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* steven@ene.com.tw
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <helper/time_support.h>
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#include <helper/bits.h>
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#include <target/target.h>
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#include <flash/nor/core.h>
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#include <flash/nor/driver.h>
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#include <flash/nor/spi.h>
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#define ISPICFG 0x0000
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#define ISPISTS 0x0004
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#define ISPIADDR 0x0008
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#define ISPICMD 0x000C
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#define ISPIDAT 0x0100
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#define ISPISTS_BUSY BIT(0)
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#define STATUS1_QE BIT(1)
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#define CFG_READ 0x372
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#define CFG_WRITE 0x371
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#define ISPI_CTRL_BASE 0x50101000
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/* name read qread page erase chip device_id page erase flash
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* _cmd _cmd _prog _cmd* _erase size size* size
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* _cmd _cmd
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*/
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struct flash_device ene_flash_device =
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FLASH_ID("ISPI flash", 0x03, 0x00, 0x02, 0x20, 0x60, 0x00132085, 0x100, 0x1000, 0x80000);
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struct eneispif_flash_bank {
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bool probed;
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target_addr_t ctrl_base;
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uint32_t dev_id;
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const struct flash_device *dev;
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};
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FLASH_BANK_COMMAND_HANDLER(eneispif_flash_bank_command)
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{
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struct eneispif_flash_bank *eneispif_info;
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LOG_DEBUG("%s", __func__);
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if (CMD_ARGC < 6)
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return ERROR_COMMAND_SYNTAX_ERROR;
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eneispif_info = malloc(sizeof(struct eneispif_flash_bank));
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if (!eneispif_info) {
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LOG_ERROR("not enough memory");
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return ERROR_FAIL;
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}
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bank->driver_priv = eneispif_info;
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eneispif_info->probed = false;
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eneispif_info->ctrl_base = ISPI_CTRL_BASE;
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if (CMD_ARGC >= 7) {
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COMMAND_PARSE_ADDRESS(CMD_ARGV[6], eneispif_info->ctrl_base);
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LOG_INFO("ASSUMING ISPI device at ctrl_base = " TARGET_ADDR_FMT,
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eneispif_info->ctrl_base);
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}
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return ERROR_OK;
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}
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static int eneispif_read_reg(struct flash_bank *bank, uint32_t *value, target_addr_t address)
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{
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struct target *target = bank->target;
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struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
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int result = target_read_u32(target, eneispif_info->ctrl_base + address, value);
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if (result != ERROR_OK) {
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LOG_ERROR("%s error at " TARGET_ADDR_FMT, __func__,
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eneispif_info->ctrl_base + address);
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return result;
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}
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LOG_DEBUG("Read address " TARGET_ADDR_FMT " = 0x%" PRIx32,
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eneispif_info->ctrl_base + address, *value);
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return ERROR_OK;
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}
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static int eneispif_write_reg(struct flash_bank *bank, target_addr_t address, uint32_t value)
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{
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struct target *target = bank->target;
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struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
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LOG_DEBUG("Write address " TARGET_ADDR_FMT " = 0x%" PRIx32,
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eneispif_info->ctrl_base + address, value);
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int result = target_write_u32(target, eneispif_info->ctrl_base + address, value);
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if (result != ERROR_OK) {
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LOG_ERROR("%s error writing 0x%" PRIx32 " to " TARGET_ADDR_FMT, __func__,
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value, eneispif_info->ctrl_base + address);
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return result;
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}
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return ERROR_OK;
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}
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static int eneispif_wait(struct flash_bank *bank)
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{
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int64_t start = timeval_ms();
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while (1) {
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uint32_t status;
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if (eneispif_read_reg(bank, &status, ISPISTS) != ERROR_OK)
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return ERROR_FAIL;
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if (!(status & ISPISTS_BUSY))
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break;
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int64_t now = timeval_ms();
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if (now - start > 1000) {
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LOG_ERROR("Busy more than 1000ms.");
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return ERROR_TARGET_TIMEOUT;
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}
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}
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return ERROR_OK;
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}
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static int eneispi_erase_sector(struct flash_bank *bank, int sector)
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{
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int retval = ERROR_OK;
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struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
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uint32_t offset;
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uint32_t conf;
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retval = eneispif_read_reg(bank, &conf, ISPICFG);
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if (retval != ERROR_OK)
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return retval;
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offset = bank->sectors[sector].offset;
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retval = eneispif_write_reg(bank, ISPIADDR, offset); /* Address */
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if (retval != ERROR_OK)
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goto done;
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eneispif_write_reg(bank, ISPICFG, CFG_WRITE); /* Cmmmand enable */
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eneispif_write_reg(bank, ISPICMD, SPIFLASH_WRITE_ENABLE); /* Write enable */
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retval = eneispif_write_reg(bank, ISPICMD, eneispif_info->dev->erase_cmd); /* Erase page */
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if (retval != ERROR_OK)
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goto done;
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retval = eneispif_wait(bank);
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if (retval != ERROR_OK)
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goto done;
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done:
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eneispif_write_reg(bank, ISPICFG, conf); /* restore */
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return retval;
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}
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static int eneispif_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
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{
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struct target *target = bank->target;
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struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
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int retval = ERROR_OK;
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LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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if (last < first || last >= bank->num_sectors) {
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LOG_ERROR("Flash sector invalid");
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return ERROR_FLASH_SECTOR_INVALID;
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}
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if (!(eneispif_info->probed)) {
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LOG_ERROR("Flash bank not probed");
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return ERROR_FLASH_BANK_NOT_PROBED;
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}
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for (unsigned int sector = first; sector <= last; sector++) {
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if (bank->sectors[sector].is_protected) {
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LOG_ERROR("Flash sector %u protected", sector);
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return ERROR_FAIL;
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}
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}
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if (eneispif_info->dev->erase_cmd == 0x00)
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return ERROR_FLASH_OPER_UNSUPPORTED;
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for (unsigned int sector = first; sector <= last; sector++) {
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retval = eneispi_erase_sector(bank, sector);
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if (retval != ERROR_OK)
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break;
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}
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return retval;
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}
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static int eneispif_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
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{
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for (unsigned int sector = first; sector <= last; sector++)
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bank->sectors[sector].is_protected = set;
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return ERROR_OK;
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}
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static int eneispif_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset,
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uint32_t count)
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{
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struct target *target = bank->target;
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struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
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uint32_t page_size;
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uint32_t conf;
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int retval = ERROR_OK;
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LOG_DEBUG("bank->size=0x%x offset=0x%08" PRIx32 " count=0x%08" PRIx32, bank->size, offset,
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count);
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||||
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
if (offset + count > eneispif_info->dev->size_in_bytes) {
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||||
LOG_WARNING("Write past end of flash. Extra data discarded.");
|
||||
count = eneispif_info->dev->size_in_bytes - offset;
|
||||
}
|
||||
|
||||
/* Check sector protection */
|
||||
for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
|
||||
/* Start offset in or before this sector? */
|
||||
/* End offset in or behind this sector? */
|
||||
if ((offset < (bank->sectors[sector].offset + bank->sectors[sector].size)) &&
|
||||
((offset + count - 1) >= bank->sectors[sector].offset) &&
|
||||
bank->sectors[sector].is_protected) {
|
||||
LOG_ERROR("Flash sector %u protected", sector);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
retval = eneispif_read_reg(bank, &conf, ISPICFG);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
eneispif_write_reg(bank, ISPICFG, CFG_WRITE); // Cmmmand enable
|
||||
|
||||
/* If no valid page_size, use reasonable default. */
|
||||
page_size =
|
||||
eneispif_info->dev->pagesize ? eneispif_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
|
||||
uint32_t page_offset = offset % page_size;
|
||||
|
||||
while (count > 0) {
|
||||
uint32_t cur_count;
|
||||
|
||||
/* clip block at page boundary */
|
||||
if (page_offset + count > page_size)
|
||||
cur_count = page_size - page_offset;
|
||||
else
|
||||
cur_count = count;
|
||||
|
||||
eneispif_write_reg(bank, ISPICMD, SPIFLASH_WRITE_ENABLE); /* Write enable */
|
||||
target_write_buffer(target, eneispif_info->ctrl_base + ISPIDAT, cur_count, buffer);
|
||||
eneispif_write_reg(bank, ISPIADDR, offset);
|
||||
retval = eneispif_write_reg(bank, ISPICMD,
|
||||
(cur_count << 16) | eneispif_info->dev->pprog_cmd);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
page_offset = 0;
|
||||
buffer += cur_count;
|
||||
offset += cur_count;
|
||||
count -= cur_count;
|
||||
retval = eneispif_wait(bank);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
}
|
||||
|
||||
err:
|
||||
eneispif_write_reg(bank, ISPICFG, conf); /* restore */
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* Return ID of flash device */
|
||||
/* On exit, SW mode is kept */
|
||||
static int eneispif_read_flash_id(struct flash_bank *bank, uint32_t *id)
|
||||
{
|
||||
struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
|
||||
struct target *target = bank->target;
|
||||
int retval;
|
||||
uint32_t conf, value;
|
||||
uint8_t buffer[4];
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("Target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
retval = eneispif_read_reg(bank, &conf, ISPICFG);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
LOG_DEBUG("ISPCFG = (0x%08" PRIx32 ")", conf);
|
||||
|
||||
/* read ID from Receive Register */
|
||||
eneispif_write_reg(bank, ISPICFG, CFG_WRITE); /* Cmmmand enable */
|
||||
retval = eneispif_write_reg(bank, ISPICMD, (3 << 16) | SPIFLASH_READ_ID);
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
|
||||
retval = eneispif_wait(bank);
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
|
||||
retval = target_read_buffer(target, eneispif_info->ctrl_base + ISPIDAT, 3, buffer);
|
||||
if (retval != ERROR_OK)
|
||||
goto done;
|
||||
value = (buffer[2] << 16) | (buffer[1] << 8) | buffer[0];
|
||||
LOG_DEBUG("ISPDAT = (0x%08" PRIx32 ")", value);
|
||||
|
||||
*id = value;
|
||||
done:
|
||||
eneispif_write_reg(bank, ISPICFG, conf); // restore
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int eneispif_probe(struct flash_bank *bank)
|
||||
{
|
||||
struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
|
||||
struct flash_sector *sectors;
|
||||
uint32_t id;
|
||||
int retval;
|
||||
uint32_t sectorsize;
|
||||
|
||||
if (eneispif_info->probed)
|
||||
free(bank->sectors);
|
||||
|
||||
eneispif_info->probed = false;
|
||||
|
||||
LOG_INFO("Assuming ISPI flash at address " TARGET_ADDR_FMT
|
||||
" with controller at " TARGET_ADDR_FMT,
|
||||
bank->base, eneispif_info->ctrl_base);
|
||||
|
||||
eneispif_write_reg(bank, ISPICFG, CFG_READ); /* RAM map enable */
|
||||
|
||||
retval = eneispif_read_flash_id(bank, &id);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
eneispif_info->dev_id = id;
|
||||
eneispif_info->dev = &ene_flash_device;
|
||||
|
||||
LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")", eneispif_info->dev->name,
|
||||
eneispif_info->dev_id);
|
||||
|
||||
/* Set correct size value */
|
||||
bank->size = eneispif_info->dev->size_in_bytes;
|
||||
|
||||
if (bank->size <= (1UL << 16))
|
||||
LOG_WARNING("device needs 2-byte addresses - not implemented");
|
||||
|
||||
/* if no sectors, treat whole bank as single sector */
|
||||
sectorsize = eneispif_info->dev->sectorsize ? eneispif_info->dev->sectorsize
|
||||
: eneispif_info->dev->size_in_bytes;
|
||||
|
||||
/* create and fill sectors array */
|
||||
bank->num_sectors = eneispif_info->dev->size_in_bytes / sectorsize;
|
||||
sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
|
||||
if (!sectors) {
|
||||
LOG_ERROR("not enough memory");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
|
||||
sectors[sector].offset = sector * sectorsize;
|
||||
sectors[sector].size = sectorsize;
|
||||
sectors[sector].is_erased = -1;
|
||||
sectors[sector].is_protected = 0;
|
||||
}
|
||||
|
||||
bank->sectors = sectors;
|
||||
eneispif_info->probed = true;
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int eneispif_auto_probe(struct flash_bank *bank)
|
||||
{
|
||||
struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
|
||||
if (eneispif_info->probed)
|
||||
return ERROR_OK;
|
||||
return eneispif_probe(bank);
|
||||
}
|
||||
|
||||
static int eneispif_protect_check(struct flash_bank *bank)
|
||||
{
|
||||
/* Nothing to do. Protection is only handled in SW. */
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int get_eneispif_info(struct flash_bank *bank, struct command_invocation *cmd)
|
||||
{
|
||||
struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
|
||||
|
||||
if (!(eneispif_info->probed)) {
|
||||
command_print(cmd, "ENE ISPI flash bank not probed yet.");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
command_print(cmd,
|
||||
"ENE ISPI flash information:\n"
|
||||
" Device \'%s\' (ID 0x%08" PRIx32 ")",
|
||||
eneispif_info->dev->name, eneispif_info->dev_id);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
const struct flash_driver eneispif_flash = {
|
||||
.name = "eneispif",
|
||||
.usage = "flash bank <name> 'eneispif' <base_address> <size> 0 0 <target> <ctrl_base>",
|
||||
.flash_bank_command = eneispif_flash_bank_command,
|
||||
.erase = eneispif_erase,
|
||||
.protect = eneispif_protect,
|
||||
.write = eneispif_write,
|
||||
.read = default_flash_read,
|
||||
.probe = eneispif_probe,
|
||||
.auto_probe = eneispif_auto_probe,
|
||||
.erase_check = default_flash_blank_check,
|
||||
.protect_check = eneispif_protect_check,
|
||||
.info = get_eneispif_info,
|
||||
.free_driver_priv = default_flash_free_driver_priv,
|
||||
};
|
||||
|
|
@ -157,7 +157,7 @@ static int linuxgpiod_swd_write(int swclk, int swdio)
|
|||
int retval;
|
||||
|
||||
if (!swdio_input) {
|
||||
if (!last_stored || (swdio != last_swdio)) {
|
||||
if (!last_stored || swdio != last_swdio) {
|
||||
retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SWDIO], swdio);
|
||||
if (retval < 0)
|
||||
LOG_WARNING("Fail set swdio");
|
||||
|
|
@ -165,7 +165,7 @@ static int linuxgpiod_swd_write(int swclk, int swdio)
|
|||
}
|
||||
|
||||
/* write swclk last */
|
||||
if (!last_stored || (swclk != last_swclk)) {
|
||||
if (!last_stored || swclk != last_swclk) {
|
||||
retval = gpiod_line_set_value(gpiod_line[ADAPTER_GPIO_IDX_SWCLK], swclk);
|
||||
if (retval < 0)
|
||||
LOG_WARNING("Fail set swclk");
|
||||
|
|
@ -320,12 +320,12 @@ static int helper_get_line(enum adapter_gpio_config_index idx)
|
|||
|
||||
switch (adapter_gpio_config[idx].pull) {
|
||||
case ADAPTER_GPIO_PULL_NONE:
|
||||
#ifdef GPIOD_LINE_REQUEST_FLAG_BIAS_DISABLE
|
||||
#ifdef HAVE_LIBGPIOD1_FLAGS_BIAS
|
||||
flags |= GPIOD_LINE_REQUEST_FLAG_BIAS_DISABLE;
|
||||
#endif
|
||||
break;
|
||||
case ADAPTER_GPIO_PULL_UP:
|
||||
#ifdef GPIOD_LINE_REQUEST_FLAG_BIAS_PULL_UP
|
||||
#ifdef HAVE_LIBGPIOD1_FLAGS_BIAS
|
||||
flags |= GPIOD_LINE_REQUEST_FLAG_BIAS_PULL_UP;
|
||||
#else
|
||||
LOG_WARNING("linuxgpiod: ignoring request for pull-up on %s: not supported by gpiod v%s",
|
||||
|
|
@ -333,7 +333,7 @@ static int helper_get_line(enum adapter_gpio_config_index idx)
|
|||
#endif
|
||||
break;
|
||||
case ADAPTER_GPIO_PULL_DOWN:
|
||||
#ifdef GPIOD_LINE_REQUEST_FLAG_BIAS_PULL_DOWN
|
||||
#ifdef HAVE_LIBGPIOD1_FLAGS_BIAS
|
||||
flags |= GPIOD_LINE_REQUEST_FLAG_BIAS_PULL_DOWN;
|
||||
#else
|
||||
LOG_WARNING("linuxgpiod: ignoring request for pull-down on %s: not supported by gpiod v%s",
|
||||
|
|
|
|||
|
|
@ -230,13 +230,13 @@ static int remote_bitbang_sleep(unsigned int microseconds)
|
|||
unsigned int us = microseconds % 1000;
|
||||
|
||||
for (unsigned int i = 0; i < ms; i++) {
|
||||
tmp = remote_bitbang_queue('D', NO_FLUSH);
|
||||
tmp = remote_bitbang_queue('Z', NO_FLUSH);
|
||||
if (tmp != ERROR_OK)
|
||||
return tmp;
|
||||
}
|
||||
|
||||
for (unsigned int i = 0; i < us; i++) {
|
||||
tmp = remote_bitbang_queue('d', NO_FLUSH);
|
||||
tmp = remote_bitbang_queue('z', NO_FLUSH);
|
||||
if (tmp != ERROR_OK)
|
||||
return tmp;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2109,7 +2109,7 @@ static int mips32_dsp_find_register_by_name(const char *reg_name)
|
|||
*/
|
||||
static int mips32_dsp_get_all_regs(struct command_invocation *cmd, struct mips_ejtag *ejtag_info)
|
||||
{
|
||||
uint32_t value;
|
||||
uint32_t value = 0;
|
||||
for (int i = 0; i < MIPS32NUMDSPREGS; i++) {
|
||||
int retval = mips32_pracc_read_dsp_reg(ejtag_info, &value, i);
|
||||
if (retval != ERROR_OK) {
|
||||
|
|
@ -2134,7 +2134,7 @@ static int mips32_dsp_get_all_regs(struct command_invocation *cmd, struct mips_e
|
|||
*/
|
||||
static int mips32_dsp_get_register(struct command_invocation *cmd, struct mips_ejtag *ejtag_info)
|
||||
{
|
||||
uint32_t value;
|
||||
uint32_t value = 0;
|
||||
int index = mips32_dsp_find_register_by_name(CMD_ARGV[0]);
|
||||
if (index == MIPS32NUMDSPREGS) {
|
||||
command_print(CMD, "ERROR: register '%s' not found", CMD_ARGV[0]);
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ ${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
|
|||
${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
|
||||
|
||||
pld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart
|
||||
virtex2 set_user_codes $zynq_pl.pld 0x02 0x03 0x22 0x23
|
||||
virtex2 set_user_codes zynq_pl.pld 0x02 0x03 0x22 0x23
|
||||
|
||||
set XC7_JSHUTDOWN 0x0d
|
||||
set XC7_JPROGRAM 0x0b
|
||||
|
|
|
|||
Loading…
Reference in New Issue