Merge pull request #1023 from en-sc/en-sc/check-ac-busy
target/riscv: check `abstractcs.busy`
This commit is contained in:
Evgeniy Naydanov
GitHub
commit
740cdc78f3
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@ -127,6 +127,8 @@ typedef struct {
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uint32_t base;
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/* The number of harts connected to this DM. */
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int hart_count;
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/* Indicates we already examined this DM, so don't need to do it again. */
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bool was_examined;
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/* Indicates we already reset this DM, so don't need to do it again. */
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bool was_reset;
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/* Targets that are connected to this DM. */
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@ -140,6 +142,12 @@ typedef struct {
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/* The program buffer stores executable code. 0 is an illegal instruction,
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* so we use 0 to mean the cached value is invalid. */
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uint32_t progbuf_cache[16];
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/* Some operations are illegal when an abstract command is running.
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* The field is used to track whether the last command timed out, and
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* abstractcs.busy may have remained set. In that case we may need to
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* re-check the busy state before executing these operations. */
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bool abstract_cmd_maybe_busy;
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} dm013_info_t;
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typedef struct {
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@ -196,9 +204,6 @@ typedef struct {
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uint8_t dataaccess;
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int16_t dataaddr;
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/* The width of the hartsel field. */
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unsigned hartsellen;
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/* DM that provides access to this target. */
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dm013_info_t *dm;
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@ -763,6 +768,7 @@ static int dm_read_exec(struct target *target, uint32_t *value, uint32_t address
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dm013_info_t *dm = get_dm(target);
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if (!dm)
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return ERROR_FAIL;
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dm->abstract_cmd_maybe_busy = true;
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return dmi_read_exec(target, value, address + dm->base);
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}
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@ -780,6 +786,7 @@ static int dm_write_exec(struct target *target, uint32_t address,
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dm013_info_t *dm = get_dm(target);
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if (!dm)
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return ERROR_FAIL;
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dm->abstract_cmd_maybe_busy = true;
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return dmi_write_exec(target, address + dm->base, value, ensure_success);
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}
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@ -874,6 +881,14 @@ static int wait_for_idle(struct target *target, uint32_t *abstractcs)
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assert(target);
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assert(abstractcs);
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dm013_info_t *dm = get_dm(target);
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if (!dm) {
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LOG_ERROR("BUG: Target %s is not assigned to any RISC-V debug module",
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target_name(target));
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*abstractcs = 0;
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return ERROR_FAIL;
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}
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time_t start = time(NULL);
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do {
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if (dm_read(target, abstractcs, DM_ABSTRACTCS) != ERROR_OK) {
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@ -885,9 +900,10 @@ static int wait_for_idle(struct target *target, uint32_t *abstractcs)
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return ERROR_FAIL;
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}
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if (get_field(*abstractcs, DM_ABSTRACTCS_BUSY) == 0)
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if (get_field(*abstractcs, DM_ABSTRACTCS_BUSY) == 0) {
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dm->abstract_cmd_maybe_busy = false;
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return ERROR_OK;
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}
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} while ((time(NULL) - start) < riscv_command_timeout_sec);
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LOG_TARGET_ERROR(target,
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@ -896,6 +912,11 @@ static int wait_for_idle(struct target *target, uint32_t *abstractcs)
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riscv_command_timeout_sec,
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*abstractcs);
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if (!dm->abstract_cmd_maybe_busy)
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LOG_TARGET_ERROR(target,
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"BUG: dm->abstract_cmd_maybe_busy had not been set when starting an abstract command.");
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dm->abstract_cmd_maybe_busy = true;
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return ERROR_TIMEOUT_REACHED;
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}
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@ -1911,6 +1932,151 @@ static int set_group(struct target *target, bool *supported, unsigned int group,
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return ERROR_OK;
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}
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static int wait_for_idle_if_needed(struct target *target)
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{
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dm013_info_t *dm = get_dm(target);
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if (!dm)
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return ERROR_FAIL;
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if (!dm->abstract_cmd_maybe_busy)
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/* The previous abstract command ended correctly
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* and busy was cleared. No need to do anything. */
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return ERROR_OK;
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/* The previous abstract command timed out and abstractcs.busy
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* may have remained set. Wait for it to get cleared. */
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uint32_t abstractcs;
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int result = wait_for_idle(target, &abstractcs);
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if (result != ERROR_OK)
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return result;
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LOG_DEBUG_REG(target, DM_ABSTRACTCS, abstractcs);
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return ERROR_OK;
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}
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static int examine_dm(struct target *target)
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{
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dm013_info_t *dm = get_dm(target);
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if (!dm)
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return ERROR_FAIL;
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if (dm->was_examined)
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return ERROR_OK;
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int result = ERROR_FAIL;
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uint32_t dmcontrol;
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if (!dm->was_reset) {
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/* First, the Debug Module is reset. However,
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* `dmcontrol.hartsel` should be read first, in order not to
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* change it when requesting the reset, since changing it
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* without checking that `abstractcs.busy` is low is
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* prohibited.
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*/
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result = dm_read(target, &dmcontrol, DM_DMCONTROL);
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if (result != ERROR_OK)
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return result;
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/* Initiate the reset (`dmcontrol.dmactive == 0`) leaving
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* `dmcontrol.hartsel` the same.
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*/
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dmcontrol = (dmcontrol & DM_DMCONTROL_HARTSELLO) |
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(dmcontrol & DM_DMCONTROL_HARTSELHI);
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result = dm_write(target, DM_DMCONTROL, dmcontrol);
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if (result != ERROR_OK)
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return result;
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/* FIXME: We should poll dmcontrol until dmactive becomes 0
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* See https://github.com/riscv/riscv-debug-spec/pull/566
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*/
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} else {
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/* The DM was already reset when examining a different hart.
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* No need to reset it again. But for safety, assume that an abstract
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* command might be in progress at the moment.
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*/
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dm->abstract_cmd_maybe_busy = true;
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}
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dm->current_hartid = HART_INDEX_UNKNOWN;
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result = dm_write(target, DM_DMCONTROL, DM_DMCONTROL_HARTSELLO |
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DM_DMCONTROL_HARTSELHI | DM_DMCONTROL_DMACTIVE |
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DM_DMCONTROL_HASEL);
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if (result != ERROR_OK)
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return result;
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result = dm_read(target, &dmcontrol, DM_DMCONTROL);
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if (result != ERROR_OK)
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return result;
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/* FIXME: We should poll for dmactive==1 as the debug module
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* may need some time to actually activate.
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* See https://github.com/riscv/riscv-debug-spec/pull/566
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*/
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if (!get_field(dmcontrol, DM_DMCONTROL_DMACTIVE)) {
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LOG_TARGET_ERROR(target, "Debug Module did not become active.");
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LOG_DEBUG_REG(target, DM_DMCONTROL, dmcontrol);
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return ERROR_FAIL;
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}
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/* The DM has been reset and has successfully came out of the reset (dmactive=1):
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* - either the reset has been performed during this call to examine_dm() (above);
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* - or the reset had already happened in an earlier call of examine_dm() when
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* examining a different hart.
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*/
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dm->was_reset = true;
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dm->hasel_supported = get_field(dmcontrol, DM_DMCONTROL_HASEL);
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uint32_t hartsel =
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(get_field(dmcontrol, DM_DMCONTROL_HARTSELHI) <<
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DM_DMCONTROL_HARTSELLO_LENGTH) |
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get_field(dmcontrol, DM_DMCONTROL_HARTSELLO);
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/* Before doing anything else we must first enumerate the harts. */
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const int max_hart_count = MIN(RISCV_MAX_HARTS, hartsel + 1);
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if (dm->hart_count < 0) {
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for (int i = 0; i < max_hart_count; ++i) {
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/* TODO: This is extremely similar to
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* riscv013_get_hart_state().
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* It would be best to reuse the code.
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*/
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result = dm013_select_hart(target, i);
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if (result != ERROR_OK)
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return result;
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uint32_t s;
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result = dmstatus_read(target, &s, /*authenticated*/ true);
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if (result != ERROR_OK)
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return result;
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if (get_field(s, DM_DMSTATUS_ANYNONEXISTENT))
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break;
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dm->hart_count = i + 1;
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if (get_field(s, DM_DMSTATUS_ANYHAVERESET)) {
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dmcontrol = DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_ACKHAVERESET;
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/* If `abstractcs.busy` is set, debugger should not
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* change `hartsel`.
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*/
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result = wait_for_idle_if_needed(target);
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if (result != ERROR_OK)
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return result;
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dmcontrol = set_dmcontrol_hartsel(dmcontrol, i);
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result = dm_write(target, DM_DMCONTROL, dmcontrol);
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if (result != ERROR_OK)
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return result;
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}
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}
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LOG_TARGET_DEBUG(target, "Detected %d harts.", dm->hart_count);
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}
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if (dm->hart_count <= 0) {
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LOG_TARGET_ERROR(target, "No harts found!");
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return ERROR_FAIL;
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}
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dm->was_examined = true;
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return ERROR_OK;
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}
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static int examine(struct target *target)
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{
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/* We reset target state in case if something goes wrong during examine:
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@ -1947,39 +2113,18 @@ static int examine(struct target *target)
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return ERROR_FAIL;
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}
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/* Reset the Debug Module. */
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dm013_info_t *dm = get_dm(target);
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if (!dm)
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return ERROR_FAIL;
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if (!dm->was_reset) {
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dm_write(target, DM_DMCONTROL, 0);
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dm_write(target, DM_DMCONTROL, DM_DMCONTROL_DMACTIVE);
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dm->was_reset = true;
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}
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int result = examine_dm(target);
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if (result != ERROR_OK)
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return result;
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result = dm013_select_target(target);
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if (result != ERROR_OK)
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return result;
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/* We're here because we're uncertain about the state of the target. That
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* includes our progbuf cache. */
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riscv013_invalidate_cached_progbuf(target);
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dm_write(target, DM_DMCONTROL, DM_DMCONTROL_HARTSELLO |
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DM_DMCONTROL_HARTSELHI | DM_DMCONTROL_DMACTIVE |
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DM_DMCONTROL_HASEL);
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dm->current_hartid = HART_INDEX_UNKNOWN;
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uint32_t dmcontrol;
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if (dm_read(target, &dmcontrol, DM_DMCONTROL) != ERROR_OK)
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return ERROR_FAIL;
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/* Ensure the HART_INDEX_UNKNOWN is flushed out */
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if (dm013_select_hart(target, 0) != ERROR_OK)
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return ERROR_FAIL;
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if (!get_field(dmcontrol, DM_DMCONTROL_DMACTIVE)) {
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LOG_TARGET_ERROR(target, "Debug Module did not become active. dmcontrol=0x%x",
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dmcontrol);
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return ERROR_FAIL;
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}
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dm->hasel_supported = get_field(dmcontrol, DM_DMCONTROL_HASEL);
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uint32_t dmstatus;
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if (dmstatus_read(target, &dmstatus, false) != ERROR_OK)
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return ERROR_FAIL;
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@ -1990,17 +2135,6 @@ static int examine(struct target *target)
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return ERROR_FAIL;
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}
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uint32_t hartsel =
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(get_field(dmcontrol, DM_DMCONTROL_HARTSELHI) <<
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DM_DMCONTROL_HARTSELLO_LENGTH) |
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get_field(dmcontrol, DM_DMCONTROL_HARTSELLO);
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info->hartsellen = 0;
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while (hartsel & 1) {
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info->hartsellen++;
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hartsel >>= 1;
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}
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LOG_TARGET_DEBUG(target, "hartsellen=%d", info->hartsellen);
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uint32_t hartinfo;
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if (dm_read(target, &hartinfo, DM_HARTINFO) != ERROR_OK)
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return ERROR_FAIL;
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@ -2046,38 +2180,9 @@ static int examine(struct target *target)
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, info->progbufsize);
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}
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/* Before doing anything else we must first enumerate the harts. */
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if (dm->hart_count < 0) {
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for (int i = 0; i < MIN(RISCV_MAX_HARTS, 1 << info->hartsellen); ++i) {
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if (dm013_select_hart(target, i) != ERROR_OK)
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return ERROR_FAIL;
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uint32_t s;
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if (dmstatus_read(target, &s, true) != ERROR_OK)
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return ERROR_FAIL;
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if (get_field(s, DM_DMSTATUS_ANYNONEXISTENT))
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break;
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dm->hart_count = i + 1;
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if (get_field(s, DM_DMSTATUS_ANYHAVERESET))
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dm_write(target, DM_DMCONTROL,
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set_dmcontrol_hartsel(DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_ACKHAVERESET, i));
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}
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LOG_TARGET_DEBUG(target, "Detected %d harts.", dm->hart_count);
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}
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if (dm->hart_count <= 0) {
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LOG_TARGET_ERROR(target, "No harts found!");
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return ERROR_FAIL;
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}
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/* Don't call any riscv_* functions until after we've counted the number of
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* cores and initialized registers. */
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if (dm013_select_hart(target, info->index) != ERROR_OK)
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return ERROR_FAIL;
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enum riscv_hart_state state_at_examine_start;
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if (riscv_get_hart_state(target, &state_at_examine_start) != ERROR_OK)
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return ERROR_FAIL;
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@ -2098,7 +2203,7 @@ static int examine(struct target *target)
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* program buffer. */
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r->progbuf_size = info->progbufsize;
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int result = register_read_abstract_with_size(target, NULL, GDB_REGNO_S0, 64);
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result = register_read_abstract_with_size(target, NULL, GDB_REGNO_S0, 64);
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if (result == ERROR_OK)
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r->xlen = 64;
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else
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@ -2728,8 +2833,14 @@ static int riscv013_get_hart_state(struct target *target, enum riscv_hart_state
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* message that a reset happened, that the target is running, and then
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* that it is halted again once the request goes through.
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*/
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if (target->state == TARGET_HALTED)
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if (target->state == TARGET_HALTED) {
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dmcontrol |= DM_DMCONTROL_HALTREQ;
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/* `haltreq` should not be issued if `abstractcs.busy`
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* is set. */
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int result = wait_for_idle_if_needed(target);
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if (result != ERROR_OK)
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return result;
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}
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dm_write(target, DM_DMCONTROL, dmcontrol);
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}
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if (get_field(dmstatus, DM_DMSTATUS_ALLNONEXISTENT)) {
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@ -2850,11 +2961,24 @@ static int assert_reset(struct target *target)
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/* Run the user-supplied script if there is one. */
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target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
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} else {
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dm013_info_t *dm = get_dm(target);
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if (!dm)
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return ERROR_FAIL;
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uint32_t control = set_field(0, DM_DMCONTROL_DMACTIVE, 1);
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control = set_dmcontrol_hartsel(control, info->index);
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control = set_field(control, DM_DMCONTROL_HALTREQ,
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target->reset_halt ? 1 : 0);
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control = set_field(control, DM_DMCONTROL_NDMRESET, 1);
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/* If `abstractcs.busy` is set, debugger should not
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* change `hartsel` or set `haltreq`
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*/
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const bool hartsel_changed = (int)info->index != dm->current_hartid;
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if (hartsel_changed || target->reset_halt) {
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result = wait_for_idle_if_needed(target);
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if (result != ERROR_OK)
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return result;
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}
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result = dm_write(target, DM_DMCONTROL, control);
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if (result != ERROR_OK)
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return result;
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@ -2871,6 +2995,9 @@ static int assert_reset(struct target *target)
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static int deassert_reset(struct target *target)
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{
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RISCV013_INFO(info);
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dm013_info_t *dm = get_dm(target);
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if (!dm)
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return ERROR_FAIL;
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int result;
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select_dmi(target);
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@ -2879,6 +3006,15 @@ static int deassert_reset(struct target *target)
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control = set_field(control, DM_DMCONTROL_DMACTIVE, 1);
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control = set_field(control, DM_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0);
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control = set_dmcontrol_hartsel(control, info->index);
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/* If `abstractcs.busy` is set, debugger should not
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* change `hartsel`.
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*/
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const bool hartsel_changed = (int)info->index != dm->current_hartid;
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if (hartsel_changed) {
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result = wait_for_idle_if_needed(target);
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if (result != ERROR_OK)
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return result;
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}
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result = dm_write(target, DM_DMCONTROL, control);
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if (result != ERROR_OK)
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return result;
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@ -3900,6 +4036,12 @@ static int read_memory_progbuf_inner_run_and_process_batch(struct target *target
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struct riscv_batch *batch, struct memory_access_info access,
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uint32_t start_index, uint32_t elements_to_read, uint32_t *elements_read)
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{
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dm013_info_t *dm = get_dm(target);
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if (!dm)
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return ERROR_FAIL;
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/* Abstract commands are executed while running the batch. */
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dm->abstract_cmd_maybe_busy = true;
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if (batch_run(target, batch) != ERROR_OK)
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return ERROR_FAIL;
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@ -4624,6 +4766,12 @@ static int write_memory_progbuf_run_batch(struct target *target, struct riscv_ba
|
|||
target_addr_t *address_p, target_addr_t end_address, uint32_t size,
|
||||
const uint8_t *buffer)
|
||||
{
|
||||
dm013_info_t *dm = get_dm(target);
|
||||
if (!dm)
|
||||
return ERROR_FAIL;
|
||||
|
||||
/* Abstract commands are executed while running the batch. */
|
||||
dm->abstract_cmd_maybe_busy = true;
|
||||
if (batch_run(target, batch) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
|
||||
|
|
@ -4921,6 +5069,11 @@ static int dm013_select_hart(struct target *target, int hart_index)
|
|||
if (hart_index == dm->current_hartid)
|
||||
return ERROR_OK;
|
||||
|
||||
/* `hartsel` should not be changed if `abstractcs.busy` is set. */
|
||||
int result = wait_for_idle_if_needed(target);
|
||||
if (result != ERROR_OK)
|
||||
return result;
|
||||
|
||||
uint32_t dmcontrol = DM_DMCONTROL_DMACTIVE;
|
||||
dmcontrol = set_dmcontrol_hartsel(dmcontrol, hart_index);
|
||||
if (dm_write(target, DM_DMCONTROL, dmcontrol) != ERROR_OK) {
|
||||
|
|
@ -5015,6 +5168,11 @@ static int riscv013_halt_go(struct target *target)
|
|||
|
||||
LOG_TARGET_DEBUG(target, "halting hart");
|
||||
|
||||
/* `haltreq` should not be issued if `abstractcs.busy` is set. */
|
||||
int result = wait_for_idle_if_needed(target);
|
||||
if (result != ERROR_OK)
|
||||
return result;
|
||||
|
||||
/* Issue the halt command, and then wait for the current hart to halt. */
|
||||
uint32_t dmcontrol = DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_HALTREQ;
|
||||
dmcontrol = set_dmcontrol_hartsel(dmcontrol, dm->current_hartid);
|
||||
|
|
@ -5057,11 +5215,8 @@ static int riscv013_halt_go(struct target *target)
|
|||
/* Only some harts were halted/unavailable. Read
|
||||
* dmstatus for this one to see what its status
|
||||
* is. */
|
||||
riscv013_info_t *info = get_info(t);
|
||||
dmcontrol = set_dmcontrol_hartsel(dmcontrol, info->index);
|
||||
if (dm_write(target, DM_DMCONTROL, dmcontrol) != ERROR_OK)
|
||||
if (dm013_select_target(target) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
dm->current_hartid = info->index;
|
||||
if (dm_read(target, &t_dmstatus, DM_DMSTATUS) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
|
@ -5283,6 +5438,10 @@ static int riscv013_step_or_resume_current_hart(struct target *target,
|
|||
/* Issue the resume command, and then wait for the current hart to resume. */
|
||||
uint32_t dmcontrol = DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_RESUMEREQ;
|
||||
dmcontrol = set_dmcontrol_hartsel(dmcontrol, dm->current_hartid);
|
||||
/* `resumereq` should not be issued if `abstractcs.busy` is set. */
|
||||
int result = wait_for_idle_if_needed(target);
|
||||
if (result != ERROR_OK)
|
||||
return result;
|
||||
dm_write(target, DM_DMCONTROL, dmcontrol);
|
||||
|
||||
dmcontrol = set_field(dmcontrol, DM_DMCONTROL_RESUMEREQ, 0);
|
||||
|
|
|
|||
Loading…
Reference in New Issue