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201 Commits

Author SHA1 Message Date
Clifford Wolf ecd64182c5 Added "yosys -X" 2014-12-29 13:33:33 +01:00
Clifford Wolf cfe0817697 Converting "share" to dict<> and pool<> complete 2014-12-29 02:01:42 +01:00
Clifford Wolf a2226e5307 Added mkhash_xorshift() 2014-12-29 00:12:36 +01:00
Clifford Wolf f3a97b75c7 Fixed performance bug in object hashing 2014-12-28 19:03:18 +01:00
Clifford Wolf 3da46d3437 Renamed hashmap.h to hashlib.h, some related improvements 2014-12-28 17:51:16 +01:00
Clifford Wolf 6c8b0a5fd1 More dict/pool related changes 2014-12-27 12:02:57 +01:00
Clifford Wolf 66ab88d7b0 More hashtable finetuning 2014-12-27 03:04:50 +01:00
Clifford Wolf ec4751e55c Replaced std::unordered_set (nodict) with Yosys::pool 2014-12-26 21:59:41 +01:00
Clifford Wolf 9e6fb0b02c Replaced std::unordered_map as implementation for Yosys::dict 2014-12-26 21:35:22 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf edb3c9d0c4 Renamed extend() to extend_xx(), changed most users to extend_u0() 2014-12-24 09:51:17 +01:00
Clifford Wolf 76fa527492 Added support for multiple clock domains to "abc" pass 2014-12-21 16:52:05 +01:00
Clifford Wolf 6cec188c52 Fixed build with gcc 4.6 2014-12-16 10:38:25 +01:00
Clifford Wolf 7775d2806f Added IdString::destruct_guard hack 2014-12-11 21:46:36 +01:00
Clifford Wolf 7d6e586df8 Added bool constructors to SigBit and SigSpec 2014-12-08 15:08:02 +01:00
Clifford Wolf bca2442c67 Added module->addDffe() and module->addDffeGate() 2014-12-08 14:59:38 +01:00
Clifford Wolf 546e8b5fe7 Improved TopoSort determinism 2014-11-07 15:21:03 +01:00
Clifford Wolf 34caeeb4f3 Fixed a few VS warnings 2014-10-17 06:02:38 +02:00
William Speirs 9cb2303799 Made iterators extend std::iterator and added == operator 2014-10-15 00:56:37 +02:00
Clifford Wolf 0b8cfbc6fd Added support for "keep" on modules 2014-09-29 12:51:54 +02:00
Clifford Wolf 00964f2f61 Initialize RTLIL::Const from std::vector<bool> 2014-09-19 15:50:55 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf e07698818d Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
Clifford Wolf be44157c0f Added RTLIL::Const::size() 2014-08-31 18:07:48 +02:00
Clifford Wolf 0b6769af3f Typo fixes in cell->*Param() API 2014-08-31 17:43:31 +02:00
Clifford Wolf 2a1b08aeb3 Added design->scratchpad 2014-08-30 19:37:12 +02:00
Clifford Wolf eda603105e Added is_signed argument to SigSpec.as_int() and Const.as_int() 2014-08-24 15:14:00 +02:00
Clifford Wolf 98442e019d Added emscripten (emcc) support to build system and some build fixes 2014-08-22 16:20:22 +02:00
Clifford Wolf b37d70dfd7 Added mod->addGate() methods for new gate types 2014-08-19 14:26:54 +02:00
Clifford Wolf 7f734ecc09 Added module->uniquify() 2014-08-16 23:50:36 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf ca87116449 More idstring sort_by_* helpers and fixed tpl ordering in techmap 2014-08-15 02:40:46 +02:00
Clifford Wolf 978a933b6a Added RTLIL::SigSpec::to_sigbit_map() 2014-08-14 23:14:47 +02:00
Clifford Wolf 2f44d8ccf8 Added sig.{replace,remove,extract} variants for std::{map,set} pattern 2014-08-14 22:32:18 +02:00
Clifford Wolf 1bf7a18fec Added module->ports 2014-08-14 16:22:52 +02:00
Clifford Wolf 13f2f36884 RIP $safe_pmux 2014-08-14 11:39:46 +02:00
Clifford Wolf e5ac8fdf2b Fixed SigBit(RTLIL::Wire *wire) constructor 2014-08-12 15:39:48 +02:00
Clifford Wolf 523df73145 Added support for truncating of wires to wreduce pass 2014-08-05 14:47:03 +02:00
Clifford Wolf ebbbe7fc83 Added RTLIL::IdString::in(...) 2014-08-04 15:40:07 +02:00
Clifford Wolf 8e7361f128 Removed at() method from RTLIL::IdString 2014-08-02 19:08:02 +02:00
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf 768eb846c4 More bugfixes related to new RTLIL::IdString 2014-08-02 18:14:21 +02:00
Clifford Wolf 08392aad8f Limit size of log_signal buffer to 100 elements 2014-08-02 15:52:21 +02:00
Clifford Wolf e590ffc84d Improvements in new RTLIL::IdString implementation 2014-08-02 15:44:10 +02:00
Clifford Wolf 60f3dc9923 Implemented new reference counting RTLIL::IdString 2014-08-02 15:11:35 +02:00
Clifford Wolf 97ad0623df Fixed memory corruption related to id2cstr() 2014-08-02 13:34:07 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf 14412e6c95 Preparations for RTLIL::IdString redesign: cleanup of existing code 2014-08-02 00:45:25 +02:00
Clifford Wolf d13eb7e099 Added ModIndex helper class, some changes to RTLIL::Monitor 2014-08-01 17:14:32 +02:00
Clifford Wolf 97a17d39e2 Packed SigBit::data and SigBit::offset in a union 2014-08-01 15:25:42 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf cd9407404a Added RTLIL::Monitor 2014-07-31 14:45:14 +02:00
Clifford Wolf e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf 2541489105 Added techmap CONSTMAP feature 2014-07-30 22:04:30 +02:00
Clifford Wolf a7c6b37abf Added "kernel/yosys.h" and "kernel/yosys.cc" 2014-07-30 14:10:15 +02:00
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf 3c45277ee0 Added wire->upto flag for signals such as "wire [0:7] x;" 2014-07-28 12:12:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf d86a25f145 Added std::initializer_list<> constructor to SigSpec 2014-07-28 10:52:58 +02:00
Clifford Wolf c4bdba78cb Added proper Design->addModule interface 2014-07-27 21:12:09 +02:00
Clifford Wolf cbc3a46a97 Added RTLIL::SigSpecConstIterator 2014-07-27 14:47:23 +02:00
Clifford Wolf 675cb93da9 Added RTLIL::Module::wire(id) and cell(id) lookup functions 2014-07-27 11:18:31 +02:00
Clifford Wolf 0bd8fafbd2 Added RTLIL::Design::modules() 2014-07-27 11:18:30 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf d088854b47 Added conversion from ObjRange to std::vector and std::set 2014-07-27 11:18:30 +02:00
Clifford Wolf 1c8fdaeef8 Added RTLIL::ObjIterator and RTLIL::ObjRange 2014-07-27 11:18:30 +02:00
Clifford Wolf ddc5b41848 Using std::move() in SigSpec move constructor 2014-07-27 09:20:59 +02:00
Clifford Wolf 7f3dc86ecd Added RTLIL::SigSpec move constructor and move assignment operator 2014-07-27 02:11:57 +02:00
Clifford Wolf c91570bde3 Mostly cosmetic changes to rtlil.h 2014-07-27 02:00:04 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf d68c993ed2 Changed more code to the new RTLIL::Wire constructors 2014-07-26 21:30:38 +02:00
Clifford Wolf 946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf 97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf cd6574ecf6 Added some missing "const" in rtlil.h 2014-07-26 15:58:22 +02:00
Clifford Wolf 7ac9dc7f6e Added RTLIL::Module::connections() 2014-07-26 15:58:21 +02:00
Clifford Wolf b03aec6e32 Added RTLIL::Module::connect(const RTLIL::SigSig&) 2014-07-26 14:31:47 +02:00
Clifford Wolf 3719281ed4 Automatically pack SigSpec on copy/assign 2014-07-26 13:59:30 +02:00
Clifford Wolf e75e495c2b Added new RTLIL::Cell port access methods 2014-07-26 12:22:58 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 4755e14e7b Added copy-constructor-like module->addCell(name, other) method 2014-07-26 00:38:44 +02:00
Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf c762050e7f Added RTLIL::SigSpec is_chunk()/as_chunk() API 2014-07-25 14:23:10 +02:00
Clifford Wolf 6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf 22ede43b3f Small changes regarding cover() and check() in SigSpec 2014-07-24 04:46:36 +02:00
Clifford Wolf 82fa356037 Added hashing to RTLIL::SigSpec relational and equal operators 2014-07-23 23:58:03 +02:00
Clifford Wolf 2a41afb7b2 Added RTLIL::SigSpec::repeat() 2014-07-23 21:34:14 +02:00
Clifford Wolf c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
Clifford Wolf a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf 4e802eb7f6 Fixed all users of SigSpec::chunks_rw() and removed it 2014-07-23 15:36:09 +02:00
Clifford Wolf 85db102e13 Replaced RTLIL::SigSpec::operator!=() with inline version 2014-07-23 15:35:09 +02:00
Clifford Wolf ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf 260c19ec5a Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 2014-07-23 09:34:47 +02:00
Clifford Wolf c61467a32c Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&) 2014-07-23 08:59:54 +02:00
Clifford Wolf 9e94f41b89 SigSpec refactoring: Added RTLIL::SigSpecIterator 2014-07-22 23:49:26 +02:00
Clifford Wolf f80da7b41d SigSpec refactoring: added RTLIL::SigSpec::operator[] 2014-07-22 22:54:03 +02:00
Clifford Wolf a97be0828a Removed RTLIL::SigChunk::compare() 2014-07-22 21:40:52 +02:00
Clifford Wolf 08e1e25169 SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api 2014-07-22 21:33:52 +02:00