mirror of https://github.com/YosysHQ/yosys.git
Fixed a few VS warnings
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18cb8b4636
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34caeeb4f3
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@ -181,7 +181,7 @@ struct PerformanceTimer
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}
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float sec() const {
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return total_ns * 1e-9;
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return total_ns * 1e-9f;
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}
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#else
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static int64_t query() { return 0; }
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@ -898,7 +898,7 @@ struct RTLIL::SigBit
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SigBit() : wire(NULL), data(RTLIL::State::S0) { }
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SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
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SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }
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SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); }
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SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
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SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
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SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }
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SigBit(const RTLIL::SigSpec &sig);
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@ -107,7 +107,7 @@ struct SatGen
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{
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log_assert(timestep != 0);
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std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
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return imported_signals[pf].count(bit);
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return imported_signals[pf].count(bit) != 0;
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}
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void getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)
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