mirror of https://github.com/YosysHQ/yosys.git
Fixed SigBit(RTLIL::Wire *wire) constructor
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@ -852,7 +852,7 @@ struct RTLIL::SigBit
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SigBit() : wire(NULL), data(RTLIL::State::S0) { }
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SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
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SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0) { log_assert(wire && wire->width == 1); }
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SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }
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SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); }
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SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; }
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SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data.bits[index]; }
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