riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Made iterators extend std::iterator and added == operator

This commit is contained in:
William Speirs 2014-10-14 17:10:08 -04:00 committed by Clifford Wolf
parent 069521e2d5
commit 9cb2303799
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
kernel/rtlil.h
View File

@ -920,23 +920,25 @@ struct RTLIL::SigBit
}
};
struct RTLIL::SigSpecIterator
struct RTLIL::SigSpecIterator : public std::iterator<std::input_iterator_tag, RTLIL::SigSpec>
{
RTLIL::SigSpec *sig_p;
int index;
inline RTLIL::SigBit &operator*() const;
inline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; }
inline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }
inline void operator++() { index++; }
};
struct RTLIL::SigSpecConstIterator
struct RTLIL::SigSpecConstIterator : public std::iterator<std::input_iterator_tag, RTLIL::SigSpec>
{
const RTLIL::SigSpec *sig_p;
int index;
inline const RTLIL::SigBit &operator*() const;
inline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; }
inline bool operator==(const RTLIL::SigSpecIterator &other) const { return index == other.index; }
inline void operator++() { index++; }
};