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631 Commits

Author SHA1 Message Date
Diego H 819ca73096 Changes in GoWin synth commands and ALU primitive support 2018-12-03 20:08:35 -06:00
Miodrag Milanovic 43030db5ff Leave only real black box cells 2018-12-02 11:57:50 +01:00
Miodrag Milanovic 83bce9f59c Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
Sylvain Munaut 3e5ab50a73 ice40: Add option to only use CE if it'd be use by more than X FFs 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-27 21:50:42 +01:00
Clifford Wolf dbc4cb8f4a
Merge pull request #697 from eddiehung/xilinx_ps7 
Add support for PS7 block for Xilinx
 2018-11-12 09:09:22 +01:00
Clifford Wolf 317cc9c2b7
Merge pull request #695 from daveshah1/ecp5_bb 
ecp5: Adding some blackbox cells
 2018-11-12 09:08:49 +01:00
Eddie Hung 99a14b0e37 Add support for Xilinx PS7 block 2018-11-10 12:45:07 -08:00
David Shah fae3e645a2 ecp5: Add 'fake' DCU parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-09 18:25:42 +00:00
David Shah 960c8794fa ecp5: Add blackboxes for ancillary DCU cells 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-09 15:18:30 +00:00
David Shah 1f51332808 ecp5: Adding some blackbox cells 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-07 14:56:38 +00:00
Clifford Wolf d084fb4c3f Fix sf2 LUT interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-31 15:36:53 +01:00
Clifford Wolf cf79fd4376 Basic SmartFusion2 and IGLOO2 synthesis support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-31 15:28:57 +01:00
David Shah b65932edc4 ecp5: Remove DSP parameters that don't work 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-22 16:20:38 +01:00
David Shah 101f5234ff ecp5: Add DSP blackboxes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-21 19:27:02 +01:00
David Shah d29b517fef ecp5: Sim model fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-19 15:16:40 +01:00
David Shah 677b8ed3ca ecp5: Add latch inference 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-19 15:16:40 +01:00
Clifford Wolf 24a5c65856
Merge pull request #657 from mithro/xilinx-vpr 
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
 2018-10-18 10:54:03 +02:00
David Shah df4bfa0ad6 ecp5: Disable LSR inversion 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-16 12:48:39 +01:00
David Shah 812538a036 BRAM improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-12 14:22:21 +01:00
David Shah bdfead8c64 ecp5: Adding BRAM maps for all size options 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 17:18:17 +01:00
David Shah 983fb7ff88 ecp5: First BRAM type maps successfully 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 16:35:19 +01:00
David Shah 2ef1af8b58 ecp5: Script for BRAM IO connections 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 16:11:00 +01:00
David Shah 346cbbdbdc ecp5: Adding BRAM initialisation and config 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-09 14:19:04 +01:00
Tim 'mithro' Ansell b111ea1228 xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. 
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
 2018-10-08 16:52:12 -07:00
David Shah 31e22c8b96 ecp5: Add blackbox for DP16KD 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-05 11:35:59 +01:00
Clifford Wolf 5f1fea08d5 Add inout ports to cells_xtra.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-04 11:30:55 +02:00
Tim Ansell ad975fb694
xilinx: Adding missing inout IO port to IOBUF 2018-10-03 16:38:32 -07:00
Clifford Wolf 76baae4b94
Merge pull request #645 from daveshah1/ecp5_dram_fix 
ecp5: Don't map ROMs to DRAM
 2018-10-02 10:00:10 +02:00
David Shah fcd39e1398 ecp5: Don't map ROMs to DRAM 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 18:34:41 +01:00
Clifford Wolf 51f1bbeeb0 Add iCE40 SB_SPRAM256KA simulation model 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-10 11:57:24 +02:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
David Shah 3a3558acce ecp5: Fixing miscellaneous sim model issues 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-16 15:56:12 +02:00
David Shah e9ef077266 ecp5: Fixing 'X' issues with LUT simulation models 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-16 15:20:34 +02:00
David Shah b2c62ff8ef ecp5: ECP5 synthesis fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-16 14:33:13 +02:00
David Shah 459d367913 ecp5: Adding synchronous set/reset support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-14 16:18:01 +02:00
David Shah 241429abac ecp5: Add DRAM match rule 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 16:25:52 +02:00
David Shah 4a60bc83ab ecp5: Cells and mappings fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 16:14:08 +02:00
David Shah b0fea67cc6 ecp5: Fixing arith_map 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 15:49:59 +02:00
David Shah 11c916840d ecp5: Initial arith_map implementation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 15:46:12 +02:00
David Shah c2d7be140a ecp5: Adding basic synth_ecp5 based on synth_ice40 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 14:52:25 +02:00
David Shah eb8f3f7dc4 ecp5: Adding DFF maps 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 14:32:23 +02:00
David Shah 1def34f2a6 ecp5: Adding DRAM map 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 14:08:42 +02:00
David Shah b1b9e23f94 ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 13:27:24 +02:00
David Shah cd65eeb3b3 ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 13:09:18 +02:00
Clifford Wolf 57fc8dd582 Add "synth_ice40 -json" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-13 13:35:10 +02:00
Clifford Wolf 83631555dd Fix ice40_opt for cases where a port is connected to a signal with width != 1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-11 18:12:42 +02:00
Clifford Wolf 7fecc3c199 Make -nordff the default in "prep" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-30 13:17:09 +02:00
Olof Kindgren faac2c5595 Avoid mixing module port declaration styles in ice40 cells_sim.v 
The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
 2018-05-17 13:54:43 +02:00
Clifford Wolf 47eb150eec
Merge pull request #537 from mithro/yosys-vpr 
Improving Yosys when used with VPR
 2018-05-04 12:32:30 +02:00
Clifford Wolf b4c1d3084f Add "synth_intel --noiopads" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-30 13:02:56 +02:00
Tim 'mithro' Ansell d6bdefd2e9 Improving vpr output support. 
* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
 2018-04-18 16:55:12 -07:00
Tim 'mithro' Ansell ca39e493ba synth_ice40: Rework the vpr blif output slightly. 2018-04-18 16:55:08 -07:00
Clifford Wolf 81a457c4a6 Add "synth_ice40 -nodffe" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-16 20:44:26 +02:00
c60k28 efed2420d6 Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device 2018-03-31 22:48:47 -06:00
Robert Ou 14e49fb057 coolrunner2: Add an ANDTERM/XOR between chained FFs 
In some cases (e.g. the low bits of counters) the design might end up
with a flip-flop whose input is directly driven by another flip-flop.
This isn't possible in the Coolrunner-II architecture, so add a single
AND term and XOR in this case.
 2018-03-31 03:54:48 -07:00
Robert Ou cfa3753b89 coolrunner2: Split multi-bit nets 
The PAR tool doesn't expect any "dangling" nets with no drivers nor
sinks. By splitting the nets, clean removes them.
 2018-03-31 02:56:11 -07:00
Robert Ou 8fe9cdf364 coolrunner2: Add extraction for TFFs 2018-03-31 02:54:26 -07:00
Larry Doolittle efaef82f75 Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
Clifford Wolf 6991c132b5 Add Xilinx RAM64X1D and RAM128X1D simulation models 2018-03-07 17:31:48 +01:00
Clifford Wolf 27dd500d31 Add "synth -noshare" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 17:13:45 +01:00
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Robert Ou 2abcd98527 coolrunner2: Move LOC attributes onto the IO cells 2018-01-17 16:17:32 -08:00
Clifford Wolf 9ac560f5d3 Add "dffinit -highlow" and fix synth_intel 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-09 18:42:19 +01:00
Clifford Wolf b66d50e62d Fix minor typo in "prep" help message 2017-12-19 21:44:05 +01:00
Graham Edgecombe f93e6637aa Fix port names in SB_IO_OD 2017-12-10 15:33:38 +00:00
Graham Edgecombe 52ace35a73 Remove trailing comma from SB_IO_OD port list 
This isn't compatible with Icarus Verilog.
 2017-12-10 15:33:38 +00:00
Tim Ansell 3cc31f197c
Fix spelling in -vpr help for synth_ice40 2017-12-08 18:44:45 -08:00
Clifford Wolf 1f6e8f86c5
Merge pull request #462 from daveshah1/up5k 
Add remaining UltraPlus cells to ice40 techlib
 2017-11-28 15:53:53 +01:00
David Shah 5e8d1922a4 Add remaining UltraPlus cells to ice40 techlib 2017-11-28 11:07:49 +00:00
Clifford Wolf 4782d59a3f
Merge pull request #455 from daveshah1/up5k 
Add UltraPlus specific cells to ice40 techlib
 2017-11-18 19:12:48 +01:00
David Shah 0505f1043c Remove unnecessary keep attributes 2017-11-18 17:53:21 +00:00
Clifford Wolf c01df04e32
Merge pull request #453 from dh73/master 
Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
 2017-11-18 09:56:36 +01:00
David Shah 8ae73e60e2 Merge branch 'master' into up5k 2017-11-17 15:15:39 +00:00
Clifford Wolf 234726c655 Add "synth_ice40 -vpr" 2017-11-16 21:37:02 +01:00
David Shah f9f3ca5da0 Add some UltraPlus cells to ice40 techlib 2017-11-16 12:24:35 +00:00
dh73 3fd1d61e2a Initial Cyclone 10 support 2017-11-08 22:45:21 -06:00
dh73 1fc061d90c Organizing Speedster file names 2017-11-08 20:23:55 -06:00
Larry Doolittle 50bcd9a728 Clean whitespace and permissions in techlibs/intel 2017-10-05 16:23:49 +02:00
Clifford Wolf 65f91e5120 Rename "write_verilog -nobasenradix" to "write_verilog -decimal" 2017-10-03 17:31:21 +02:00
dh73 4718e65763 Tested and working altsyncarm without init files 2017-10-01 19:59:45 -05:00
dh73 cbaba62401 Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now 2017-10-01 11:04:17 -05:00
Clifford Wolf c5b204d8d2 Add first draft of eASIC back-end 2017-09-29 17:53:43 +02:00
Clifford Wolf e64b9d5a4d Fix synth_ice40 doc regarding -top default 2017-09-29 17:52:57 +02:00
Andrew Zonenberg 122532b7e1 Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted. 2017-09-14 10:26:32 -07:00
Andrew Zonenberg a84172b23b Initial support for extraction of counters with clock enable 2017-09-14 10:26:10 -07:00
Clifford Wolf 2f75240e36 Merge pull request #406 from azonenberg/coolrunner-techmap 
Coolrunner techmapping improvements
 2017-09-02 13:43:51 +02:00
Robert Ou 5f65e24ccb coolrunner2: Finish fixing special-use p-terms 2017-09-01 07:22:16 -07:00
Robert Ou fa04366f38 coolrunner2: Generate a feed-through AND term when necessary 2017-09-01 07:22:01 -07:00
Robert Ou 6775177171 coolrunner2: Initial fixes for special p-terms 
Certain signals can only be controlled by a product term and not a
sum-of-products. Do the initial work for fixing this.
 2017-09-01 07:21:51 -07:00
Robert Ou 7f08be4304 coolrunner2: Fix mapping of flip-flops 2017-09-01 07:21:39 -07:00
Robert Ou ac84f47829 coolrunner2: Combine some for loops together 2017-09-01 07:21:31 -07:00
Andrew Zonenberg 40021d2fd8 Fixed typo in error message 2017-09-01 06:45:10 -07:00
Andrew Zonenberg fc0c7f74dc Added blackbox $__COUNT_ cell model 2017-09-01 06:44:28 -07:00
Andrew Zonenberg 80aaf50302 Refactoring: moved modules still in cells_sim to cells_sim_wip 2017-09-01 06:44:15 -07:00
Andrew Zonenberg 06754108fc Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-extraction 2017-08-30 16:40:41 -07:00
Andrew Zonenberg 634f18be96 extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos 2017-08-30 16:28:25 -07:00
Andrew Zonenberg 3fc1b9f3fd Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells. 2017-08-28 22:18:57 -07:00
Andrew Zonenberg b5c15636c5 Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass 2017-08-28 22:18:34 -07:00
Andrew Zonenberg c3145863e7 Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're multi-edge-sensitive and getting confused. 2017-08-28 14:25:46 -07:00
Andrew Zonenberg e62362225c Fixed bug causing GP_SPI model to not synthesize 2017-08-27 07:31:48 -07:00
Andrew Zonenberg e6eaf487b6 Fixed more issues with GreenPAK counter sim models 2017-08-15 09:18:36 -07:00
Andrew Zonenberg 3a404be62a Updated PGEN model to have level triggered reset (matches actual hardware behavior 2017-08-15 09:18:27 -07:00
Andrew Zonenberg e5109847c9 Fixed bug in GP_COUNTx model 2017-08-15 09:18:17 -07:00
Andrew Zonenberg 66b256d40e Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high 2017-08-15 09:18:07 -07:00
Clifford Wolf 2cf0b5c157 Merge pull request #381 from azonenberg/countfix 
Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
 2017-08-14 21:47:26 +02:00
Robert Ou 78fd24f40f coolrunner2: Add INVERT parameter to some BUFGs 2017-08-14 12:13:33 -07:00
Robert Ou 1e3ffd57cb coolrunner2: Add FFs with clock enable to cells_sim.v 2017-08-14 12:13:25 -07:00
Andrew Zonenberg 348acbd968 Fixed typo in GP_COUNT8 sim model 2017-08-14 10:45:40 -07:00
Andrew Zonenberg c205d571df Fixed typo in error message 2017-08-14 10:45:40 -07:00
Andrew Zonenberg 0a6c702c41 Changed LEVEL resets for GP_COUNTx to be properly synthesizeable 2017-08-14 10:45:40 -07:00
Andrew Zonenberg 9f3dc59ffe Changed LEVEL resets to be edge triggered anyway 2017-08-14 10:45:40 -07:00
Andrew Zonenberg b049ead042 Added level-triggered reset support to GP_COUNTx simulation models 2017-08-14 10:45:40 -07:00
Andrew Zonenberg ac75524f69 Fixed undeclared "count" in GP_COUNT8_ADV 2017-08-14 10:45:39 -07:00
Andrew Zonenberg db20e3f1c2 Fixed undeclared "count" in GP_COUNT14_ADV 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 3618ca2218 Fixed typo in last commit 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 4da1a327c0 Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else. 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 4504dd78e9 Fixed typo in COUNT8 model 2017-08-14 10:45:39 -07:00
Andrew Zonenberg 60dd5dba7b Moved GP_POR out of digital cells b/c it has delays 2017-08-14 10:45:39 -07:00
Andrew Zonenberg f55d4cc2fd Improved cells_sim_digital model for GP_COUNT8 2017-08-14 10:45:39 -07:00
Andrew Zonenberg fe3a932cfa Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital 2017-08-14 10:45:39 -07:00
Clifford Wolf 8a69759306 Add techlibs/xilinx/lut2lut.v 2017-07-10 12:09:05 +02:00
Clifford Wolf 621787a9e0 Fix some c++ clang compiler errors 2017-07-03 19:38:30 +02:00
Clifford Wolf 5c1c126374 Apply minor coding style changes to coolrunner2 target 2017-07-03 19:35:40 +02:00
Clifford Wolf 6afee022ad Merge pull request #352 from rqou/master 
Initial Coolrunner-II support
 2017-07-03 19:33:36 +02:00
Robert Ou b102c0e254 coolrunner2: Add a few more primitives 
These cannot be inferred yet, but add them to cells_sim.v for now
 2017-06-25 23:58:28 -07:00
Robert Ou 36b75dfcb7 coolrunner2: Initial mapping of latches 2017-06-25 23:58:28 -07:00
Robert Ou 4af5baab21 coolrunner2: Initial mapping of DFFs 
All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N
(negative-edge triggered)
 2017-06-25 23:58:28 -07:00
Robert Ou 1eb5dee799 coolrunner2: Remove redundant INVERT_PTC 2017-06-25 23:58:28 -07:00
Robert Ou ffff001008 coolrunner2: Remove debug prints 2017-06-25 23:58:28 -07:00
Robert Ou 5798105d47 coolrunner2: Correctly handle $_NOT_ after $sop 2017-06-25 23:58:28 -07:00
Robert Ou 908ce3fdce coolrunner2: Also construct the XOR cell in the macrocell 2017-06-25 23:58:28 -07:00
Robert Ou a64b56648d coolrunner2: Initial techmapping for $sop 2017-06-25 23:58:22 -07:00
Andrew Zonenberg cbdddc3af9 greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included 2017-06-24 14:54:07 -07:00
Robert Ou 6e0fb889fa coolrunner2: Initial commit 2017-06-24 07:22:56 -07:00
Clifford Wolf e7a984a4df Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
Andrew Zonenberg 184bd148c9 greenpak4_counters: Added support for parallel output from GP_COUNTx cells 2017-05-22 19:39:55 -07:00
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Larry Doolittle 2021ddecb3 Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
dh73 c27dcc1e47 Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs 2017-04-05 23:01:29 -05:00
Clifford Wolf f3324ed0cc Merge branch 'master' of github.com:cliffordwolf/yosys 2017-02-25 13:08:27 +01:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Andrew Zonenberg 6fed2dc996 Merge https://github.com/cliffordwolf/yosys 2017-02-14 08:29:37 -08:00
Clifford Wolf 2a311c2c38 Fix double-call of log_pop() in synth_greenpak4 2017-02-14 11:57:54 +01:00
Andrew Zonenberg 0d7e71f7ab Merge https://github.com/cliffordwolf/yosys 2017-02-08 22:12:29 -08:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Andrew Zonenberg 27a626ce98 greenpak4: Added POUT to GP_COUNTx cells 2017-01-01 00:56:20 -08:00
Andrew Zonenberg ada98844b9 greenpak4: Added INT pin to GP_SPI 2016-12-21 11:35:29 +08:00
Andrew Zonenberg 6b526e9382 greenpak4: removed unused MISO pin from GP_SPI 2016-12-21 11:33:32 +08:00
Andrew Zonenberg 638f3e3b12 greenpak4: Removed SPI_BUFFER parameter 2016-12-20 13:07:49 +08:00
Andrew Zonenberg 073e8df9f1 greenpak4: replaced MOSI/MISO with single one-way SDAT pin 2016-12-20 12:34:56 +08:00