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3779 Commits

Author SHA1 Message Date
Miodrag Milanovic ad48639cdd Start restoring memory state from VCD/FST 2022-05-04 10:41:04 +02:00
Miodrag Milanovic 3730db4b98 AIM file could have gaps in or between inputs and inits 2022-05-02 11:18:30 +02:00
Jannis Harder e0e31bfc5c
Merge pull request #3257 from jix/tribuf-formal 
tribuf: `-formal` option: convert all to logic and detect conflicts
 2022-04-25 16:23:06 +02:00
Miodrag Milanovic bbfdea2f8a Match $anyseq input if connected to public wire 2022-04-22 17:20:17 +02:00
Miodrag Milanovic 4d80bc24c7 Treat $anyseq as input from FST 2022-04-22 16:23:39 +02:00
Miodrag Milanovic 33f4009bb5 Last sample from input does not represent change 2022-04-22 13:46:11 +02:00
Miodrag Milanovic 83cad82b29 latches are always set to zero 2022-04-22 12:04:05 +02:00
Miodrag Milanovic c989adcc2d If not multiclock, output only on clock edges 2022-04-22 12:03:39 +02:00
Miodrag Milanovic 75032a565d Set init state for all wires from FST and set past 2022-04-22 11:57:39 +02:00
Miodrag Milanovic 8fa2f3b260 Fix multiclock for btor2 witness 2022-04-22 11:53:41 +02:00
Miodrag Milanović c3a3f68b4d
Merge pull request #3280 from YosysHQ/micko/fix_readaiw 
Fix reading aiw from other solvers
 2022-04-18 09:49:21 +02:00
Marcelina Kościelnicka 25ff83f0b5 memory_share: Fix up mismatched address widths. 2022-04-15 22:01:00 +02:00
Marcelina Kościelnicka 48eea3efcf opt_dff: Fix behavior on $ff with D == Q. 2022-04-15 22:00:32 +02:00
Miodrag Milanovic 9508bb2330 Fix reading aiw from other solvers 2022-04-15 11:45:16 +02:00
Jannis Harder bc48500548 tribuf: `-formal` option: convert all to logic and detect conflicts 2022-04-12 12:46:22 +02:00
Miodrag Milanovic 868409361c Use wrap_async_control_gate if ff is fine 2022-04-08 16:30:29 +02:00
Iris Johnson ccc6060f52 Makefile: properly conditionalize features requiring compression. 2022-04-07 20:07:44 -05:00
Catherine 8a1d531b25
Merge pull request #3269 from YosysHQ/micko/fix_autotop 
Reorder steps in -auto-top to fix synth command, fixes #3261
 2022-04-07 22:40:35 +00:00
Marcelina Kościelnicka 376d8cb26f abc: Add support for FFs with reset in -dff 2022-04-07 15:05:02 +02:00
Miodrag Milanovic 977002b1d2 Reorder steps in -auto-top to fix synth command, fixes #3261 2022-04-05 14:02:37 +02:00
Marcelina Kościelnicka 0aec79a0da show: Fix width labels. 
See #3266.
 2022-04-04 22:48:09 +02:00
Miodrag Milanovic 6020ba67ac past_ad initial value setting 2022-04-02 19:13:15 +02:00
Miodrag Milanovic 2c96ecc5f7 setInitState can be only one altering values 2022-04-02 19:13:15 +02:00
Miodrag Milanovic b54aecd80a Set past_d value for init state 2022-04-02 19:13:15 +02:00
Jannis Harder 8ca9737180
Merge pull request #3264 from jix/invalid_ff_dcinit_merge 
opt_merge: Add `-keepdc` option required for formal verification
 2022-04-02 12:41:28 +02:00
Jannis Harder ca5b910296 opt_merge: Add `-keepdc` option required for formal verification 
The `-keepdc` option prevents merging flipflops with dont-care bits in
their initial value, as, in general, this is not a valid transform for
formal verification.

The keepdc option of `opt` is passed along to `opt_merge` now.
 2022-04-01 21:03:20 +02:00
Miodrag Milanovic 86ce441af6 Set init values for wrapped async control signals 2022-04-01 17:44:00 +02:00
Miodrag Milanovic c95b9b4ba5 Support memories in aiw and multiclock 2022-03-31 13:10:13 +02:00
Lofty c1057cb3e0
Merge pull request #3194 from Ravenslofty/abc9-flow3mfs 
abc9: add flow3mfs script
 2022-03-28 15:51:04 +01:00
gatecat 8b64dc1dce abc9_ops: Also derive blackboxes with timing info 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-24 14:36:07 +00:00
Miodrag Milanovic 322ab1cd54 Proper SigBit forming in sim 2022-03-22 14:43:18 +01:00
Miodrag Milanovic ff3b0c2c46 Proper SigBit forming in sim 2022-03-22 14:22:32 +01:00
Miodrag Milanovic 55eed8df57 More verbose warnings 2022-03-18 14:47:35 +01:00
Miodrag Milanovic 1f3423cd7d Recognize registers and set initial state for them in tb 2022-03-16 14:35:39 +01:00
Miodrag Milanovic e217e3017a Update sim help message. 2022-03-16 07:55:57 +01:00
Miodrag Milanović 25d6fdfea7
Merge pull request #3232 from YosysHQ/micko/fst2tb 
Added fst2tb pass for generating testbench
 2022-03-14 20:01:55 +01:00
Miodrag Milanovic f5c20b8286 Added fst2tb pass for generating testbench 2022-03-14 19:06:29 +01:00
Claire Xen 5e2992dae2
Merge pull request #3213 from antonblanchard/abc-typo 
abc: Fix {I} and {P} substitution
 2022-03-14 16:05:23 +01:00
Miodrag Milanović cbece4af0c
Merge pull request #3229 from YosysHQ/micko/sim_date 
Add date parameter to enable full date/time and version info
 2022-03-11 19:02:57 +01:00
Claire Xenia Wolf e21badd4b3 Add "sim -q" option 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-03-11 16:26:11 +01:00
Miodrag Milanovic 37de369ba7 Add date parameter to enable full date/time and version info 2022-03-11 16:01:59 +01:00
Claire Xenia Wolf be32de1caa Small fix in "sim" help message 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-03-11 15:36:23 +01:00
Miodrag Milanovic 5204694123 FstData already do conversion to VCD 2022-03-11 15:21:36 +01:00
Miodrag Milanovic b72c779204 Support cell name in btor witness file 2022-03-11 15:11:14 +01:00
Miodrag Milanovic 357336339a Proper write of memory data 2022-03-11 11:19:53 +01:00
Miodrag Milanovic 295b0d1899 Start work on memory init 2022-03-09 18:34:02 +01:00
Miodrag Milanovic f37ac5d934 Fixes and error check 2022-03-09 09:48:29 +01:00
Miodrag Milanovic ede348cdc2 cleanup 2022-03-07 16:32:32 +01:00
Miodrag Milanovic 1b1ecd4ab0 Error checks for aiger witness 2022-03-07 15:00:14 +01:00
Miodrag Milanovic b6aca1d743 btor2 witness co-simulation 2022-03-07 13:59:36 +01:00
Miodrag Milanović 9581b9adac
Merge pull request #3219 from YosysHQ/micko/quick_vcd 
VCD reader support by using external tool
 2022-03-04 10:42:14 +01:00
Miodrag Milanovic 59983eda17 Add option to ignore X only signals in output 2022-03-02 16:02:13 +01:00
Miodrag Milanovic 48b56a4f7f Write simulation files after simulation is performed 2022-03-02 15:23:07 +01:00
Miodrag Milanovic 28bc88a57e Cleanup 2022-03-02 09:39:22 +01:00
Miodrag Milanovic 94505395a9 Refactor sim output writers 2022-02-28 18:22:39 +01:00
Miodrag Milanovic dfd4c81eac Quick fix 2022-02-28 11:40:06 +01:00
Claire Xenia Wolf 56b968f61c Add writing of aiw files to "sim" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-02-28 10:50:08 +01:00
Claire Xenia Wolf 1fd3a642c9 Hotfix in AIGER witness reader state machine 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-02-28 10:41:44 +01:00
Miodrag Milanovic 8be09b5b24 VCD reader support by using external tool 2022-02-28 09:09:07 +01:00
Miodrag Milanovic 9571acc0bf Support extended aiw format 2022-02-27 16:37:40 +01:00
Miodrag Milanovic fca168797e Fix for last clock edge data 2022-02-25 16:15:32 +01:00
Claire Xenia Wolf ca261d3c28 Experimental sim changes 2022-02-25 16:02:06 +01:00
Anton Blanchard 89300b2dca abc: Fix {I} and {P} substitution 
We were searching for {D} after the first match of {I} or {P}.
 2022-02-23 18:54:28 +11:00
Claire Xen a41c1df76f
Merge pull request #3211 from YosysHQ/micko/witness 
Add support for AIGER witness files in "sim" command
 2022-02-22 16:22:06 +01:00
Miodrag Milanovic fd3f08753a Fix handling of ce_over_srst 2022-02-21 16:36:12 +01:00
Claire Xenia Wolf 1aa9ad25d0 Fix cycle 0 in aiger witness co-simulation 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-02-18 16:27:41 +01:00
Miodrag Milanovic 41754b4207 Added AIGER witness file co simulation 2022-02-18 15:04:02 +01:00
Miodrag Milanovic 13a5c28459 simplify logic of handling flip-flops and latches 2022-02-18 09:17:36 +01:00
Miodrag Milanovic 61752b255f Review cleanup 2022-02-17 17:18:36 +01:00
Miodrag Milanovic fb22d7cdc4 Add support for various ff/latch cells simulation 2022-02-16 13:27:59 +01:00
Claire Xen 49545c73f7
Merge branch 'master' into clk2ff-better-names 2022-02-11 16:03:12 +01:00
Claire Xen e016518866
Merge pull request #2019 from boqwxp/glift 
Add `glift` command for creating gate-level information flow tracking models and optimization problems
 2022-02-11 15:51:24 +01:00
bfg86 7ac98d1c87 Add -suffix option to rename -wire. 
See #3195
 2022-02-11 00:05:13 +01:00
Lofty 5ac32ea68c abc9: add flow3mfs script 2022-02-10 18:28:35 +00:00
Miodrag Milanović d7f7227ce8
Merge pull request #3185 from YosysHQ/micko/co_sim 
Add co-simulation in sim pass
 2022-02-07 16:36:43 +01:00
Miodrag Milanovic c0a156bcb4 Error detection for co-simulation 2022-02-04 11:11:36 +01:00
Miodrag Milanovic 6db23de7b1 bug fix and cleanups 2022-02-04 10:01:06 +01:00
YRabbit f5609d52c4 Correct a typo in the manual 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2022-02-02 21:14:38 +10:00
Miodrag Milanovic 990aee5531 respect hide_internal flag 2022-02-02 10:15:22 +01:00
Miodrag Milanovic 169ffcd2fb unify cycles counting and cleanup 2022-02-02 10:08:23 +01:00
Miodrag Milanovic 820b2fdd65 added stimulus mode and param check 2022-02-02 09:37:32 +01:00
Scott Thibault 0a6e2bd5d5 Update comment 2022-02-02 03:21:09 +01:00
Scott Thibault e04ac4e9e9 Fix unextend method for signed constants 2022-02-02 03:21:09 +01:00
Miodrag Milanovic 8ba2000a50 error when no signal found 2022-01-31 17:41:50 +01:00
Miodrag Milanovic 1b5ff92e62 Cleanup 2022-01-31 13:45:28 +01:00
Miodrag Milanovic eabd0ff115 Compare bits when not all are defined 2022-01-31 13:41:02 +01:00
Miodrag Milanovic 26de52fa09 Cleanup 2022-01-31 12:00:15 +01:00
Miodrag Milanovic 6513300db7 message update 2022-01-31 11:41:52 +01:00
Miodrag Milanovic 543feb75cb Display simulation time data 2022-01-31 10:52:47 +01:00
Miodrag Milanovic a6959d30df Use edges when explicit 2022-01-31 09:38:25 +01:00
Miodrag Milanovic cbadfa0268 Updating initial state and checks 2022-01-31 09:19:34 +01:00
Miodrag Milanovic 190e44f0da Fix scope 2022-01-31 08:56:29 +01:00
Marcelina Kościelnicka 07a657fb0c opt_reduce: Add $bmux and $demux optimization patterns. 2022-01-30 03:37:52 +01:00
Marcelina Kościelnicka 93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Miodrag Milanovic f04d1398e5 check if stop before start 2022-01-28 19:41:43 +01:00
Miodrag Milanovic ecbba625c4 set initial state, only flip-flops 2022-01-28 15:59:13 +01:00
Miodrag Milanovic cb12b7c4d8 ignore not found private signals 2022-01-28 14:20:16 +01:00
Miodrag Milanovic 81b76155d6 recursive check 2022-01-28 13:24:38 +01:00
Miodrag Milanovic 4f75a2ca1b Do actual compare 2022-01-28 12:50:41 +01:00
Miodrag Milanovic 3e35de2be1 Add more options and time handling 2022-01-28 10:18:02 +01:00
Marcelina Kościelnicka db33b1e535 opt_dff: Don't mutate muxes while ModWalker is active. 2022-01-28 08:55:56 +01:00
Marcelina Kościelnicka 1759c80a3f memory_bram: Make use of new mem emulation functions to map more RAMs. 2022-01-27 19:31:27 +01:00
Miodrag Milanovic 40018e191b Display values of outputs 2022-01-26 16:52:36 +01:00
Miodrag Milanovic be7be63fec Check if stimulated 2022-01-26 15:51:43 +01:00
Miodrag Milanovic 9a8939f0a4 Read fst and use data to set inputs 2022-01-26 15:50:38 +01:00
Miodrag Milanovic ccfc00705a Add ability to write to FST file 2022-01-26 09:26:19 +01:00
Austin Seipp b022fe61a7 opt_dff: fix sequence point copy paste bug 
Newer GCCs emit the following warning for opt_dff:

    passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point]
      560 |      ff.has_clk = ff.has_ce = ff.has_clk = false;
          |      ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Which is correct: the order of whether the read or write of has_clk
occurs first is undefined since there is no sequence point between them.

This is almost certainly just a typo/copy paste error and objectively
wrong, so just fix it.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2022-01-04 18:18:08 +01:00
Marcelina Kościelnicka f84c9d8e17 memory_share: Fix SAT-based sharing for wide ports. 
Fixes #3117.
 2021-12-20 18:40:14 +01:00
Catherine 4f1d62d9b2 bugpoint: avoid infinite loop between -connections and -wires. 
Fixes #3113.
 2021-12-15 08:17:02 +00:00
Marcelina Kościelnicka 0aad88a2fb Add clean_zerowidth pass, use it for Verilog output. 
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
 2021-12-12 19:56:50 +01:00
Marcelina Kościelnicka 1184a7f3b4 opt_mem_priority: Fix non-ascii char in help message. 
This is a fixed version of #3072.
 2021-12-09 00:56:14 +01:00
Lofty 77327b2544 sta: very crude static timing analysis pass 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2021-11-25 17:20:27 +01:00
Marcelina Kościelnicka 107aad2cd2 show: Fix wire bit indexing. 
Fixes #3078.
 2021-11-12 15:09:58 +01:00
Claire Xen 4699ddcc1b
Merge pull request #3077 from YosysHQ/claire/genlib 
Add genlib support to ABC command
 2021-11-10 20:02:34 +01:00
Claire Xen c77d5a2aac
Spelling fix in abc.cc 2021-11-10 16:47:54 +01:00
Claire Xenia Wolf 093e287a1e Add genlib support to ABC command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-11-10 16:40:54 +01:00
Marcelina Kościelnicka 506acd52de iopadmap: Fix ebmarassing typo 2021-11-10 14:56:03 +01:00
Marcelina Kościelnicka 15b0d717ed iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
Pepijn de Vos 0c7461fe5e
gowin: widelut support (#3042) 2021-11-06 16:09:30 +01:00
Miodrag Milanovic d5de2a0cdb Make it work on all 2021-11-05 10:51:58 +01:00
Miodrag Milanovic cbb6887ac8 Correct way of setting maybe_unsused on labels 2021-11-05 10:36:15 +01:00
Marcelina Kościelnicka f346868ccc flatten: Keep sigmap around between flatten_cell invocations. 
Fixes #3064.
 2021-11-02 13:18:15 +01:00
Marcelina Kościelnicka 8d881826eb proc_dff: Emit $aldff. 2021-10-27 14:14:24 +02:00
Marcelina Kościelnicka 0a0df8d38c dfflegalize: Refactor, add aldff support. 2021-10-27 14:14:01 +02:00
Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections 
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
 2021-10-25 18:25:50 -07:00
Rupert Swarbrick bd16d01c0e Split out logic for reprocessing an AstModule 
This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
 2021-10-25 18:25:50 -07:00
Marcelina Kościelnicka 5cebf6a8ef Change implicit conversions from bool to Sig* to explicit. 
Also fixes some completely broken code in extract_reduce.
 2021-10-21 20:20:31 +02:00
Marcelina Kościelnicka e64456f920 extract_reduce: Refactor and fix input signal construction. 
Fixes #3047.
 2021-10-21 04:10:01 +02:00
Paul Annesley 3efc14f5ad dfflegalize: remove redundant check for initialized dlatch 
This if condition is repeated verbatim, and I can't imagine a legitimate
way the inputs could change in between. I imagine it's a copy/paste
mistake.
 2021-10-17 22:10:37 +02:00
Marcelina Kościelnicka 4e70c30775 FfData: some refactoring. 
- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
 2021-10-07 04:24:06 +02:00
Marcelina Kościelnicka e7d89e653c Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka ba0723cad7 zinit: Refactor to use FfData. 2021-10-02 20:19:48 +02:00
Marcelina Kościelnicka 63b9df8693 kernel/ff: Refactor FfData to enable FFs with async load. 
- *_en is split into *_ce (clock enable) and *_aload (async load aka
  latch gate enable), so both can be present at once
- has_d is removed
- has_gclk is added (to have a clear marker for $ff)
- d_is_const and val_d leftovers are removed
- async2sync, clk2fflogic, opt_dff are updated to operate correctly on
  FFs with async load
 2021-10-02 20:19:48 +02:00
Marcelina Kościelnicka f9aad606ca simplemap: refactor to use FfData. 2021-10-02 03:24:57 +02:00
Eddie Hung 96b6410dcb
abc9: make re-entrant (#2993) 
* Add testcase

* Cleanup some state at end of abc9

* Re-assign abc9_box_id from scratch

* Suppress delete unless prep_bypass did something
 2021-09-09 10:06:31 -07:00
Eddie Hung 65316ec926
abc9: holes module to instantiate cells with NEW_ID (#2992) 
* Add testcase

* holes module to instantiate cells with NEW_ID
 2021-09-09 10:06:20 -07:00
Eddie Hung f03e2c30aa
abc9: replace cell type/parameters if derived type already processed (#2991) 
* Add close bracket

* Add testcase

* Replace cell type/param if in unmap_design

* Improve abc9_box error message too

* Update comment as per review
 2021-09-09 10:05:55 -07:00
Marcelina Kościelnicka 9cbff3a4a9 opt_merge: Remove and reinsert init when connecting nets. 
Mutating the SigMap by adding a new connection will throw off FfInitVals
index.  Work around this by removing the relevant init values from index
whenever we connect nets, then re-add the new init value.

Should fix #2920.
 2021-08-22 18:34:11 +02:00
Marcelina Kościelnicka 62d41d4639 opt_clean: Make the init attribute follow the FF's Q. 
Previously, opt_clean would reconnect all ports (including FF Q ports)
to a "canonical" SigBit chosen by complex rules, but would leave the
init attribute on the old wire.  This change applies the same
canonicalization rules to the init attributes, ensuring that init moves
to wherever the Q port moved.

Part of another jab at #2920.
 2021-08-22 15:38:29 +02:00
Marcelina Kościelnicka faacc7ad89 proc_prune: Make assign removal and promotion per-bit, remember promoted bits. 
Fixes #2962.
 2021-08-14 15:26:11 +02:00
Marcelina Kościelnicka f791328506 Add opt_mem_widen pass. 
If all of us are wide, then none of us are!
 2021-08-14 01:06:23 +02:00
Marcelina Kościelnicka 1f74ec3535 memory_share: Add -nosat and -nowiden options. 
This unlocks wide port recognition by default.
 2021-08-14 00:09:04 +02:00
Marcelina Kościelnicka 9fdedf4d1c memory_dff: Recognize soft transparency logic. 2021-08-13 23:08:32 +02:00
Marcelina Kościelnicka 616ace2d92 Add new opt_mem_priority pass. 2021-08-13 11:58:52 +02:00
Miodrag Milanović 30927df881
Merge pull request #2932 from YosysHQ/mwk/logger-check-expected 
logger: Add -check-expected subcommand.
 2021-08-13 11:45:20 +02:00
Marcelina Kościelnicka d0d9aca2c3 memory_share: Pass addresses through sigmap_xmux everywhere. 
This fixes wide port recognition in some cases.
 2021-08-13 01:17:55 +02:00
Marcelina Kościelnicka c58ac63c97 logger: Add -check-expected subcommand. 
This allows us to have multiple "expect this warning" calls in a single
long script, covering only as many passes as necessary.
 2021-08-12 17:41:39 +02:00
Marcelina Kościelnicka 72d86c327e memory_dff: Recognize read ports with reset / initial value. 2021-08-11 14:17:48 +02:00
Marcelina Kościelnicka 24027b5446 proc_memwr: Use the v2 memwr cell. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00