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2032 Commits

Author SHA1 Message Date
Marcelina Kościelnicka 90b89e5ebc
Merge pull request #2232 from YosysHQ/mwk/gowin-sim-init 
gowin: Fix INIT values in sim library.
 2020-07-05 12:02:31 +02:00
Dan Ravensloft b004f09018 intel_alm: DSP inference 2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka 1fc8c3a0d1 ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00
Marcelina Kościelnicka 9beed4d771 gowin: Fix INIT values in sim library. 2020-07-05 03:03:48 +02:00
Dan Ravensloft 01772dec8c gowin: replace determine_init with setundef 2020-07-04 23:26:56 +02:00
Marcelina Kościelnicka 3ca2de0f77 synth_intel_alm: Use dfflegalize. 2020-07-04 22:56:16 +02:00
Marcelina Kościelnicka 6b0ac04698 efinix: Nuke efinix_gbuf in favor of clkbufmap. 2020-07-04 20:53:43 +02:00
Dan Ravensloft c6765443fd Improve MISTRAL_FF specify rules 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2020-07-04 19:45:10 +02:00
Eddie Hung 2bdced0d68 intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF 2020-07-04 19:45:10 +02:00
Eddie Hung 3db3e1e149 intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY 2020-07-04 19:45:10 +02:00
Dan Ravensloft 83cde2d02b intel_alm: ABC9 sequential optimisations 2020-07-04 19:45:10 +02:00
Marcelina Kościelnicka 817ae04ee0 simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
Marcelina Kościelnicka 88e7f90663 Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
Marcelina Kościelnicka 832acc8648 Add new FF types to simplemap. 2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka b0bee396a8 Add new builtin FF types 
The new types include:

- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)

The new FF types are not actually used anywhere yet (this is left
for future commits).
 2020-06-23 15:40:02 +02:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Xark 9509444ef2 Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH 2020-06-14 00:45:22 -07:00
Dan Ravensloft 8b4eb78849 intel_alm: fix DFFE matching 2020-06-11 19:55:51 +02:00
Claire Wolf 3c7122c378 Do not optimize away FFs in "prep" and Verific fron-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-09 15:54:14 +02:00
Eddie Hung 69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve 
abc9: -dff improvements
 2020-06-04 08:15:25 -07:00
Eddie Hung d3b53bc495 abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
Xiretza edd8ff2c07
Add flooring division operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
 2020-05-28 22:59:04 +02:00
Xiretza 17163cf43a
Add flooring modulo operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
 2020-05-28 22:59:03 +02:00
Eddie Hung 5b81df57c8 xilinx: tidy up cells_sim.v a little 2020-05-25 09:48:11 -07:00
Eddie Hung 76e0cc8276 ecp5: cleanup unused +/ecp5/abc9_model.v 2020-05-23 08:17:40 -07:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Eddie Hung 67fc0c3698 abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ 
instead of moving them to $__ prefix
 2020-05-14 16:44:35 -07:00
Eddie Hung 13f9d65b6f abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it 2020-05-14 10:33:57 -07:00
Eddie Hung 97a0a04314 abc9_ops/xaiger: further reducing Module::derive() calls by ... 
replacing _all_ (* abc9_box *) instantiations with their derived types
 2020-05-14 10:33:57 -07:00
Eddie Hung e79127fceb Cleanup; reduce Module::derive() calls 2020-05-14 10:33:57 -07:00
Eddie Hung cea614f5ae ecp5: latches_map.v if *not* -asyncprld 2020-05-14 10:33:57 -07:00
Eddie Hung fdc340db8e ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v 2020-05-14 10:33:57 -07:00
Eddie Hung 39759d5f0e ecp5: fix rebase mistake 2020-05-14 10:33:57 -07:00
Eddie Hung ca4f8c9444 xilinx: gate specify/attributes from iverilog 2020-05-14 10:33:57 -07:00
Eddie Hung 57c478c537 abc9: only do +/abc9_map if `DFF 2020-05-14 10:33:57 -07:00
Eddie Hung 8cda29137e ecp5: TRELLIS_FF bypass path only in async mode 2020-05-14 10:33:56 -07:00
Eddie Hung 6c34945371 xilinx/ice40/ecp5: zinit requires selected wires, so select them all 2020-05-14 10:33:56 -07:00
Eddie Hung a323881e15 xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells 2020-05-14 10:33:56 -07:00
Eddie Hung 7cd3f4a79b abc9_ops: add -prep_bypass for auto bypass boxes; refactor 
Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
 2020-05-14 10:33:56 -07:00
Eddie Hung 722540dbf9 abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00
Eddie Hung 8fbb55f4ab synth_*: no need to explicitly read +/abc9_model.v 2020-05-14 10:33:56 -07:00
Eddie Hung 48052ad813 abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too 2020-05-14 10:33:56 -07:00
Eddie Hung 4cec21b93e abc9_ops: -prep_dff_map to error if async flop found 2020-05-14 10:33:56 -07:00
Eddie Hung 6c66030dfb Uncomment negative setup times; clamp to zero for connectivity 2020-05-14 10:33:56 -07:00
Eddie Hung 0d84ff3fc4 Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init" 
This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b.
 2020-05-14 10:33:56 -07:00
Eddie Hung a52f779eca ecp5: (* abc9_flop *) gated behind YOSYS 2020-05-14 10:33:56 -07:00
Eddie Hung 34c7732642 ecp5: add synth_ecp5 -dff to work with -abc9 2020-05-14 10:33:56 -07:00
Eddie Hung 23c53a6bdd ice40: synth_ice40 cleanup 2020-05-14 10:33:56 -07:00
Eddie Hung 5d5029fa75 ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init 2020-05-14 10:33:56 -07:00
Eddie Hung fe7965e0ee ice40: add synth_ice40 -dff option, support with -abc9 2020-05-14 10:33:56 -07:00
Eddie Hung 4a10c87ae1 ice40: split out cells_map.v into ff_map.v 2020-05-14 10:33:56 -07:00
Eddie Hung c10757a8ea synth_xilinx: rename dff_mode -> dff 2020-05-14 10:33:56 -07:00
Eddie Hung 95763c8d18 abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes 2020-05-14 10:33:56 -07:00
Claire Wolf ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto 
ast: swap range regardless of range_left >= 0
 2020-05-14 18:06:18 +02:00
Eddie Hung 27b7ffc754 ice40: fix ICESTORM_LC process sensitivity 2020-05-12 15:40:48 -07:00
Eddie Hung 4ecae8a673 ice40: fix whitespace 2020-05-12 15:40:13 -07:00
David Shah 95fb3cf487 ecp5: Add missing SERDES parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2020-05-12 21:12:26 +01:00
Dan Ravensloft 5b779f7f4e intel_alm: direct LUTRAM cell instantiation 
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
 2020-05-07 21:03:13 +02:00
Eddie Hung 004999218f techlibs/common: more robustness when *_WIDTH = 0 2020-05-05 08:01:27 -07:00
Eddie Hung e6b55e8b38 synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad 2020-05-04 11:44:00 -07:00
whitequark 26cda3c247 gowin,ecp5: remove generated files in `make clean`. 2020-04-24 23:26:39 +00:00
Dan Ravensloft 4ca5f9799b intel_alm: cleanup duplication 2020-04-24 11:26:48 +02:00
Dan Ravensloft 3d149aff73 intel_alm: work around a Quartus ICE 2020-04-23 11:03:28 +02:00
Eddie Hung 51ae0f4e20 ecp5: ecp5_gsr to skip cells that don't have GSR parameter again 2020-04-22 17:53:08 -07:00
Eddie Hung d2d90e4504 xilinx: improve xilinx_dffopt message 2020-04-22 16:25:23 -07:00
Eddie Hung 7f33a0294b Cleanup use of hard-coded default parameters in light of #1945 2020-04-22 12:02:30 -07:00
Dan Ravensloft 16a3048308 intel_alm: Documentation improvements 2020-04-21 19:38:15 +02:00
Marcelina Kościelnicka b4d76309e1 Use default parameter value in getParam 
Fixes #1822.
 2020-04-21 19:09:00 +02:00
David Shah 1664bcda12 ecp5: Force SIGNED ports to be 1 bit 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-16 16:38:19 +01:00
Marcelina Kościelnicka 53ba3cf718 Fix the truth table for $_SR_* cells. 
This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.

Also get rid of sim-synth mismatch in the models while we're at it.
 2020-04-15 17:17:48 +02:00
Marcelina Kościelnicka 38a0c30d65 Get rid of dffsr2dff. 
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
 2020-04-15 16:22:37 +02:00
Dan Ravensloft 43cc6bd8a1 synth_intel_alm: VQM support 2020-04-15 16:15:25 +02:00
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs 
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
 2020-04-15 11:40:41 +02:00
whitequark 93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style 
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
 2020-04-10 14:51:01 +00:00
Eddie Hung d61a6b81fc
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu 
"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
 2020-04-03 16:28:25 -07:00
Eddie Hung 7b38cde2df cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp 2020-04-03 14:28:22 -07:00
Eddie Hung 7b09a20c0c cmp2lcu: fail if `LUT_WIDTH < 2 2020-04-03 14:28:22 -07:00
Eddie Hung 34c9b83854 synth: only techmap cmp2{lut,lcu} if -lut 2020-04-03 14:28:22 -07:00
Eddie Hung 5b87720b16 synth: use +/cmp2lcu.v in generic 'synth' too 2020-04-03 14:28:22 -07:00
Eddie Hung 2bf03c6ae0 Cleanup +/cmp2lut.v 2020-04-03 14:28:22 -07:00
Eddie Hung 051aefc3c2 synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse' 2020-04-03 14:28:22 -07:00
Eddie Hung 99a32432aa +/cmp2lcu.v to work efficiently for fully/partially constant inputs 2020-04-03 14:28:22 -07:00
Eddie Hung f68d723cdc Refactor +/cmp2lcu.v into recursive techmap 2020-04-03 14:28:22 -07:00
Eddie Hung 8e851badc4 Cleanup 2020-04-03 14:28:22 -07:00
Eddie Hung da880d5016 Cleanup cmp2lcu.v 2020-04-03 14:28:22 -07:00
Eddie Hung 9b63700678 techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu 2020-04-03 14:28:22 -07:00
Eddie Hung fffe42d4c1 cmp2lut: comment out unused since 362f4f9 2020-04-03 14:28:04 -07:00
whitequark 763401fc82 ecp5: do not map FFRAM if explicitly requested otherwise. 2020-04-03 05:51:40 +00:00
whitequark ebee746ad2 ice40: do not map FFRAM if explicitly requested otherwise. 2020-04-03 05:51:40 +00:00
Eddie Hung 5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings 
IdString: use more ID::*, make them easier to use, speed up IdString::in()
 2020-04-02 11:47:25 -07:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Marcin Kościelnicki 0ed1062557 simcells.v: Generate the fine FF cell types by a python script. 
This makes adding more FF types in the future much more manageable.

Fixes #1824.
 2020-04-02 18:37:15 +02:00
Eddie Hung fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Alberto Gonzalez fc6b898178
Fix indentation in `techlibs/ice40/synth_ice40.cc`. 2020-04-01 16:29:56 +00:00
David Shah beab15b77c
Merge pull request #1794 from YosysHQ/dave/mince-abc9-fix 
ice40: Map unmapped 'mince' DFFs to gate level
 2020-03-21 17:35:27 +00:00
Sylvain Munaut c15ce5a73e ice40: Fix typos in SPRAM ABC9 timing specs 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-03-20 22:19:55 +01:00
David Shah e813624f21 ice40: Map unmapped 'mince' DFFs to gate level 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-20 20:29:16 +00:00
Marcin Kościelnicki 9b982e929c xilinx: Mark IOBUFDS.IOB as external pad 2020-03-20 14:37:38 +01:00
Sylvain Munaut acd9eeef7c ice40: Fix SPRAM model to keep data stable if chipselect is low 
According to the official simulation model, and also cross-checked
on real hardware, the data output of the SPRAM when chipselect is
low is kept stable. It doesn't go undefined.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-03-14 21:01:42 +01:00
Miodrag Milanovic acb341745d Fix invalid verilog syntax 2020-03-14 14:33:44 +01:00
N. Engelhardt 282d331e7e
Merge pull request #1716 from zeldin/ecp5_fix 
ecp5: remove unused parameter from \$__ECP5_PDPW16KD
 2020-03-09 11:04:08 +01:00
N. Engelhardt 8a39a580e1 remove unused parameters 2020-03-06 16:45:36 +01:00
Eddie Hung 69f1555058 ice40: fix specify for ICE40_{LP,U} 2020-03-05 08:11:49 -08:00
Eddie Hung 0930c00f03 ice40: fix implicit signal in specify, also clamp negative times to 0 2020-03-04 15:28:17 -08:00
Eddie Hung 6eb528277e
Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1 
xilinx: cleanup DSP48E1 handling for abc9
 2020-03-04 13:37:09 -08:00
Eddie Hung 7b543fdb0c xilinx: consider DSP48E1.ADREG 2020-03-04 12:04:02 -08:00
Eddie Hung 512596760b xilinx: cleanup DSP48E1 handling for abc9 2020-03-04 11:31:12 -08:00
Eddie Hung f65fc845e5 xilinx: improve specify for DSP48E1 2020-03-04 11:31:12 -08:00
Eddie Hung 78d4fff69d xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v 2020-03-04 11:31:12 -08:00
N. Engelhardt 0ec971444b
Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc 
Add -flowmap option to `synth{,_ice40}`
 2020-03-03 19:15:41 +01:00
Eddie Hung 4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify 
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
 2020-03-02 12:32:27 -08:00
R. Ou 7932672fc2 coolrunner2: Attempt to give wires/cells more meaningful names 2020-03-02 01:40:57 -08:00
R. Ou b9c98e0100 coolrunner2: Fix invalid multiple fanouts of XOR/OR gates 
In some cases where multiple output pins share identical combinatorial
logic, yosys would only generate one $sop cell and therefore one
MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid,
so make the fixup pass duplicate cells when necessary. For example,
fixes the following code:

module top(input a, input b, input clk_, output reg o, output o2);

wire clk;

BUFG bufg0 (
    .I(clk_),
    .O(clk),
);

always @(posedge clk)
    o = a ^ b;
assign o2 = a ^ b;

endmodule
 2020-03-02 01:07:15 -08:00
R. Ou a618004897 coolrunner2: Fix packed register+input buffer insertion 
The register will be packed with the input buffer if and only if the
input buffer doesn't have any other loads.
 2020-03-02 00:32:57 -08:00
R. Ou a6aeee4e1a coolrunner2: Insert many more required feedthrough cells 2020-03-01 16:56:21 -08:00
Dan Ravensloft d7987fec12 Add -flowmap to synth and synth_ice40 2020-02-28 14:29:57 +00:00
Eddie Hung 090e54569a Remove RAMB{18,36}E1 from cells_xtra.py 2020-02-27 10:33:04 -08:00
Eddie Hung 376319dc8d xilinx: Update RAMB* specify entries 2020-02-27 10:17:29 -08:00
Eddie Hung 6bd9550100 ice40: add delays to SB_CARRY 2020-02-27 10:17:29 -08:00
Eddie Hung 3b74e0fa45 xilinx: add delays to INV 2020-02-27 10:17:29 -08:00
Eddie Hung aa969f8778 More +/ice40/cells_sim.v fixes 2020-02-27 10:17:29 -08:00
Eddie Hung b0ffd9cd8b Make +/xilinx/cells_sim.v legal 2020-02-27 10:17:29 -08:00
Eddie Hung 1ef1ca812b Get rid of (* abc9_{arrival,required} *) entirely 2020-02-27 10:17:29 -08:00
Eddie Hung 3ea5506f81 abc9_ops: use TimingInfo for -prep_{lut,box} too 2020-02-27 10:17:29 -08:00
Eddie Hung 7d86aceee3 Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy 2020-02-27 10:17:29 -08:00
Eddie Hung 3728ef1765 ice40: fix specify for inverted clocks 2020-02-27 10:17:29 -08:00
Eddie Hung aac309626b Fix tests by gating some specify constructs from iverilog 2020-02-27 10:17:29 -08:00
Eddie Hung e22fee6cdd abc9_ops: ignore (* abc9_flop *) if not '-dff' 2020-02-27 10:17:29 -08:00
Eddie Hung a76520112d ice40: specify fixes 2020-02-27 10:17:29 -08:00
Eddie Hung fb60d82971 ice40: move over to specify blocks for -abc9 2020-02-27 10:17:29 -08:00
Eddie Hung a85c55113f synth_ecp5: use +/abc9_model.v 2020-02-27 10:17:29 -08:00
Eddie Hung 8408c13405 Update xilinx for ABC9 2020-02-27 10:17:29 -08:00
Eddie Hung ac24a23e31 Create +/abc9_model.v for $__ABC9_{DELAY,FF_} 2020-02-27 10:17:29 -08:00
Eddie Hung d2284715fa ecp5: remove small LUT entries 2020-02-27 10:17:29 -08:00
Eddie Hung ccc84f8923 Fix commented out specify statement 2020-02-27 10:17:29 -08:00
Eddie Hung 12d70ca8fb xilinx: improve specify functionality 2020-02-27 10:17:29 -08:00
Eddie Hung 46a89d7264 ecp5: deprecate abc9_{arrival,required} and *.{lut,box} 2020-02-27 10:17:29 -08:00
Eddie Hung 577545488a xilinx: use specify blocks in place of abc9_{arrival,required} 2020-02-27 10:17:29 -08:00
Eddie Hung 0e7c55e2a7 Auto-generate .box/.lut files from specify blocks 2020-02-27 10:17:29 -08:00
Eddie Hung 74f49b1f55 abc9_ops: -prep_box, to be called once 2020-02-27 10:17:29 -08:00
Eddie Hung 5643c1b8c5 abc9_ops: -prep_lut and -write_lut to auto-generate LUT library 2020-02-27 10:17:29 -08:00
Claire Wolf ab8826ae36
Merge pull request #1709 from rqou/coolrunner2_counter 
Improve CoolRunner-II optimization by using extract_counter pass
 2020-02-27 19:05:56 +01:00
Claire Wolf 47228feb77
Merge pull request #1708 from rqou/coolrunner2-buf-fix 
coolrunner2: Separate and improve buffer cell insertion pass
 2020-02-27 19:03:59 +01:00
Piotr Binkowski 62ab100c61 xilinx: mark IOBUFDSE3 IOB pin as external 2020-02-27 13:15:57 +01:00
Marcus Comstedt 48a9b4f616 ecp5: Add missing parameter to \$__ECP5_PDPW16KD 2020-02-22 15:51:25 +01:00
R. Ou 13d0ff4a5f coolrunner2: Use extract_counter to optimize counters 
This tends to make much more efficient pterm usage compared to just
throwing the problem at ABC
 2020-02-17 03:09:40 -08:00
R. Ou 6a0682f5a0 coolrunner2: Separate and improve buffer cell insertion pass 
The new pass will contain all of the logic for inserting "passthrough"
product term and XOR cells as appropriate for the architecture. For
example, this commit fixes connecting an input pin directly to another
output pin with no logic in between.
 2020-02-16 20:25:46 -08:00
Miodrag Milanovic cd5c177739 Remove executable flag from files 2020-02-15 10:36:44 +01:00
Eddie Hung 00d41905df abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr 2020-02-13 12:33:58 -08:00
Eddie Hung c244b27b6d abc9: cleanup 2020-02-10 10:17:23 -08:00