zero level outputs when the user project area is powered down.
That allows the synthesis tools to buffer these outputs. The
protection from floating inputs is left as-is, but all logic that
was unnecessary to be specified by gate instances has been changed
to RTL. This leaves only a handful of signals (logic analyzer input,
user IRQ, and wishbone data out and acknowledge out) to be handled
by explicit logic gate instances.
the left hand side of caravan from gpio_defaults_block_14 to
gpio_defaults_block_25. Otherwise, the script that generates the
custom user configuration won't be able to change the defaults
for GPIO 25.
- high level changes:
* add larger buffers on output ports
* add buffers on input ports
* adjust sdc file increasing output load and setting a high transition
- detailed changes:
* add interactive script for openlane where the order of events is a bit shuffled
- to add obstruction before pdn
- to manually insert buffers on some ports
- to manually remove buffers inserted by synthesis on for example serial_clock_out
* change openlane config adding extra row and columns to increase the space and fit the
added buffers
* change config to enable buffering
* increase density for better placement?
* change the cell exclude list. some excluded cells didn't make sense
* ef decap cells break dynamic sims?
* add custom pdn script for to duplicate the old pdn
- misc changes:
* fix openlane makefile to properly detect interactive script
!important still need to run dynamic simulations
!important depends on some updates to openlane
Corrected the pad constant connections to all be in the correct domain
(1.8V or 3.3V). Created a new "constant_block" module that generates
a single constant 1 and 0 value in the 1.8V domain, and used 7 of these
in the chip_io (and chip_io_alt) modules to create the 1.8V domain
constant signals for the seven pads belonging to the management (clock,
reset, flash SPI, and management GPIO).
inputs that are permanently tied low or high come from either
the local "TIE" pad connections (if they are in the 3.3V
domain) or from a constant one wire in the 1.8V domain that
is generated in the gpio_control_block module and exported
to the chip_io (or chip_io_alt) module.
from the data and replace them with a single flop clocked on the
negative edge of the serial clock. This will completely avoid hold
violations by ensuring that the block's output data bit does not
change anywhere near the clock rising edge, so clocks do not have
to be tightly aligned among all of the GPIO blocks.
does not pass through an inverter, so that the input can remain
unconnected. Rewired the existing implementation to use an
alternative gate that has an inverting input so that the
user_gpio_out signal can be left undriven when the GPIOs are in
the management enable state. This is a simple logic refactoring
and does not change the logic function. The manual rewiring has
been confirmed by LVS, but at least one GL simulation should be
run to confirm that the logic function remains the same as before.
* Corrects four signals which were missing from the caravan top level
(management output and output enable to GPIO 0 and 1---these errors
would have prevented the houskeeping SPI from working on caravel).
Corrected RTL verilog (source of the error), GL verilog, and layout.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* (1) Modified the .magicrc file to set a default for PDK if not set in the
environment. (2) Fixed the user ID programming layout to not leave holes
behind when the script moves the vias around (similar to the handling of
the GPIO defaults block). (3) Added substrate isolation to gpio_control_block
and fixed the path references to the standard cells. (4) Fixed the four
missing routes on the Caravan top level. (5) Reinstated the large rendered
labels for the pads on both caravel and caravan. (6) Corrected the top
level gate-level netlist for caravan to add the missing pins to the
management core wrapper. (7) Did the same for the caravan top level RTL.
(8) Created scripts to run full LVS including extracting the management
core wrapper and reading all gate-level verilog submodules. (9) Moved all
of the LVS scripts to the scripts directory.
* Apply automatic changes to Manifest and README.rst
* Made the changes from pull request #73 as they did not get merged
successfully, and if merged now they will generate conflicts with
this pull request in scripts/set_user_id.py. So it's easier to
just manually add them to this pull request.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* - update caravan configuration
* change correct gpio_default blocks instance names
* implement powerrouting work around
* place spare logic blocks
* keep the history of runs and sym link last/final one
* - update caravan mag, def and gl views
- add fake power routing cell in the rtl as a placeholder for openlane
to prevent routing on that cell
- fix some syntax errors in chip_io_alt
- match simple_por lef pins with mag by regenerating it
* Apply automatic changes to Manifest and README.rst
* add caravan power routing lef
* - update mag and def view of caravan
- add_macro_placement for fake cell
* Added back the power routing to Caravan, fixed DRC errors, ran LVS,
corrected placement of isolated substrate regions, and replaced the
signal routing for the analog lines. Be aware that merging with
main may cause issues with the mgmt_protect.mag file and its
subcells mprj2_logic_high.mag and mprj_logic_high.mag. It may be
worth cherry-picking the files to merge and exclude those layouts.
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
* Fix syntax error in gpio_control_block
Fixed syntax error that was only visible when running iverilog for simulation
* Apply automatic changes to Manifest and README.rst
Co-authored-by: marwaneltoukhy <marwaneltoukhy@users.noreply.github.com>
* REVERT ME: temporarily match simple_por pin in verilog with lef
* - update configs
- add patch file for power routing def
* - update the following caravel toplevel views
- gl
- mag
- def
- add caravel power routing def
* Apply automatic changes to Manifest and README.rst
* update gl mag and def for caravel
* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"
This reverts commit b70c27c69f.
* update caravel gds
* Apply automatic changes to Manifest and README.rst
* Added text and logo cells back into the caravel top level. Put an
isolated ground marker layer on the xres_buf layout. Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v. Updated the copyright block text.
Corrected DRC errors in the top level routing.
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
* - add openlane patch file to for input buffering workaround
- update configuration of mgmt protect
* mgmt_protect updated
* mgmt_protect updated
* remove some via3 to fix power shorts
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
* Corrected the issue reported on the github issue tracker (#34)
in which the use of "clocking" as an instance name in caravel and
caravan conflicts with the system verilog keyword of the same
name.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
correctly no matter how the "gpio_defaults_block.mag" and
"gl/gpio_defaults_block.v" are defined. Previously it assumed
that they both defined all bits as zero, which was not the case
for the layout. Now both define bit value 0x0402 and the script
can flip bits either direction as needed in both verilog and
layout
it was configured for the caravel_pico SoC, with the housekeeping
SPI able to access the upper 256-word section of the memory if the
CSB bit in the housekeeping control register is cleared. This
testbench tests both access through housekeeping and access directly
from the SoC through the memory-mapped address.
architecture type passed to gcc as the value to the '-march='
option an environment variable, setting that environment variable
to "rv32imc" by default, and overriding it with "rv32ic" specifically
for the new caravel_pico without the multiplier and divider option,
on testbenches "mem" and "storage" which both have multiplies in the
C code.
caravel_pico repository. The issue is that each SoC implementation
defines its own modules and therefore needs its own includes. The
implication is that this file now needs to exist in every SoC
implementation's verilog/gl/ directory.
connections to the core side VCCD1 and VSSD1 on the clamped3 pads.
Also added scripts for running LVS on chip_io to the mag/ directory,
and revised the scripts so that they will only re-run extraction if
there is no netlist file in the mag/ directory.
gate-level simulations from running. Corrected caravan_netlists.v,
which did not have the same change made yesterday to caravel_netlists.v
for the DLL.
knowledge and which went undetected since before MPW-one. Modified
the "pll" and "sysctrl" testbenches so that they run and measure
something useful. Both exercise the clock monitoring on GPIO
outputs functions. The PLL test also runs the digital locked
loop (behavioral verilog). The PLL test overlaps sysctrl, but
"pll" cannot be run on gate level verilog, whereas "sysctrl" can.
M0stafaRady
R. Timothy Edwards
Mohamed Shalan
M0stafaRady
Marwan Abbas
kareem
Jeff DiCorpo
jeffdi
Kareem Farid
manarabdelaty