riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

fix bug at reading from debug registers

This commit is contained in:
M0stafaRady 2022-10-03 08:57:23 -07:00
parent e81416bb51
commit c4859c8789
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
verilog/rtl/debug_regs.v
View File

@ -34,7 +34,7 @@ module debug_regs (
debug_reg_2[31:24] <= (wbs_adr_i[2] && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_2[31:24];
wbs_ack_o <= 1;
end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o) begin // read
wbs_dat_o <= (wbs_adr_i[3]) ? debug_reg_2 : debug_reg_1;
wbs_dat_o <= (wbs_adr_i[2]) ? debug_reg_2 : debug_reg_1;
wbs_ack_o <= 1;
end else begin
wbs_ack_o <= 0;