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Corrected the gpio_control_block so that the user_gpio_out signal (#89) 

does not pass through an inverter, so that the input can remain
unconnected.  Rewired the existing implementation to use an
alternative gate that has an inverting input so that the
user_gpio_out signal can be left undriven when the GPIOs are in
the management enable state.  This is a simple logic refactoring
and does not change the logic function.  The manual rewiring has
been confirmed by LVS, but at least one GL simulation should be
run to confirm that the logic function remains the same as before.
This commit is contained in:
R. Timothy Edwards 2022-04-25 14:27:41 -04:00 committed by GitHub
parent ad8d168555
commit b2089fe9eb
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2 changed files with 470 additions and 431 deletions
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893
mag/gpio_control_block.mag
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File diff suppressed because it is too large Load Diff

8
verilog/gl/gpio_control_block.v
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@ -696,7 +696,7 @@ module gpio_control_block (mgmt_gpio_in,
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(vssd),
sky130_fd_sc_hd__fill_1 PHY_21 (.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
.VPWR(vccd));
@ -877,7 +877,7 @@ module gpio_control_block (mgmt_gpio_in,
.VPB(vccd),
.VPWR(vccd),
.X(pad_gpio_outenb));
sky130_fd_sc_hd__inv_2 _100_ (.A(user_gpio_out),
sky130_fd_sc_hd__inv_2 _100_ (.A(mgmt_ena),
.VGND(vssd),
.VNB(vssd),
.VPB(vccd),
@ -913,8 +913,8 @@ module gpio_control_block (mgmt_gpio_in,
.VPB(vccd),
.VPWR(vccd),
.Y(_073_));
sky130_fd_sc_hd__o22ai_2 _105_ (.A1(mgmt_ena),
.A2(_069_),
sky130_fd_sc_hd__o2bb2ai_2 _105_ (.A1_N(user_gpio_out),
.A2_N(_069_),
.B1(_072_),
.B2(_073_),
.VGND(vssd),