mirror of https://github.com/efabless/caravel.git
Fix housekeeping spi tests
This commit is contained in:
M0stafaRady
parent
1c48f527b8
commit
cb929cb329
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@ -315,16 +315,16 @@ class Caravel_env:
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data_bits = []
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is_list = isinstance(bits, (list,tuple))
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if is_list :
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cocotb.log.info(f'[caravel] [drive_gpio_in] start bits[1] = {bits[1]} bits[0]= {bits[0]}')
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cocotb.log.debug(f'[caravel] [drive_gpio_in] start bits[1] = {bits[1]} bits[0]= {bits[0]}')
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data_bits = BinaryValue(value = data, n_bits =bits[0]-bits[1]+1 ,bigEndian=(bits[0]<bits[1]))
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for i,bits2 in enumerate(range(bits[1],bits[0]+1)):
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self.dut._id(f"bin{bits2}",False).value = data_bits[i]
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self.dut._id(f"bin{bits2}_en",False).value = 1
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cocotb.log.info(f'[caravel] [drive_gpio_in] drive bin{bits2} with {data_bits[i]} and bin{bits2}_en with 1')
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cocotb.log.debug(f'[caravel] [drive_gpio_in] drive bin{bits2} with {data_bits[i]} and bin{bits2}_en with 1')
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else:
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self.dut._id(f'bin{bits}',False).value = data
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self.dut._id(f'bin{bits}_en',False).value = 1
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cocotb.log.info(f'[caravel] [drive_gpio_in] drive bin{bits} with {data} and bin{bits}_en with 1')
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cocotb.log.debug(f'[caravel] [drive_gpio_in] drive bin{bits} with {data} and bin{bits}_en with 1')
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"""drive the value of gpio management"""
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def drive_mgmt_gpio(self,data):
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@ -18,7 +18,7 @@ reg = Regs()
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@cocotb.test()
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@repot_test
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async def hk_regs_wr_wb(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=237,num_error=INFINITY)
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caravelEnv,clock = await test_configure(dut,timeout_cycles=700,num_error=INFINITY)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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with open('wb_models/housekeepingWB/HK_regs.json') as f:
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@ -58,12 +58,13 @@ async def hk_regs_wr_wb(dut):
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break
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if not bit_exist:
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data_exp += '0'
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await ClockCycles(caravelEnv.clk,10)
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cocotb.log.info(f"[TEST] expected data calculated = {data_exp}")
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data_out = await cpu.read_address(address)
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cocotb.log.info(f"[TEST] Read {bin(data_out)} from {regs[mem][key][0][0]} address {hex(address)} through wishbone")
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if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong read from {regs[mem][key][0][0]} address {hex(address)} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}")
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else: cocotb.log.debug(f"[TEST] read the right value {hex(data_out)} from {regs[mem][key][0][0]} address {address} ")
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else: cocotb.log.info(f"[TEST] read the right value {hex(data_out)} from {regs[mem][key][0][0]} address {hex(address)} ")
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'''randomly write then read housekeeping regs through SPI'''
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@cocotb.test()
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@ -81,12 +82,16 @@ async def hk_regs_wr_spi(dut):
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if key == 'base_addr':
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continue
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address = regs[mem][key][0][7]
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if address in [111,36]: # 111 is for Housekeeping SPI disable, writing 1 to this address will disable the SPI and 36 is for mprj_io[03] changing bit 3 of this register would disable the spi by deassert spi_is_enabled
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continue
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# address = int(key,16)
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if address in [0x69,0x6A,0x6B,0x6C]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
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continue
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data_in = random.getrandbits(bits_num)
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cocotb.log.info(f"[TEST] Writing {bin(data_in)} to reg [{regs[mem][key][0][0]}] address {hex(address)} through SPI")
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await write_reg_spi(caravelEnv,address=address,data=data_in)
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#calculate the expected value for each bit
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is_unknown = False
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data_exp = ''
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for i in range(bits_num):
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bit_exist = False
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@ -103,14 +108,22 @@ async def hk_regs_wr_spi(dut):
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break
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else : # read only get the value from reset
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data_exp += bin(reset_val)[2:].zfill(bits_num)[i]
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bit_exist = True
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break
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if field_access == "NA": # that mean the value is unknown as the register value can change by hardware mostly the reg value is input to the housekeeping from other blocks
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is_unknown = True
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break
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if not bit_exist:
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data_exp += '0'
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if is_unknown:# that mean the value is unknown as the register value can change by hardware mostly the reg value is input to the housekeeping from other blocks
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continue
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await ClockCycles(caravelEnv.clk,10)
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cocotb.log.info(f"[TEST] expected data calculated = {data_exp}")
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data_out = await read_reg_spi(caravelEnv,address=address)
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cocotb.log.info(f"[TEST] Read {bin(data_out)} from [{regs[mem][key][0][0]}] address {hex(address)} through SPI")
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if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong read from [{regs[mem][key][0][0]}] address {hex(address)} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}")
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else: cocotb.log.debug(f"[TEST] read the right value {hex(data_out)} from [{regs[mem][key][0][0]}] address {address} ")
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else: cocotb.log.info(f"[TEST] read the right value {hex(data_out)} from [{regs[mem][key][0][0]}] address {address} ")
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'''check reset value of house keeping register'''
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@cocotb.test()
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@ -16,14 +16,14 @@
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"0x10": [["PLL bypass","pll_bypass",0,1,"RW",1,1,9]],
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"0x14": [["CPU IRQ","irq_spi",0,1,"RW",0,0,10]],
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"0x18": [["CPU reset","reset_reg",0,1,"RW",0,0,11]],
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"0x28": [["CPU trap","trap",0,1,"RW",0,0,12]],
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"0x28": [["CPU trap","trap",0,1,"NA",0,0,12]],
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"0x1c": [["DCO trim",["pll_trim",7,0],0,8,"RW",255,255,13]],
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"0x1d": [["DCO trim",["pll_trim",15,8],0,8,"RW",239,239,14]],
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"0x1e": [["DCO trim",["pll_trim",23,16],0,8,"RW",255,255,15]],
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"0x1f": [["DCO trim",["pll_trim",25,24],0,2,"RW",3,3,16]],
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"0x20": [["PLL output divider","pll_sel",0,3,"RW",2,2,17],["PLL output divider 2","pll90_sel",3,3,"RW",2,2,17]],
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"0x24": [["PLL feedback divider","pll_div",0,5,"RW",4,4,18]],
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"0x34": [["SRAM read-only control","sram_ro_csb",0,1,"RW",1,1,20],["SRAM read-only control","sram_ro_clk",0,1,"RW",0,0,20]],
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"0x34": [["SRAM read-only control","sram_ro_csb",0,1,"RW",1,1,20],["SRAM read-only control","sram_ro_clk",1,1,"RW",0,0,20]],
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"0x30": [["SRAM read-only address","sram_ro_addr",0,8,"RW",0,0,21]]
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},
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@ -117,7 +117,7 @@
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},
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"sys":{ "base_addr": ["SYS_BASE_ADR",639631360],
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"0x00": [["user2 vdd good","usr2_vdd_pwrgood",0,1,"RO",0,0,26],["user1 vdd good","usr1_vdd_pwrgood",1,1,"RO",0,0,26],
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"0x00": [["user2 vdd good","usr2_vdd_pwrgood",0,1,"NA",0,0,26],["user1 vdd good","usr1_vdd_pwrgood",1,1,"NA",0,0,26],
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["user2 vcc good","usr2_vcc_pwrgood",2,1,"RO",0,0,26],["user1 vcc good","usr1_vcc_pwrgood",3,1,"RO",0,0,26]],
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"0x04": [["Trap output redirect","trap_output_dest",0,1,"RW",0,0,27],
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["clock2 output redirect","clk2_output_dest",1,1,"RW",0,0,27],
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