diff --git a/verilog/dv/cocotb/caravel.py b/verilog/dv/cocotb/caravel.py
index 8c4f36a4..1a63847d 100644
--- a/verilog/dv/cocotb/caravel.py
+++ b/verilog/dv/cocotb/caravel.py
@@ -315,16 +315,16 @@ class Caravel_env:
         data_bits = []
         is_list  = isinstance(bits, (list,tuple)) 
         if is_list : 
-            cocotb.log.info(f'[caravel] [drive_gpio_in] start bits[1] = {bits[1]} bits[0]= {bits[0]}')
+            cocotb.log.debug(f'[caravel] [drive_gpio_in] start bits[1] = {bits[1]} bits[0]= {bits[0]}')
             data_bits = BinaryValue(value = data, n_bits =bits[0]-bits[1]+1 ,bigEndian=(bits[0]<bits[1]))
             for i,bits2 in enumerate(range(bits[1],bits[0]+1)):
                 self.dut._id(f"bin{bits2}",False).value = data_bits[i]
                 self.dut._id(f"bin{bits2}_en",False).value = 1
-                cocotb.log.info(f'[caravel] [drive_gpio_in] drive bin{bits2} with {data_bits[i]} and bin{bits2}_en with 1')
+                cocotb.log.debug(f'[caravel] [drive_gpio_in] drive bin{bits2} with {data_bits[i]} and bin{bits2}_en with 1')
         else:
             self.dut._id(f'bin{bits}',False).value = data
             self.dut._id(f'bin{bits}_en',False).value = 1
-            cocotb.log.info(f'[caravel] [drive_gpio_in] drive bin{bits} with {data} and bin{bits}_en with 1')
+            cocotb.log.debug(f'[caravel] [drive_gpio_in] drive bin{bits} with {data} and bin{bits}_en with 1')
 
     """drive the value of  gpio management"""
     def drive_mgmt_gpio(self,data):
diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py
index 6d3fc77c..1c2f80fb 100644
--- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py
+++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py
@@ -18,7 +18,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def hk_regs_wr_wb(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=237,num_error=INFINITY)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=700,num_error=INFINITY)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     with open('wb_models/housekeepingWB/HK_regs.json') as f:
@@ -58,12 +58,13 @@ async def hk_regs_wr_wb(dut):
                                 break
                 if not bit_exist:
                     data_exp += '0'
+        await ClockCycles(caravelEnv.clk,10) 
 
         cocotb.log.info(f"[TEST] expected data calculated = {data_exp}")    
         data_out = await cpu.read_address(address) 
         cocotb.log.info(f"[TEST] Read {bin(data_out)} from {regs[mem][key][0][0]} address {hex(address)} through wishbone")
         if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong read from {regs[mem][key][0][0]} address {hex(address)} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}")
-        else:                           cocotb.log.debug(f"[TEST] read the right value {hex(data_out)}  from {regs[mem][key][0][0]} address {address} ")
+        else:                           cocotb.log.info(f"[TEST] read the right value {hex(data_out)}  from {regs[mem][key][0][0]} address {hex(address)} ")
 
 '''randomly write then read housekeeping regs through SPI'''
 @cocotb.test()
@@ -81,12 +82,16 @@ async def hk_regs_wr_spi(dut):
         if key == 'base_addr':
             continue
         address = regs[mem][key][0][7]
+        if address in [111,36]: # 111 is for Housekeeping SPI disable, writing 1 to this address will disable the SPI and 36 is for mprj_io[03] changing bit 3 of this register would disable the spi by deassert spi_is_enabled
+            continue
+        # address = int(key,16)
         if  address in [0x69,0x6A,0x6B,0x6C]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
             continue
         data_in = random.getrandbits(bits_num)
         cocotb.log.info(f"[TEST] Writing {bin(data_in)} to reg [{regs[mem][key][0][0]}] address {hex(address)} through SPI")
         await write_reg_spi(caravelEnv,address=address,data=data_in)
         #calculate the expected value for each bit
+        is_unknown = False
         data_exp = ''
         for i in range(bits_num): 
             bit_exist = False
@@ -103,14 +108,22 @@ async def hk_regs_wr_spi(dut):
                         break
                     else : # read only get the value from reset 
                         data_exp += bin(reset_val)[2:].zfill(bits_num)[i]
+                        bit_exist = True
+                        break
+                if field_access == "NA": # that mean the value is unknown as the register value can change by hardware mostly the reg value is input to the housekeeping from other blocks 
+                    is_unknown = True
+                    break
             if not bit_exist:
                 data_exp += '0'
+        if is_unknown:# that mean the value is unknown as the register value can change by hardware mostly the reg value is input to the housekeeping from other blocks 
+            continue
 
+        await ClockCycles(caravelEnv.clk,10) 
         cocotb.log.info(f"[TEST] expected data calculated = {data_exp}")    
         data_out = await read_reg_spi(caravelEnv,address=address) 
         cocotb.log.info(f"[TEST] Read {bin(data_out)} from [{regs[mem][key][0][0]}] address {hex(address)} through SPI")
         if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong read from [{regs[mem][key][0][0]}] address {hex(address)} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}")
-        else:                           cocotb.log.debug(f"[TEST] read the right value {hex(data_out)}  from [{regs[mem][key][0][0]}] address {address} ")
+        else:                           cocotb.log.info(f"[TEST] read the right value {hex(data_out)}  from [{regs[mem][key][0][0]}] address {address} ")
 
 '''check reset value of house keeping register'''
 @cocotb.test()
diff --git a/verilog/dv/cocotb/wb_models/housekeepingWB/HK_regs.json b/verilog/dv/cocotb/wb_models/housekeepingWB/HK_regs.json
index d8b73813..97d26688 100644
--- a/verilog/dv/cocotb/wb_models/housekeepingWB/HK_regs.json
+++ b/verilog/dv/cocotb/wb_models/housekeepingWB/HK_regs.json
@@ -16,14 +16,14 @@
                 "0x10":            [["PLL bypass","pll_bypass",0,1,"RW",1,1,9]],
                 "0x14":            [["CPU IRQ","irq_spi",0,1,"RW",0,0,10]],
                 "0x18":            [["CPU reset","reset_reg",0,1,"RW",0,0,11]],
-                "0x28":            [["CPU trap","trap",0,1,"RW",0,0,12]],
+                "0x28":            [["CPU trap","trap",0,1,"NA",0,0,12]],
                 "0x1c":            [["DCO trim",["pll_trim",7,0],0,8,"RW",255,255,13]],
                 "0x1d":            [["DCO trim",["pll_trim",15,8],0,8,"RW",239,239,14]],
                 "0x1e":            [["DCO trim",["pll_trim",23,16],0,8,"RW",255,255,15]],
                 "0x1f":            [["DCO trim",["pll_trim",25,24],0,2,"RW",3,3,16]],
                 "0x20":            [["PLL output divider","pll_sel",0,3,"RW",2,2,17],["PLL output divider 2","pll90_sel",3,3,"RW",2,2,17]],
                 "0x24":            [["PLL feedback divider","pll_div",0,5,"RW",4,4,18]],
-                "0x34":            [["SRAM read-only control","sram_ro_csb",0,1,"RW",1,1,20],["SRAM read-only control","sram_ro_clk",0,1,"RW",0,0,20]],
+                "0x34":            [["SRAM read-only control","sram_ro_csb",0,1,"RW",1,1,20],["SRAM read-only control","sram_ro_clk",1,1,"RW",0,0,20]],
                 "0x30":            [["SRAM read-only address","sram_ro_addr",0,8,"RW",0,0,21]]
             },
 
@@ -117,7 +117,7 @@
             },
             
     "sys":{     "base_addr":       ["SYS_BASE_ADR",639631360],
-                "0x00":            [["user2 vdd good","usr2_vdd_pwrgood",0,1,"RO",0,0,26],["user1 vdd good","usr1_vdd_pwrgood",1,1,"RO",0,0,26],
+                "0x00":            [["user2 vdd good","usr2_vdd_pwrgood",0,1,"NA",0,0,26],["user1 vdd good","usr1_vdd_pwrgood",1,1,"NA",0,0,26],
                                     ["user2 vcc good","usr2_vcc_pwrgood",2,1,"RO",0,0,26],["user1 vcc good","usr1_vcc_pwrgood",3,1,"RO",0,0,26]],
                 "0x04":            [["Trap output redirect","trap_output_dest",0,1,"RW",0,0,27],
                                     ["clock2 output redirect","clk2_output_dest",1,1,"RW",0,0,27],