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merge with caravel_redesign

This commit is contained in:
M0stafaRady 2022-10-04 10:57:56 -07:00
parent 2f71281af0 599ee23610
commit 4b762da8e6
7 changed files with 1024 additions and 10372 deletions
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11083
docs/source/_static/die_pads.svg
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2
docs/source/memory-mapped-io-summary.rst
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@ -112,7 +112,7 @@ Memory Mapped I/O summary
- Trap output destination (:ref:`reg_trap_out_dest`)
* - `0x 2f 00 00 08`
- IRQ 7 input source (:ref:`reg_irq7_source`)
* - `0x 30 00 00 0`
* - `0x 30 00 00 00`
- User area base.
A user project may define additional Wishbone responder modules starting at this address.
* - `0x 80 00 00 00`

2
mag/caravan.mag
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@ -59098,7 +59098,7 @@ use gpio_defaults_block_0403 gpio_defaults_block_13
timestamp 1638587925
transform -1 0 709467 0 1 897800
box -38 0 6018 2224
use gpio_defaults_block_0403 gpio_defaults_block_14
use gpio_defaults_block_0403 gpio_defaults_block_25
timestamp 1638587925
transform 1 0 8367 0 1 818400
box -38 0 6018 2224

6
manifest
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@ -1,8 +1,8 @@
535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
d1c5814b58ece3ee2cccdf95dd332529f653fc2e verilog/rtl/__user_project_wrapper.v
6576abded424d948d2a7e71c2b4a4df1eda77238 verilog/rtl/caravan.v
b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v
0e2cda74281c33da2f4e23d0ff5af91adcbcf32a verilog/rtl/caravan.v
a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
cb320bf7e981979c4e823270d823395ea609c77e verilog/rtl/caravel.v
@ -19,7 +19,7 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
9ef209f70c9e73eac04890458a5c49b39347376e verilog/rtl/housekeeping.v
3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
0f3db7cf4d68971ba4e286c8706b20c9252d1f98 verilog/rtl/mgmt_protect.v
9cb20aace3daaae58f74b4a280053e7d1ed6b8e3 verilog/rtl/mgmt_protect.v
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
9dd11188f3a6980537dd51d8dd1a827795ac70fc verilog/rtl/mprj_io.v

2
verilog/gl/caravan.v
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@ -3832,7 +3832,7 @@ module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169] })
);
gpio_defaults_block_0403 gpio_defaults_block_14 (
gpio_defaults_block_0403 gpio_defaults_block_25 (
.VGND(vssd_core),
.VPWR(vccd_core),
.gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182] })

4
verilog/rtl/caravan.v
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@ -931,8 +931,8 @@ module caravan (
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_14_INIT)
) gpio_defaults_block_14 (
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_25_INIT)
) gpio_defaults_block_25 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),

297
verilog/rtl/mgmt_protect.v
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@ -28,6 +28,14 @@
/* For the sake of placement/routing, one conb (logic 1) cell is used */
/* for every buffer. */
/*----------------------------------------------------------------------*/
/* 10/3/2022: Removed tri-state buffers in favor of AND gates; i.e., */
/* if the user project is powered down, then the outputs are grounded */
/* rather than tristated. Other explicitly-referenced gates removed */
/* with the assumption that all outputs will be buffered as needed by */
/* the synthesis tools. Therefore the only restrictions needed on the */
/* synthesis tools is the list of input signals that must not be */
/* buffered because they are allowed to be floating. */
/*----------------------------------------------------------------------*/
module mgmt_protect (
`ifdef USE_POWER_PINS
@ -154,17 +162,7 @@ module mgmt_protect (
// data input to the management core to be a solid logic 0 when
// the user project is powered down.
sky130_fd_sc_hd__and2_1 user_to_mprj_in_ena_buf [127:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.X(la_data_in_enable),
.A(la_iena_mprj),
.B(mprj_logic1[457:330])
);
assign la_data_in_enable = la_iena_mprj & mprj_logic1[457:330];
sky130_fd_sc_hd__nand2_4 user_to_mprj_in_gates [127:0] (
`ifdef USE_POWER_PINS
@ -174,34 +172,15 @@ module mgmt_protect (
.VNB(vssd),
`endif
.Y(la_data_in_mprj_bar),
.A(la_data_out_core),
.A(la_data_out_core), // may be floating
.B(la_data_in_enable)
);
sky130_fd_sc_hd__inv_8 user_to_mprj_in_buffers [127:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Y(la_data_in_mprj),
.A(la_data_in_mprj_bar)
);
assign la_data_in_mprj = ~la_data_in_mprj_bar;
// Protection, similar to the above, for the three user IRQ lines
sky130_fd_sc_hd__and2_1 user_irq_ena_buf [2:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.X(user_irq_enable),
.A(user_irq_ena),
.B(mprj_logic1[460:458])
);
assign user_irq_enable = user_irq_ena & mrpj_logic1[460:458];
sky130_fd_sc_hd__nand2_4 user_irq_gates [2:0] (
`ifdef USE_POWER_PINS
@ -211,35 +190,16 @@ module mgmt_protect (
.VNB(vssd),
`endif
.Y(user_irq_bar),
.A(user_irq_core),
.A(user_irq_core), // may be floating
.B(user_irq_enable)
);
sky130_fd_sc_hd__inv_8 user_irq_buffers [2:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Y(user_irq),
.A(user_irq_bar)
);
assign user_irq = ~user_irq_bar;
// Protection, similar to the above, for the return
// signals from user area to managment on the wishbone bus
sky130_fd_sc_hd__and2_1 user_to_mprj_wb_ena_buf (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.X(wb_in_enable),
.A(mprj_iena_wb),
.B(mprj_logic1[462])
);
assign wb_in_enable = mprj_iena_wb & mprj_logic1[462];
sky130_fd_sc_hd__nand2_4 user_wb_dat_gates [31:0] (
`ifdef USE_POWER_PINS
@ -249,20 +209,11 @@ module mgmt_protect (
.VNB(vssd),
`endif
.Y(mprj_dat_i_core_bar),
.A(mprj_dat_i_user),
.A(mprj_dat_i_user), // may be floating
.B(wb_in_enable)
);
sky130_fd_sc_hd__inv_8 user_wb_dat_buffers [31:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Y(mprj_dat_i_core),
.A(mprj_dat_i_core_bar)
);
assign mprj_dat_i_core = ~mprj_dat_i_core_bar;
sky130_fd_sc_hd__nand2_4 user_wb_ack_gate (
`ifdef USE_POWER_PINS
@ -272,223 +223,45 @@ module mgmt_protect (
.VNB(vssd),
`endif
.Y(mprj_ack_i_core_bar),
.A(mprj_ack_i_user),
.A(mprj_ack_i_user), // may be floating
.B(wb_in_enable)
);
sky130_fd_sc_hd__inv_8 user_wb_ack_buffer (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Y(mprj_ack_i_core),
.A(mprj_ack_i_core_bar)
);
assign mprj_ack_i_core = ~mprj_ack_i_core_bar;
// The remaining circuitry guards against the management
// SoC dumping current into the user project area when
// the user project area is powered down.
sky130_fd_sc_hd__einvp_8 mprj_rstn_buf (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Z(user_reset),
.A(caravel_rstn),
.TE(mprj_logic1[0])
);
sky130_fd_sc_hd__einvp_8 mprj_clk_buf (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Z(user_clock),
.A(~caravel_clk),
.TE(mprj_logic1[1])
);
sky130_fd_sc_hd__einvp_8 mprj_clk2_buf (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Z(user_clock2),
.A(~caravel_clk2),
.TE(mprj_logic1[2])
);
sky130_fd_sc_hd__einvp_8 mprj_cyc_buf (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Z(mprj_cyc_o_user),
.A(~mprj_cyc_o_core),
.TE(mprj_logic1[3])
);
sky130_fd_sc_hd__einvp_8 mprj_stb_buf (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Z(mprj_stb_o_user),
.A(~mprj_stb_o_core),
.TE(mprj_logic1[4])
);
sky130_fd_sc_hd__einvp_8 mprj_we_buf (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Z(mprj_we_o_user),
.A(~mprj_we_o_core),
.TE(mprj_logic1[5])
);
sky130_fd_sc_hd__einvp_8 mprj_sel_buf [3:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Z(mprj_sel_o_user),
.A(~mprj_sel_o_core),
.TE(mprj_logic1[9:6])
);
sky130_fd_sc_hd__einvp_8 mprj_adr_buf [31:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Z(mprj_adr_o_user),
.A(~mprj_adr_o_core),
.TE(mprj_logic1[41:10])
);
sky130_fd_sc_hd__einvp_8 mprj_dat_buf [31:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Z(mprj_dat_o_user),
.A(~mprj_dat_o_core),
.TE(mprj_logic1[73:42])
);
/* Create signal to tristate the outputs to the user project */
sky130_fd_sc_hd__and2b_1 la_buf_enable [127:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.X(la_data_out_enable),
.A_N(la_oenb_mprj),
.B(mprj_logic1[201:74])
);
assign user_reset = (~caravel_rstn) & mprj_logic1[0]);
assign user_clock = caravel_clk & mprj_logic1[1];
assign user_clock2 = caravel_clk2 & mprj_logic1[2];
assign mprj_cyc_o_user = mprj_cyc_o_core & mprj_logic1[3];
assign mprj_stb_o_user = mprj_stb_o_core & mprj_logic1[4];
assign mprj_we_o_user = mprj_we_o_core & mprj_logic1[5];
assign mprj_sel_o_user = mprj_sel_o_core & mprj_logic1[9:6];
assign mprj_adr_o_user = mprj_adr_o_core & mprj_logic1[41:10];
assign mprj_dat_o_user = mprj_dat_o_core & mprj_logic1[73:42];
/* Project data out from the managment side to the user project */
/* area when the user project is powered down. */
sky130_fd_sc_hd__einvp_8 la_buf [127:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Z(la_data_in_core),
.A(~la_data_out_mprj),
.TE(la_data_out_enable)
);
assign la_data_out_enable = (~la_oenb_mprj) & mprj_logic1[201:74];
assign la_data_in_core = la_data_out_mprj & la_data_out_enable;
/* Project data out enable (bar) from the managment side to the */
/* user project area when the user project is powered down. */
sky130_fd_sc_hd__einvp_8 user_to_mprj_oen_buffers [127:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Z(la_oenb_core),
.A(~la_oenb_mprj),
.TE(mprj_logic1[329:202])
);
assign la_oenb_core = la_oenb_mprj & mprj_logic1[329:202]);
/* The conb cell output is a resistive connection directly to */
/* the power supply, so when returning the user1_powergood */
/* signal, make sure that it is buffered properly. */
sky130_fd_sc_hd__buf_8 mprj_pwrgood (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.A(mprj_logic1[461]),
.X(user1_vcc_powergood)
);
assign user1_vcc_powergood = mprj_logic1[461];
assign user2_vcc_powergood = mprj2_logic1;
assign user1_vdd_powergood = mprj_vdd_logic1;
assign user2_vdd_powergood = mprj2_vdd_logic1;
sky130_fd_sc_hd__buf_8 mprj2_pwrgood (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.A(mprj2_logic1),
.X(user2_vcc_powergood)
);
sky130_fd_sc_hd__buf_8 mprj_vdd_pwrgood (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.A(mprj_vdd_logic1),
.X(user1_vdd_powergood)
);
sky130_fd_sc_hd__buf_8 mprj2_vdd_pwrgood (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.A(mprj2_vdd_logic1),
.X(user2_vdd_powergood)
);
endmodule
`default_nettype wire