mirror of https://github.com/efabless/caravel.git
Merge branch 'caravel_redesign' into cocotb
This commit is contained in:
M0stafaRady
commit
a741ec4525
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
|
@ -356,19 +356,19 @@ MACRO gpio_control_block
|
|||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 5.900 51.760 7.500 ;
|
||||
RECT 4.360 5.900 50.000 7.500 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 22.800 51.760 24.400 ;
|
||||
RECT 4.360 22.800 50.000 24.400 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 39.700 51.760 41.300 ;
|
||||
RECT 4.360 39.700 50.000 41.300 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 56.600 51.760 58.200 ;
|
||||
RECT 4.360 56.600 50.000 58.200 ;
|
||||
END
|
||||
END vccd
|
||||
PIN vccd1
|
||||
|
|
@ -384,15 +384,15 @@ MACRO gpio_control_block
|
|||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 11.140 51.760 12.740 ;
|
||||
RECT 4.360 11.140 50.000 12.740 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 28.040 51.760 29.640 ;
|
||||
RECT 4.360 28.040 50.000 29.640 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 44.940 51.760 46.540 ;
|
||||
RECT 4.360 44.940 50.000 46.540 ;
|
||||
END
|
||||
END vccd1
|
||||
PIN vssd
|
||||
|
|
@ -404,15 +404,15 @@ MACRO gpio_control_block
|
|||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 14.350 51.760 15.950 ;
|
||||
RECT 4.360 14.350 50.000 15.950 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 31.250 51.760 32.850 ;
|
||||
RECT 4.360 31.250 50.000 32.850 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 48.150 51.760 49.750 ;
|
||||
RECT 4.360 48.150 50.000 49.750 ;
|
||||
END
|
||||
END vssd
|
||||
PIN vssd1
|
||||
|
|
@ -424,15 +424,15 @@ MACRO gpio_control_block
|
|||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 19.590 51.760 21.190 ;
|
||||
RECT 4.360 19.590 50.000 21.190 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 36.490 51.760 38.090 ;
|
||||
RECT 4.360 36.490 50.000 38.090 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 53.390 51.760 54.990 ;
|
||||
RECT 4.360 53.390 50.000 54.990 ;
|
||||
END
|
||||
END vssd1
|
||||
PIN zero
|
||||
|
|
@ -718,68 +718,68 @@ MACRO gpio_control_block
|
|||
RECT 28.250 60.720 29.710 65.000 ;
|
||||
RECT 30.550 60.720 32.010 65.000 ;
|
||||
RECT 32.850 60.720 170.000 65.000 ;
|
||||
RECT 4.700 0.000 170.000 60.720 ;
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||||
RECT 4.690 0.000 170.000 60.720 ;
|
||||
LAYER met3 ;
|
||||
RECT 6.280 60.840 69.600 61.705 ;
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||||
RECT 6.280 60.200 70.000 60.840 ;
|
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RECT 6.280 58.800 69.600 60.200 ;
|
||||
RECT 6.280 58.160 70.000 58.800 ;
|
||||
RECT 6.280 56.760 69.600 58.160 ;
|
||||
RECT 6.280 56.120 70.000 56.760 ;
|
||||
RECT 6.280 54.720 69.600 56.120 ;
|
||||
RECT 6.280 54.080 70.000 54.720 ;
|
||||
RECT 6.280 52.680 69.600 54.080 ;
|
||||
RECT 6.280 52.040 70.000 52.680 ;
|
||||
RECT 6.280 50.640 69.600 52.040 ;
|
||||
RECT 6.280 50.000 70.000 50.640 ;
|
||||
RECT 6.280 48.600 69.600 50.000 ;
|
||||
RECT 6.280 47.960 70.000 48.600 ;
|
||||
RECT 6.280 46.560 69.600 47.960 ;
|
||||
RECT 6.280 45.920 70.000 46.560 ;
|
||||
RECT 6.280 44.520 69.600 45.920 ;
|
||||
RECT 6.280 43.880 70.000 44.520 ;
|
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RECT 6.280 42.480 69.600 43.880 ;
|
||||
RECT 6.280 41.840 70.000 42.480 ;
|
||||
RECT 6.280 40.440 69.600 41.840 ;
|
||||
RECT 6.280 39.800 70.000 40.440 ;
|
||||
RECT 6.280 38.400 69.600 39.800 ;
|
||||
RECT 6.280 37.760 70.000 38.400 ;
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||||
RECT 6.280 36.360 69.600 37.760 ;
|
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RECT 6.280 35.720 70.000 36.360 ;
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RECT 6.280 34.320 69.600 35.720 ;
|
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RECT 6.280 33.680 70.000 34.320 ;
|
||||
RECT 6.280 32.280 69.600 33.680 ;
|
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RECT 6.280 31.640 70.000 32.280 ;
|
||||
RECT 6.280 30.240 69.600 31.640 ;
|
||||
RECT 6.280 29.600 70.000 30.240 ;
|
||||
RECT 6.280 28.200 69.600 29.600 ;
|
||||
RECT 6.280 27.560 70.000 28.200 ;
|
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RECT 6.280 26.160 69.600 27.560 ;
|
||||
RECT 6.280 25.520 70.000 26.160 ;
|
||||
RECT 6.280 24.120 69.600 25.520 ;
|
||||
RECT 6.280 23.480 70.000 24.120 ;
|
||||
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|
||||
RECT 6.280 20.040 69.600 21.440 ;
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|
||||
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||||
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||||
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||||
RECT 6.280 15.320 70.000 15.960 ;
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||||
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||||
RECT 6.280 13.280 70.000 13.920 ;
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||||
RECT 6.280 11.880 69.600 13.280 ;
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||||
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RECT 6.280 9.840 69.600 11.240 ;
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
RECT 4.665 13.280 70.000 13.920 ;
|
||||
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|
||||
RECT 4.665 11.240 70.000 11.880 ;
|
||||
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||||
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|
||||
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|
||||
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|
||||
RECT 4.665 5.760 69.600 7.160 ;
|
||||
RECT 4.665 5.120 70.000 5.760 ;
|
||||
RECT 4.665 3.720 69.600 5.120 ;
|
||||
RECT 4.665 3.080 70.000 3.720 ;
|
||||
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|
||||
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|
||||
LAYER met4 ;
|
||||
RECT 6.280 60.480 170.000 65.000 ;
|
||||
RECT 6.280 2.080 12.400 60.480 ;
|
||||
|
|
@ -791,7 +791,21 @@ MACRO gpio_control_block
|
|||
RECT 44.800 2.080 170.000 60.480 ;
|
||||
RECT 6.280 0.000 170.000 2.080 ;
|
||||
LAYER met5 ;
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
RECT 51.600 4.300 170.000 9.100 ;
|
||||
RECT 50.000 0.000 170.000 4.300 ;
|
||||
END
|
||||
END gpio_control_block
|
||||
END LIBRARY
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1664286915
|
||||
timestamp 1664976471
|
||||
<< obsli1 >>
|
||||
rect 0 13000 853 13014
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||||
rect 0 0 33962 13000
|
||||
|
|
@ -35,7 +35,7 @@ rect 5190 12144 5482 13000
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rect 5650 12144 5942 13000
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||||
rect 6110 12144 6402 13000
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||||
rect 6570 12144 34000 13000
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||||
rect 940 0 34000 12144
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||||
rect 938 0 34000 12144
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||||
<< metal3 >>
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||||
rect 14000 12248 34000 12368
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||||
rect 14000 11840 34000 11960
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||||
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|
@ -68,66 +68,66 @@ rect 14000 1232 34000 1352
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rect 14000 824 34000 944
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||||
rect 14000 416 34000 536
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||||
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||||
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||||
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||||
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||||
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|
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||||
rect 1256 0 34000 416
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||||
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||||
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|
||||
rect 10000 5200 34000 5288
|
||||
rect 10320 3598 34000 5200
|
||||
rect 10000 3510 34000 3598
|
||||
rect 10320 1908 34000 3510
|
||||
rect 10000 1820 34000 1908
|
||||
rect 10320 860 34000 1820
|
||||
rect 10000 0 34000 860
|
||||
<< labels >>
|
||||
rlabel metal2 s 938 12200 994 13000 6 gpio_defaults[0]
|
||||
port 1 nsew signal input
|
||||
|
|
@ -250,39 +264,39 @@ rlabel metal4 s 2560 496 2880 12016 6 vccd
|
|||
port 43 nsew power bidirectional
|
||||
rlabel metal4 s 7560 496 7880 12016 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal5 s 872 1180 10352 1500 6 vccd
|
||||
rlabel metal5 s 872 1180 10000 1500 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal5 s 872 4560 10352 4880 6 vccd
|
||||
rlabel metal5 s 872 4560 10000 4880 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal5 s 872 7940 10352 8260 6 vccd
|
||||
rlabel metal5 s 872 7940 10000 8260 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal5 s 872 11320 10352 11640 6 vccd
|
||||
rlabel metal5 s 872 11320 10000 11640 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal4 s 3560 496 3880 12016 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal4 s 8560 496 8880 12016 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal5 s 872 2228 10352 2548 6 vccd1
|
||||
rlabel metal5 s 872 2228 10000 2548 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal5 s 872 5608 10352 5928 6 vccd1
|
||||
rlabel metal5 s 872 5608 10000 5928 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal5 s 872 8988 10352 9308 6 vccd1
|
||||
rlabel metal5 s 872 8988 10000 9308 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal4 s 5060 496 5380 12016 6 vssd
|
||||
port 45 nsew ground bidirectional
|
||||
rlabel metal5 s 872 2870 10352 3190 6 vssd
|
||||
rlabel metal5 s 872 2870 10000 3190 6 vssd
|
||||
port 45 nsew ground bidirectional
|
||||
rlabel metal5 s 872 6250 10352 6570 6 vssd
|
||||
rlabel metal5 s 872 6250 10000 6570 6 vssd
|
||||
port 45 nsew ground bidirectional
|
||||
rlabel metal5 s 872 9630 10352 9950 6 vssd
|
||||
rlabel metal5 s 872 9630 10000 9950 6 vssd
|
||||
port 45 nsew ground bidirectional
|
||||
rlabel metal4 s 6060 496 6380 12016 6 vssd1
|
||||
port 46 nsew ground bidirectional
|
||||
rlabel metal5 s 872 3918 10352 4238 6 vssd1
|
||||
rlabel metal5 s 872 3918 10000 4238 6 vssd1
|
||||
port 46 nsew ground bidirectional
|
||||
rlabel metal5 s 872 7298 10352 7618 6 vssd1
|
||||
rlabel metal5 s 872 7298 10000 7618 6 vssd1
|
||||
port 46 nsew ground bidirectional
|
||||
rlabel metal5 s 872 10678 10352 10998 6 vssd1
|
||||
rlabel metal5 s 872 10678 10000 10998 6 vssd1
|
||||
port 46 nsew ground bidirectional
|
||||
rlabel metal3 s 14000 416 34000 536 6 zero
|
||||
port 47 nsew signal output
|
||||
|
|
@ -290,8 +304,8 @@ port 47 nsew signal output
|
|||
string FIXED_BBOX 0 0 34000 13000
|
||||
string LEFclass BLOCK
|
||||
string LEFview TRUE
|
||||
string GDS_END 572784
|
||||
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_09_27_06_53/results/signoff/gpio_control_block.magic.gds
|
||||
string GDS_END 572912
|
||||
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_10_05_06_26/results/signoff/gpio_control_block.magic.gds
|
||||
string GDS_START 204218
|
||||
<< end >>
|
||||
|
||||
|
|
|
|||
2
manifest
2
manifest
|
|
@ -19,7 +19,7 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
|
|||
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
|
||||
9ef209f70c9e73eac04890458a5c49b39347376e verilog/rtl/housekeeping.v
|
||||
3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
|
||||
9cb20aace3daaae58f74b4a280053e7d1ed6b8e3 verilog/rtl/mgmt_protect.v
|
||||
ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v
|
||||
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
|
||||
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
|
||||
9dd11188f3a6980537dd51d8dd1a827795ac70fc verilog/rtl/mprj_io.v
|
||||
|
|
|
|||
|
|
@ -97,7 +97,7 @@ set ::env(GRT_OBS) "\
|
|||
li1 4.21500 57.40500 49.81500 64.93000,
|
||||
li1 16.83000 0 49.41000 5.24000,
|
||||
li1 49.000 0 169.81000 64.84500,
|
||||
met5 67 0 170 65,
|
||||
met5 50 0 170 65,
|
||||
met4 49 0 170 65,
|
||||
met2 120 0 170 65,
|
||||
met1 120 0 170 65"
|
||||
|
|
|
|||
|
|
@ -55,9 +55,9 @@ proc custom_run_placement {args} {
|
|||
}
|
||||
|
||||
variable SCRIPT_DIR [file dirname [file normalize [info script]]]
|
||||
prep -design $SCRIPT_DIR -tag $::env(OPENLANE_RUN_TAG) -overwrite -verbose 0
|
||||
prep -design $SCRIPT_DIR -tag $::env(TAG) -overwrite -verbose 0
|
||||
exec rm -rf $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
exec ln -sf $SCRIPT_DIR/runs/$::env(OPENLANE_RUN_TAG) $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
exec ln -sf $SCRIPT_DIR/runs/$::env(TAG) $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
run_synthesis
|
||||
|
||||
init_floorplan
|
||||
|
|
@ -69,7 +69,7 @@ tap_decap_or
|
|||
add_route_obs
|
||||
run_power_grid_generation
|
||||
|
||||
set dont_use_old ::env(DONT_USE_CELLS)
|
||||
set dont_use_old $::env(DONT_USE_CELLS)
|
||||
global_placement_or
|
||||
set ::env(DONT_USE_CELLS) "$::env(DONT_USE_CELLS) sky130_fd_sc_hd__buf_1"
|
||||
run_resizer_design
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Tue Sep 27 13:54:44 2022
|
||||
# Wed Oct 5 13:27:20 2022
|
||||
###############################################################################
|
||||
current_design gpio_control_block
|
||||
###############################################################################
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -180,7 +180,7 @@ module mgmt_protect (
|
|||
|
||||
// Protection, similar to the above, for the three user IRQ lines
|
||||
|
||||
assign user_irq_enable = user_irq_ena & mrpj_logic1[460:458];
|
||||
assign user_irq_enable = user_irq_ena & mprj_logic1[460:458];
|
||||
|
||||
sky130_fd_sc_hd__nand2_4 user_irq_gates [2:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
|
|
@ -233,7 +233,7 @@ module mgmt_protect (
|
|||
// SoC dumping current into the user project area when
|
||||
// the user project area is powered down.
|
||||
|
||||
assign user_reset = (~caravel_rstn) & mprj_logic1[0]);
|
||||
assign user_reset = (~caravel_rstn) & mprj_logic1[0];
|
||||
assign user_clock = caravel_clk & mprj_logic1[1];
|
||||
assign user_clock2 = caravel_clk2 & mprj_logic1[2];
|
||||
assign mprj_cyc_o_user = mprj_cyc_o_core & mprj_logic1[3];
|
||||
|
|
@ -252,7 +252,7 @@ module mgmt_protect (
|
|||
/* Project data out enable (bar) from the managment side to the */
|
||||
/* user project area when the user project is powered down. */
|
||||
|
||||
assign la_oenb_core = la_oenb_mprj & mprj_logic1[329:202]);
|
||||
assign la_oenb_core = la_oenb_mprj & mprj_logic1[329:202];
|
||||
|
||||
/* The conb cell output is a resistive connection directly to */
|
||||
/* the power supply, so when returning the user1_powergood */
|
||||
|
|
|
|||
Loading…
Reference in New Issue