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add clock to the output od configuration function

This commit is contained in:
M0stafaRady 2022-10-01 12:34:53 -07:00
parent d12fac2ad1
commit 53e868abdf
13 changed files with 21 additions and 137 deletions
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123
verilog/dv/cocotb/tests/bitbang/bitbang_tests.py
View File

@ -14,7 +14,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def bitbang_no_cpu_all_o(dut):
caravelEnv = await test_configure(dut,timeout_cycles=10206)
caravelEnv,clock = await test_configure(dut,timeout_cycles=10206)
cpu = RiskV(dut)
cpu.cpu_force_reset()
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
@ -128,7 +128,7 @@ async def bitbang_no_cpu_all_o(dut):
@cocotb.test()
@repot_test
async def bitbang_no_cpu_all_i(dut):
caravelEnv = await test_configure(dut,timeout_cycles=8005)
caravelEnv,clock = await test_configure(dut,timeout_cycles=8005)
cpu = RiskV(dut)
cpu.cpu_force_reset()
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
@ -238,7 +238,7 @@ async def bitbang_no_cpu_all_i(dut):
@cocotb.test()
@repot_test
async def io_ports(dut):
caravelEnv = await test_configure(dut)
caravelEnv,clock = await test_configure(dut)
cpu = RiskV(dut)
cpu.cpu_force_reset()
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
@ -256,120 +256,3 @@ async def io_ports(dut):
while True:
if await cpu.read_address(reg.get_addr('reg_mprj_xfer')) != 1 :
break
"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI."""
@cocotb.test()
@repot_test
async def bitbang_spi(dut):
caravelEnv = await test_configure(dut,timeout_cycles=18910)
# Apply data 0x1809 (management standard output) to first block of
# user 1 and user 2 (GPIO 0 and 37) bits 0, 1, 9, and 12 are "1" (data go in backwards)
cpu = RiskV(dut)
cpu.cpu_force_reset()
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
#Configure all as output except reg_mprj_io_3
await clear_registers(cpu)
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 18 and 19
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 17 and 20
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 16 and 21
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 15 and 22
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 14 and 23
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 13 and 24
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 12 and 25
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 11 and 26
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 10 and 27
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 9 and 28
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 8 and 29
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 7 and 30
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 6 and 31
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 5 and 32
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 4 and 33
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 3 and 34
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 2 and 35
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 1 and 36
await clock_in_end_output_spi(caravelEnv) # 0 and 37 and load
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
i= 0x20
for j in range(5):
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),i)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} int {caravelEnv.monitor_gpio((37,5)).integer} i = {i}')
if caravelEnv.monitor_gpio((37,5)).integer != i << 27:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,5))} instead of {bin(i << 27)}')
# for k in range(250):
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0)
if caravelEnv.monitor_gpio((37,5)).integer != 0:
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x20
await ClockCycles(caravelEnv.clk, 1)
i= 0x80000000
for j in range(32):
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3f)
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),i)
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)}')
if caravelEnv.monitor_gpio((31,5)).integer != i>>5 :
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,5))} instead of {i>>5}')
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} type {int(caravelEnv.monitor_gpio((37,5)))} i = {i}')
await ClockCycles(caravelEnv.clk, 1)
# await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
await ClockCycles(caravelEnv.clk, 1)
if caravelEnv.monitor_gpio((37,5)).integer != 0:
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x80000000
await ClockCycles(caravelEnv.clk, 1000)

3
verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py
View File

@ -8,13 +8,14 @@ from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from caravel import GPIO_MODE
from common import Macros
reg = Regs()
@cocotb.test()
@repot_test
async def bitbang_cpu_all_o(dut):
caravelEnv = await test_configure(dut,timeout_cycles=2075459)
caravelEnv,clock = await test_configure(dut,timeout_cycles=2075459)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

2
verilog/dv/cocotb/tests/cpu/cpu_stress.py
View File

@ -14,7 +14,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def cpu_stress(dut):
caravelEnv = await test_configure(dut,timeout_cycles=1492541)
caravelEnv,clock = await test_configure(dut,timeout_cycles=1492541)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

4
verilog/dv/cocotb/tests/gpio/gpio.py
View File

@ -14,7 +14,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def gpio_all_o(dut):
caravelEnv = await test_configure(dut,timeout_cycles=264012)
caravelEnv,clock = await test_configure(dut,timeout_cycles=264012)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -55,7 +55,7 @@ async def gpio_all_o(dut):
@cocotb.test()
@repot_test
async def gpio_all_i(dut):
caravelEnv = await test_configure(dut,timeout_cycles=45464)
caravelEnv,clock = await test_configure(dut,timeout_cycles=45464)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

2
verilog/dv/cocotb/tests/hello_world/helloWorld.py
View File

@ -5,7 +5,7 @@ from tests.common_functions.test_functions import *
@repot_test
async def helloWorld(dut):
caravelEnv = await test_configure(dut)
caravelEnv,clock = await test_configure(dut)
cocotb.log.info("[Test] Hello world")
caravelEnv.print_gpios_ctrl_val()
caravelEnv.print_gpios_HW_val()

6
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py
View File

@ -18,7 +18,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def hk_regs_wr_wb(dut):
caravelEnv = await test_configure(dut,timeout_cycles=237,num_error=INFINITY)
caravelEnv,clock = await test_configure(dut,timeout_cycles=237,num_error=INFINITY)
cpu = RiskV(dut)
cpu.cpu_force_reset()
with open('wb_models/housekeepingWB/HK_regs.json') as f:
@ -69,7 +69,7 @@ async def hk_regs_wr_wb(dut):
@cocotb.test()
@repot_test
async def hk_regs_wr_spi(dut):
caravelEnv = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
caravelEnv,clock = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
with open('wb_models/housekeepingWB/HK_regs.json') as f:
regs = json.load(f)
@ -116,7 +116,7 @@ async def hk_regs_wr_spi(dut):
@cocotb.test()
@repot_test
async def hk_regs_rst_spi(dut):
caravelEnv = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
caravelEnv,clock = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
with open('wb_models/housekeepingWB/HK_regs.json') as f:
regs = json.load(f)

2
verilog/dv/cocotb/tests/irq/IRQ_external.py
View File

@ -21,7 +21,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def IRQ_external(dut):
caravelEnv = await test_configure(dut,timeout_cycles=164360)
caravelEnv,clock = await test_configure(dut,timeout_cycles=164360)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

2
verilog/dv/cocotb/tests/irq/IRQ_timer.py
View File

@ -14,7 +14,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def IRQ_timer(dut):
caravelEnv = await test_configure(dut,timeout_cycles=166519)
caravelEnv,clock = await test_configure(dut,timeout_cycles=166519)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

2
verilog/dv/cocotb/tests/irq/IRQ_uart.py
View File

@ -21,7 +21,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def IRQ_uart(dut):
caravelEnv = await test_configure(dut,timeout_cycles=18613481)
caravelEnv,clock = await test_configure(dut,timeout_cycles=18613481)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

2
verilog/dv/cocotb/tests/mem/mem_stress.py
View File

@ -14,7 +14,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def mem_stress(dut):
caravelEnv = await test_configure(dut,timeout_cycles=18164004)
caravelEnv,clock = await test_configure(dut,timeout_cycles=18164004)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

4
verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py
View File

@ -14,7 +14,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def mgmt_gpio_out(dut):
caravelEnv = await test_configure(dut,timeout_cycles=99562)
caravelEnv,clock = await test_configure(dut,timeout_cycles=99562)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -61,7 +61,7 @@ async def mgmt_gpio_out(dut):
@cocotb.test()
@repot_test
async def mgmt_gpio_in(dut):
caravelEnv = await test_configure(dut,timeout_cycles=326525)
caravelEnv,clock = await test_configure(dut,timeout_cycles=326525)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

2
verilog/dv/cocotb/tests/temp_partial_test/partial.py
View File

@ -14,7 +14,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def temp_partial(dut):
caravelEnv = await test_configure(dut,timeout_cycles=70000)
caravelEnv,clock = await test_configure(dut,timeout_cycles=70000)
# Apply data 0x1809 (management standard output) to first block of
# user 1 and user 2 (GPIO 0 and 37) bits 0, 1, 9, and 12 are "1" (data go in backwards)
cpu = RiskV(dut)

4
verilog/dv/cocotb/tests/timer/timer.py
View File

@ -14,7 +14,7 @@ reg = Regs()
@cocotb.test()
@repot_test
async def timer0_oneshot(dut):
caravelEnv = await test_configure(dut,timeout_cycles=1114136)
caravelEnv,clock = await test_configure(dut,timeout_cycles=1114136)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -56,7 +56,7 @@ async def timer0_oneshot(dut):
@cocotb.test()
@repot_test
async def timer0_periodic(dut):
caravelEnv = await test_configure(dut,timeout_cycles=58257)
caravelEnv,clock = await test_configure(dut,timeout_cycles=58257)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()