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fix wrong cell name 

`sky130_fd_sc_hd__dlygate4sd2` is called `sky130_fd_sc_hd__dlygate4sd2_1`
This commit is contained in:
Kareem Farid 2022-03-22 17:02:36 +02:00 committed by GitHub
parent 880b499d18
commit 8e02ea79d8
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1 changed files with 2 additions and 2 deletions
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4
verilog/rtl/gpio_control_block.v
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@ -162,7 +162,7 @@ module gpio_control_block #(
/* add a final logic gate after that. The logic gate is */
/* synthesized and will be sized appropriately for an output buffer */
sky130_fd_sc_hd__dlygate4sd2 data_delay_1 (
sky130_fd_sc_hd__dlygate4sd2_1 data_delay_1 (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
@ -173,7 +173,7 @@ module gpio_control_block #(
.A(serial_data_pre),
);
sky130_fd_sc_hd__dlygate4sd2 data_delay_2 (
sky130_fd_sc_hd__dlygate4sd2_1 data_delay_2 (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),