From 8e02ea79d8e5c1413b51f83b59a9091248567982 Mon Sep 17 00:00:00 2001 From: Kareem Farid Date: Tue, 22 Mar 2022 17:02:36 +0200 Subject: [PATCH] fix wrong cell name `sky130_fd_sc_hd__dlygate4sd2` is called `sky130_fd_sc_hd__dlygate4sd2_1` --- verilog/rtl/gpio_control_block.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v index bb50b83a..6bc3fab5 100644 --- a/verilog/rtl/gpio_control_block.v +++ b/verilog/rtl/gpio_control_block.v @@ -162,7 +162,7 @@ module gpio_control_block #( /* add a final logic gate after that. The logic gate is */ /* synthesized and will be sized appropriately for an output buffer */ - sky130_fd_sc_hd__dlygate4sd2 data_delay_1 ( + sky130_fd_sc_hd__dlygate4sd2_1 data_delay_1 ( `ifdef USE_POWER_PINS .VPWR(vccd), .VGND(vssd), @@ -173,7 +173,7 @@ module gpio_control_block #( .A(serial_data_pre), ); - sky130_fd_sc_hd__dlygate4sd2 data_delay_2 ( + sky130_fd_sc_hd__dlygate4sd2_1 data_delay_2 ( `ifdef USE_POWER_PINS .VPWR(vccd), .VGND(vssd),