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update make file to take user_project_wrapper file as input for iverilog

This commit is contained in:
M0stafaRady 2022-10-02 06:48:29 -07:00
parent 927c216a6b
commit f0494ef4b1
1 changed files with 1 additions and 1 deletions
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2
verilog/dv/cocotb/Makefile
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@ -46,7 +46,7 @@ cocotb:
iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
-DTESTNAME=\"$(TestName)\" -DTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \
-f$(VERILOG_PATH)/includes/includes.rtl.caravel \
-o sim_build/sim.vvp caravel_top.sv
-o sim_build/sim.vvp $(CARAVEL_PATH)/rtl/__user_project_wrapper.v $(CARAVEL_PATH)/rtl/debug_regs.v caravel_top.sv
#GL
# iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
# -DTESTNAME=\"$(TestName)\" -DRUNTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \