From f0494ef4b130ddd02681fe6e337332763c21b787 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 2 Oct 2022 06:48:29 -0700 Subject: [PATCH] update make file to take user_project_wrapper file as input for iverilog --- verilog/dv/cocotb/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/dv/cocotb/Makefile b/verilog/dv/cocotb/Makefile index bc6a73be..5699749a 100644 --- a/verilog/dv/cocotb/Makefile +++ b/verilog/dv/cocotb/Makefile @@ -46,7 +46,7 @@ cocotb: iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ -DTESTNAME=\"$(TestName)\" -DTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ - -o sim_build/sim.vvp caravel_top.sv + -o sim_build/sim.vvp $(CARAVEL_PATH)/rtl/__user_project_wrapper.v $(CARAVEL_PATH)/rtl/debug_regs.v caravel_top.sv #GL # iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ # -DTESTNAME=\"$(TestName)\" -DRUNTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \