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Add spi master temp created to simulate the silicon validation test and to be removed after

This commit is contained in:
M0stafaRady 2022-10-04 10:46:34 -07:00
parent 11330823b7
commit 5e523bce5b
3 changed files with 174 additions and 0 deletions
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14
verilog/dv/cocotb/tests.json
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@ -187,5 +187,19 @@
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"using SPI master for reading from external memory"}
,"spi_master_temp" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"To be deleted"}
,"user_pass_thru_rd" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"use the housekeeping spi in user pass thru mode to read from external mem"}
}
}

49
verilog/dv/cocotb/tests/spi_master/spi_master.py
View File

@ -53,3 +53,52 @@ async def spi_master_rd(dut):
await ClockCycles(caravelEnv.clk,1000)
@cocotb.test()
@repot_test
async def spi_master_temp(dut):
""" the firmware is configured to always send clk to spi so I can't insert alot of logics reading values
the method of testing used can't work if 2 addresses Consecutive have the same address
"""
caravelEnv,clock = await test_configure(dut,timeout_cycles=214842)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info (f"[TEST] start spi_master_temp test")
await FallingEdge(dut.bin33_monitor)
await RisingEdge(dut.bin32_monitor)
a = ''
b = ''
# first value
for i in range(8):
a = a + dut.bin35_monitor.value.binstr
await RisingEdge(dut.bin32_monitor)
cocotb.log.info (f" [TEST] a = {a} = {int(a,2)}")
# second val
for i in range(8):
b = b + dut.bin35_monitor.value.binstr
await RisingEdge(dut.bin32_monitor)
cocotb.log.info (f" [TEST] b = {b} = {int(b,2)}")
s = int(a,2) + int(b,2)
s_bin = bin(s)[2:].zfill(8)
cocotb.log.info (f" [TEST] sending sum of {int(a,2)} + {int(b,2)} = {s} = {s_bin}")
for i in range(8):
dut.bin34_en.value = 1
dut.bin34.value = int(s_bin[i],2) # bin
cocotb.log.debug (f"[SPI_VIP] [SPI_op] SDO = {s_bin[i]} ")
await FallingEdge(dut.bin32_monitor)
dut.bin34_en.value = 0 # enable
while True:
if cpu.read_debug_reg1() == 0xBB:
cocotb.log.info(f" [TEST] firmware recieve the right value {s}")
break
elif cpu.read_debug_reg1() == 0xBB:
cocotb.log.error(f" [TEST] firmware recieve the incorrect value {cpu.read_debug_reg2()} instead of {s}")
break
await ClockCycles(caravelEnv.clk,10)

111
verilog/dv/cocotb/tests/spi_master/spi_master_temp.c Normal file
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@ -0,0 +1,111 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
#include <csr.h>
// --------------------------------------------------------
/*
* SPI master Test
* - Enables SPI master
* - Uses SPI master to talk to external SPI module
*/
void spi_write(char c)
{
reg_spimaster_wdata = (unsigned long) c;
// reg_spimaster_wdata = c;
// spi_master_control_length_write(8);
// spi_master_control_start_write(1);
// reg_spimaster_control = 0x0800;
reg_spimaster_control = 0x0801;
}
char spi_read()
{
// reg_spimaster_wdata = c;
// spi_master_control_length_write(8);
// spi_master_control_start_write(1);
// reg_spimaster_control = 0x0800;
// spi_write(0x00);
// reg_spimaster_rdata = 0x00;
// reg_spimaster_control = 0x0801;
spi_write(0x00);
while (reg_spimaster_status != 1);
return reg_spimaster_rdata;
}
void main()
{
int i;
uint32_t value;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
// For SPI operation, GPIO 1 should be an input, and GPIOs 2 to 4
// should be outputs.
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; // SDI
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; // SDO
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; // CSB
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; // SCK
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_2 =0xAA;
reg_spi_enable = 1;
// For SPI operation, GPIO 1 should be an input, and GPIOs 2 to 4
// should be outputs.
// Start test
// Enable SPI master
// SPI master configuration bits:
// bits 7-0: Clock prescaler value (default 2)
// bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first)
// bit 9: CSB sense (0 = inverted, 1 = noninverted)
// bit 10: SCK sense (0 = noninverted, 1 = inverted)
// bit 11: mode (0 = read/write opposite edges, 1 = same edges)
// bit 12: stream (1 = CSB ends transmission)
// bit 13: enable (1 = enabled)
// bit 14: IRQ enable (1 = enabled)
// bit 15: (unused)
reg_spimaster_cs = 0x10001; // sel=0, manual CS
spi_write(0x08); // Write 0x03 (read mode)
spi_write(0x05); // Write 0x00 (start address high byte)
value = spi_read(); // 0x93
if (value == 0xD)
reg_debug_1 = 0xBB; // get correct value
else {
reg_debug_2 = value;
reg_debug_1 = 0xEE; // get wrong value
}
reg_spimaster_cs = 0x0000; // release CS
reg_spimaster_cs = 0x10001; // sel=0, manual CS
}