mirror of https://github.com/efabless/caravel.git
Added a testbench that exercises the SRAM 2nd (read-only) port, as
it was configured for the caravel_pico SoC, with the housekeeping SPI able to access the upper 256-word section of the memory if the CSB bit in the housekeeping control register is cleared. This testbench tests both access through housekeeping and access directly from the SoC through the memory-mapped address.
This commit is contained in:
Tim Edwards
parent
e938b7dcf3
commit
7a45a096a5
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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PDK_PATH = $(PDK_ROOT)/sky130A
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VERILOG_PATH = ../../../..
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RTL_PATH = $(VERILOG_PATH)/rtl
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BEHAVIOURAL_MODELS = ../../
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RISCV_TYPE ?= rv32imc
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FIRMWARE_PATH = ../..
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GCC_PATH?=/ef/apps/bin
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GCC_PREFIX?=riscv32-unknown-elf
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SIM_DEFINES = -DFUNCTIONAL -DSIM
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SIM?=RTL
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.SUFFIXES:
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PATTERN = sram_ro
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# Path to management SoC wrapper repository
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MGMT_CORE_PATH ?= ~/gits/caravel_pico
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ifeq ($(SIM),RTL)
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MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog/rtl
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else
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MGMT_WRAPPER_PATH = $(MGMT_CORE_PATH)/verilog
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endif
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all: ${PATTERN:=.vcd}
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hex: ${PATTERN:=.hex}
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%.vvp: %_tb.v %.hex
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ifeq ($(SIM),RTL)
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iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
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-I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
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$< -o $@
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else
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iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
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-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
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$< -o $@
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endif
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%.vcd: %.vvp
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vvp $<
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%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
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${GCC_PATH}/${GCC_PREFIX}-gcc -march=$(RISCV_TYPE) -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
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%.hex: %.elf
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${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
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# to fix flash base address
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sed -i 's/@10000000/@00000000/g' $@
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%.bin: %.elf
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${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
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check-env:
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ifndef PDK_ROOT
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$(error PDK_ROOT is undefined, please export it before running make)
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endif
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ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
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$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
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endif
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ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
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$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
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endif
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# check for efabless style installation
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ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
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SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
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endif
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# ---- Clean ----
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clean:
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rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
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.PHONY: clean hex all
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@ -0,0 +1,137 @@
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/*
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* SPDX-FileCopyrightText: 2020 Efabless Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "../../defs.h"
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#define reg_hkspi_sram_ctrl (*(volatile uint32_t *)0x26100034)
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#define reg_hkspi_sram_addr (*(volatile uint32_t *)0x26100030)
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#define reg_hkspi_sram_data (*(volatile uint32_t *)0x2610002c)
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// --------------------------------------------------------
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/*
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* SRAM read-only Test
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* Tests the read-only port of the dual port SRAM,
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* which can be read back through the housekeeping
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* module or from the SoC.
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*/
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void main()
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{
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int i;
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/* Set data out to zero */
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reg_mprj_datal = 0;
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/* Set mprj_io[31:16] to outputs so that we can place values on */
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/* the output pins and check them in the testbench verilog. */
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reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
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/* Apply configuration */
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reg_mprj_xfer = 1;
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while (reg_mprj_xfer == 1);
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/* Flag start of test */
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reg_mprj_datal = 0x48000000;
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/* Write to SRAM (reg_rw_block0 = 0x01000000) */
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/* BUT housekeeping RO data is only 256 words at 0x01000400 */
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/* The lower half is accessible by the management SoC */
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(*(volatile uint32_t*)0x01000400) = 0x04030201;
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(*(volatile uint32_t*)0x01000404) = 0xaa55aa55;
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(*(volatile uint32_t*)0x01000408) = 0x55aa55aa;
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(*(volatile uint32_t*)0x0100040c) = 0xcc33cc33;
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(*(volatile uint32_t*)0x01000410) = 0xff00ff00;
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/* Read data from housekeeping back-door */
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reg_hkspi_sram_ctrl = 0; /* assert select */
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/* Note that addressing in this mode is word-wise; */
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/* address 0 in housekeeping = SRAM word address 0x100 */
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/* = SRAM byte address 0x400 = memory-mapped address */
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/* 0x01000400, while address 1 in housekeeping = SRAM */
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/* word address 0x101 = SRAM byte address 0x404 = */
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/* memory-mapped address 0x01000404, and so forth. */
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reg_hkspi_sram_addr = 0; /* first word address */
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/* Apply value to output */
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reg_mprj_datal = reg_hkspi_sram_data;
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reg_hkspi_sram_addr = 1; /* next word address */
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/* Apply value to output */
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reg_mprj_datal = reg_hkspi_sram_data;
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reg_hkspi_sram_addr = 2; /* next word address */
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/* Apply value to output */
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reg_mprj_datal = reg_hkspi_sram_data;
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reg_hkspi_sram_addr = 3; /* next word address */
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/* Apply value to output */
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reg_mprj_datal = reg_hkspi_sram_data;
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reg_hkspi_sram_addr = 4; /* next word address */
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/* Apply value to output */
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reg_mprj_datal = reg_hkspi_sram_data;
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/* Flag end of first test */
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reg_mprj_datal = 0x48010000;
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/* Now do the same thing using the management SoC access only, */
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/* which requires CSB set high */
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reg_hkspi_sram_ctrl = 1; /* de-assert select */
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(*(volatile uint32_t*)0x01000000) = 0xff00ff00;
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(*(volatile uint32_t*)0x01000004) = 0xcc33cc33;
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(*(volatile uint32_t*)0x01000008) = 0x55aa55aa;
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(*(volatile uint32_t*)0x0100000c) = 0xaa55aa55;
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(*(volatile uint32_t*)0x01000010) = 0x04030201;
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/* Read back from read-only port (note different address block) */
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reg_mprj_datal = (*(volatile uint32_t*)0x02000000);
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reg_mprj_datal = (*(volatile uint32_t*)0x02000004);
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reg_mprj_datal = (*(volatile uint32_t*)0x02000008);
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reg_mprj_datal = (*(volatile uint32_t*)0x0200000c);
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reg_mprj_datal = (*(volatile uint32_t*)0x02000010);
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/* Flag end of second test */
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reg_mprj_datal = 0x48020000;
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}
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@ -0,0 +1,189 @@
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`default_nettype none
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/*
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* SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
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*
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* StriVe - A full example SoC using PicoRV32 in SkyWater s8
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2018 Tim Edwards <tim@efabless.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* SPDX-License-Identifier: ISC
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*/
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`timescale 1 ns / 1 ps
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`include "__uprj_netlists.v"
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`include "caravel_netlists.v"
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`include "spiflash.v"
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module sram_ro_tb;
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reg clock;
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reg power1;
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reg power2;
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always #10 clock <= (clock === 1'b0);
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initial begin
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clock <= 0;
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end
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initial begin
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$dumpfile("sram_ro.vcd");
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$dumpvars(0, sram_ro_tb);
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// Repeat cycles of 1000 clock edges as needed to complete testbench
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repeat (25) begin
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repeat (1000) @(posedge clock);
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$display("+1000 cycles");
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end
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$display("%c[1;31m",27);
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`ifdef GL
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$display ("Monitor: Timeout, Test GPIO (GL) Failed");
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`else
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$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
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`endif
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$display("%c[0m",27);
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$finish;
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end
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wire [37:0] mprj_io; // Most of these are no-connects
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wire [15:0] checkbits;
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assign checkbits = mprj_io[31:16];
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assign mprj_io[3] = 1'b1; // Force CSB high.
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wire flash_csb;
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wire flash_clk;
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wire flash_io0;
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wire flash_io1;
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wire gpio;
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reg RSTB;
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// Monitor
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initial begin
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wait(checkbits == 16'h4800);
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`ifdef GL
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$display("Monitor: Test R/O SRAM (GL) Started");
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`else
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$display("Monitor: Test R/O SRAM (RTL) Started");
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`endif
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wait(checkbits == 16'h0403);
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wait(checkbits == 16'haa55);
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wait(checkbits == 16'h55aa);
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wait(checkbits == 16'hcc33);
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wait(checkbits == 16'hff00);
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wait(checkbits == 16'h4801);
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`ifdef GL
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$display("Monitor: Test R/O SRAM (GL) Midpoint");
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`else
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$display("Monitor: Test R/O SRAM (RTL) Midpoint");
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`endif
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wait(checkbits == 16'hff00);
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wait(checkbits == 16'hcc33);
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wait(checkbits == 16'h55aa);
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wait(checkbits == 16'haa55);
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wait(checkbits == 16'h0403);
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wait(checkbits == 16'h4802);
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`ifdef GL
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$display("Monitor: Test R/O SRAM (GL) Passed");
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`else
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$display("Monitor: Test R/O SRAM (RTL) Passed");
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`endif
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$finish;
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end
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initial begin
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RSTB <= 1'b0;
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#1000;
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RSTB <= 1'b1; // Release reset
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#2000;
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end
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initial begin // Power-up
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power1 <= 1'b0;
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power2 <= 1'b0;
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#200;
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power1 <= 1'b1;
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#200;
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power2 <= 1'b1;
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end
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always @(checkbits) begin
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#1 $display("GPIO state = %b", checkbits);
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end
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wire VDD3V3;
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wire VDD1V8;
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wire VSS;
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assign VDD3V3 = power1;
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assign VDD1V8 = power2;
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assign VSS = 1'b0;
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// These are the mappings of mprj_io GPIO pads that are set to
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// specific functions on startup:
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//
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// JTAG = mgmt_gpio_io[0] (inout)
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// SDO = mgmt_gpio_io[1] (output)
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// SDI = mgmt_gpio_io[2] (input)
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// CSB = mgmt_gpio_io[3] (input)
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// SCK = mgmt_gpio_io[4] (input)
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// ser_rx = mgmt_gpio_io[5] (input)
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// ser_tx = mgmt_gpio_io[6] (output)
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// irq = mgmt_gpio_io[7] (input)
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caravel uut (
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.vddio (VDD3V3),
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.vssio (VSS),
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.vdda (VDD3V3),
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.vssa (VSS),
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.vccd (VDD1V8),
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.vssd (VSS),
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.vdda1 (VDD3V3),
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.vdda2 (VDD3V3),
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.vssa1 (VSS),
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.vssa2 (VSS),
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.vccd1 (VDD1V8),
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.vccd2 (VDD1V8),
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.vssd1 (VSS),
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.vssd2 (VSS),
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.clock (clock),
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.gpio (gpio),
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.mprj_io (mprj_io),
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.flash_csb(flash_csb),
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.flash_clk(flash_clk),
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.flash_io0(flash_io0),
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.flash_io1(flash_io1),
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.resetb (RSTB)
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);
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spiflash #(
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.FILENAME("sram_ro.hex")
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) spiflash (
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.csb(flash_csb),
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.clk(flash_clk),
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.io0(flash_io0),
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.io1(flash_io1),
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.io2(), // not used
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.io3() // not used
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);
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endmodule
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`default_nettype wire
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