fix bug assert csb before reset for the GL sim to work

verilog/dv/cocotb/caravel.py

@@ -51,14 +51,16 @@ class Caravel_env:
     """start carvel by insert power then reset"""
     async def start_up(self):
         await self.power_up()
+        await self.disable_csb()
         await self.reset()
         await self.disable_bins()
-        await self.disable_csb()
         common.fill_macros(self.dut.macros) # get macros value
 
     async def disable_bins(self):
         for i in range(38):
-         common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0) 
+            if i == 3:
+                continue
+            common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0) 
 
     """setup the vdd and vcc power bins"""
     async def power_up(self):

verilog/dv/cocotb/caravel_tests.py

@@ -32,7 +32,7 @@ from tests.mem.mem_stress import *
 from tests.irq.IRQ_external import *
 from tests.irq.IRQ_timer import *
 from tests.irq.IRQ_uart import *
-from tests.gpio.gpio_all_o import *
+from tests.gpio.gpio import *
 from tests.mgmt_gpio.mgmt_gpio import *
 from tests.timer.timer import *
 from tests.uart.uart import *