From 199d5c0f5c4a9e86715bf4848430a91eee7b6ba3 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 1 Oct 2022 12:36:02 -0700 Subject: [PATCH] fix bug assert csb before reset for the GL sim to work --- verilog/dv/cocotb/caravel.py | 6 ++++-- verilog/dv/cocotb/caravel_tests.py | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/verilog/dv/cocotb/caravel.py b/verilog/dv/cocotb/caravel.py index e1c85149..8c4f36a4 100644 --- a/verilog/dv/cocotb/caravel.py +++ b/verilog/dv/cocotb/caravel.py @@ -51,14 +51,16 @@ class Caravel_env: """start carvel by insert power then reset""" async def start_up(self): await self.power_up() + await self.disable_csb() await self.reset() await self.disable_bins() - await self.disable_csb() common.fill_macros(self.dut.macros) # get macros value async def disable_bins(self): for i in range(38): - common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0) + if i == 3: + continue + common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0) """setup the vdd and vcc power bins""" async def power_up(self): diff --git a/verilog/dv/cocotb/caravel_tests.py b/verilog/dv/cocotb/caravel_tests.py index 2d4cd80d..8579ed11 100644 --- a/verilog/dv/cocotb/caravel_tests.py +++ b/verilog/dv/cocotb/caravel_tests.py @@ -32,7 +32,7 @@ from tests.mem.mem_stress import * from tests.irq.IRQ_external import * from tests.irq.IRQ_timer import * from tests.irq.IRQ_uart import * -from tests.gpio.gpio_all_o import * +from tests.gpio.gpio import * from tests.mgmt_gpio.mgmt_gpio import * from tests.timer.timer import * from tests.uart.uart import *