mirror of https://github.com/efabless/caravel.git
add test uart_rx
This commit is contained in:
M0stafaRady
parent
407b0be306
commit
18b4f36525
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@ -1,60 +1,60 @@
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@00000000
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03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02
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03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30
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17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6
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73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00
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13 06 46 2E 63 0C B5 00 83 26 06 00 23 20 D5 00
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13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00
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93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00
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6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30
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EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00
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13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01
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67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01
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13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00
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13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE
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83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01
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13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00
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23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC
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B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00
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B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00
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13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00
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03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF
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23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00
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13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00
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13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01
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67 80 00 00 13 01 01 FD 23 26 81 02 13 04 01 03
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B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00
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B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30
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93 87 C7 FF 23 A0 07 00 B7 57 00 F0 93 87 87 00
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23 A0 07 00 B7 57 00 F0 23 A0 07 00 B7 57 00 F0
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93 87 C7 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0
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93 87 07 01 83 A7 07 00 23 26 F4 FE 23 24 04 FE
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93 07 00 19 23 20 F4 FE 23 22 04 FE 6F 00 C0 0C
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B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00
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B7 57 00 F0 93 87 07 01 83 A7 07 00 23 2E F4 FC
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03 27 C4 FD 83 27 C4 FE 63 F8 E7 06 83 27 84 FE
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93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 10 00
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63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 01
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23 A0 E7 00 6F 00 40 04 03 27 84 FE 93 07 20 00
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63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 02
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23 A0 E7 00 6F 00 40 02 03 27 84 FE 93 07 30 00
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63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 03
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23 A0 E7 00 6F 00 00 04 03 27 C4 FD 83 27 C4 FE
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63 7A F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 04
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23 A0 E7 00 83 27 C4 FD 23 26 F4 FE 83 27 44 FE
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93 87 17 00 23 22 F4 FE 03 27 44 FE 83 27 04 FE
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E3 48 F7 F2 83 27 84 FE 63 9A 07 00 B7 07 10 30
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93 87 87 FF 13 07 E0 0E 23 A0 E7 00 B7 07 10 30
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93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00
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03 24 C1 02 13 01 01 03 67 80 00 00
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6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00
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13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
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23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE
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23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE
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23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD
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23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD
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13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03
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03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02
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03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01
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03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00
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03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30
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17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6
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73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00
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13 06 46 2E 63 0C B5 00 83 26 06 00 23 20 D5 00
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13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00
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93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00
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6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30
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EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00
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13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01
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67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01
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13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00
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13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE
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83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01
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13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00
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23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC
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B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00
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B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00
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13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00
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03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF
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23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00
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13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00
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13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01
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67 80 00 00 13 01 01 FD 23 26 81 02 13 04 01 03
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B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00
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B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30
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93 87 C7 FF 23 A0 07 00 B7 57 00 F0 93 87 87 00
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23 A0 07 00 B7 57 00 F0 23 A0 07 00 B7 57 00 F0
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93 87 47 00 13 07 00 30 23 A0 E7 00 B7 57 00 F0
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93 87 87 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0
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93 87 C7 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0
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93 87 07 01 83 A7 07 00 23 26 F4 FE 23 24 04 FE
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93 07 00 19 23 20 F4 FE 23 22 04 FE 6F 00 C0 0C
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B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00
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B7 57 00 F0 93 87 07 01 83 A7 07 00 23 2E F4 FC
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03 27 C4 FD 83 27 C4 FE 63 F8 E7 06 83 27 84 FE
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93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 10 00
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63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 01
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23 A0 E7 00 6F 00 40 04 03 27 84 FE 93 07 20 00
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63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 02
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23 A0 E7 00 6F 00 40 02 03 27 84 FE 93 07 30 00
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63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 03
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23 A0 E7 00 6F 00 00 04 03 27 C4 FD 83 27 C4 FE
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63 7A F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 04
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23 A0 E7 00 83 27 C4 FD 23 26 F4 FE 83 27 44 FE
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93 87 17 00 23 22 F4 FE 03 27 44 FE 83 27 04 FE
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E3 48 F7 F2 83 27 84 FE 63 9A 07 00 B7 07 10 30
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93 87 87 FF 13 07 E0 0E 23 A0 E7 00 B7 07 10 30
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93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00
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03 24 C1 02 13 01 01 03 67 80 00 00
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@ -0,0 +1,77 @@
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@00000000
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6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00
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13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
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23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE
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23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE
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23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD
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23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD
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13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03
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03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02
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03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01
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03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00
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03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30
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17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6
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73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00
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13 06 C6 3C 63 0C B5 00 83 26 06 00 23 20 D5 00
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13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00
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93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00
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6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30
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EF 00 40 28 6F 00 00 00 13 01 01 FF 23 26 81 00
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13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01
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67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01
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13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00
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13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE
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83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01
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13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00
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23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC
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B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00
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B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00
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13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00
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03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF
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23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00
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13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00
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13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01
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67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02
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23 26 A4 FE 83 27 C4 FE 83 A7 07 00 13 85 07 00
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03 24 C1 01 13 01 01 02 67 80 00 00 13 01 01 FF
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23 26 11 00 23 24 81 00 13 04 01 01 B7 67 00 F0
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13 85 87 80 EF F0 1F FC 93 07 05 00 13 85 07 00
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83 20 C1 00 03 24 81 00 13 01 01 01 67 80 00 00
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13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02
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93 07 05 00 A3 07 F4 FE 03 47 F4 FE 93 07 A0 00
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63 16 F7 00 13 05 D0 00 EF F0 9F FD 13 00 00 00
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B7 67 00 F0 93 87 47 80 03 A7 07 00 93 07 10 00
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E3 08 F7 FE B7 67 00 F0 93 87 07 80 03 47 F4 FE
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23 A0 E7 00 13 00 00 00 83 20 C1 01 03 24 81 01
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13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 11 00
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23 2C 81 00 13 04 01 02 23 26 A4 FE 6F 00 C0 01
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83 27 C4 FE 13 87 17 00 23 26 E4 FE 83 C7 07 00
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13 85 07 00 EF F0 DF F6 83 27 C4 FE 83 C7 07 00
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E3 90 07 FE 13 00 00 00 13 00 00 00 83 20 C1 01
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03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE
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23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE
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13 00 00 00 EF F0 9F EF 13 07 05 00 93 07 10 00
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E3 0A F7 FE B7 67 00 F0 93 87 07 80 83 A7 07 00
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03 27 C4 FE 03 47 07 00 63 9C E7 00 B7 07 10 30
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93 87 87 FF 13 07 B0 01 23 A0 E7 00 6F 00 40 01
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B7 07 10 30 93 87 87 FF 13 07 E0 01 23 A0 E7 00
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13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02
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67 80 00 00 13 01 01 FF 23 26 11 00 23 24 81 00
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13 04 01 01 B7 47 00 F0 93 87 07 80 13 07 10 00
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23 A0 E7 00 B7 07 10 30 93 87 87 FF 23 A0 07 00
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B7 07 10 30 93 87 C7 FF 23 A0 07 00 B7 07 00 26
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93 87 C7 03 37 27 00 00 13 07 97 80 23 A0 E7 00
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B7 07 00 26 93 87 87 03 13 07 30 40 23 A0 E7 00
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B7 07 00 26 13 07 10 00 23 A0 E7 00 13 00 00 00
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B7 07 00 26 03 A7 07 00 93 07 10 00 E3 0A F7 FE
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B7 67 00 F0 13 07 10 00 23 A0 E7 00 B7 07 10 30
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93 87 87 FF 13 07 A0 0A 23 A0 E7 00 B7 07 00 10
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13 85 87 48 EF F0 9F EE B7 07 10 30 93 87 87 FF
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13 07 B0 0B 23 A0 E7 00 B7 07 00 10 13 85 C7 48
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EF F0 DF EC B7 07 10 30 93 87 87 FF 13 07 C0 0C
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23 A0 E7 00 B7 07 00 10 13 85 07 49 EF F0 1F EB
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13 00 00 00 83 20 C1 00 03 24 81 00 13 01 01 01
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67 80 00 00
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@00000484
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00 00 00 00 42 00 00 00 4D 00 00 00 41 00 00 00
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00 00 00 00
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@ -156,5 +156,11 @@
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"GL":["nightly","weekly","tape_out"],
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"GL_SDF":["weekly","tape_out"],
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"description":"test uart transmit"}
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,"uart_rx" :{"level":0,
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"SW":true,
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"RTL":["setup","nightly","weekly","tape_out"],
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"GL":["nightly","weekly","tape_out"],
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"GL_SDF":["weekly","tape_out"],
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"description":"test uart reception"}
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}
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}
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@ -13,7 +13,8 @@ from caravel import GPIO_MODE
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baud_rate = 9600
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number_of_bits = 8
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bit_rate_ns = round((10**9)/(baud_rate*number_of_bits) )
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clk = 12.5
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bit_time = 10**5 * clk / (96)
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reg = Regs()
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@ -25,19 +26,19 @@ async def uart_tx(dut):
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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cocotb.log.info(f"[TEST] Start uart test")
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expected_data = "Monitor: Test UART (RTL) passed"
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expected_msg = "Monitor: Test UART (RTL) passed"
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await wait_reg1(cpu,caravelEnv,0XAA)
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cocotb.log.info (f"[TEST] start sending on uart")
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cocotb.log.info (f"[TEST] start receiving from uart")
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counter =0
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data_out =''
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while True:
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if counter %8 == 0:
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if counter != 0:
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data_out = data_out+chr(int(char,2))
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cocotb.log.info (f"[TEST] msg is:'{data_out}' expected '{expected_data}'")
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if data_out == expected_data:
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cocotb.log.info (f"[TEST] msg is:'{data_out}' expected '{expected_msg}'")
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if data_out == expected_msg:
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cocotb.log.info (f"[TEST] Pass recieve the full expected msg '{data_out}'")
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break
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await start_of_tx(caravelEnv)
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@ -54,3 +55,68 @@ async def start_of_tx(caravelEnv):
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break
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await Timer(bit_rate_ns, units='ns')
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await Timer(bit_rate_ns, units='ns')
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@cocotb.test()
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@repot_test
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async def uart_rx(dut):
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caravelEnv = await test_configure(dut,timeout_cycles=95844)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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cocotb.log.info(f"[TEST] Start uart test")
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caravelEnv.drive_gpio_in((5,5),1)
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# send first char
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await wait_reg1(cpu,caravelEnv,0XAA)
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await uart_send_char(caravelEnv,"B")
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await uart_check_char_recieved(caravelEnv,cpu)
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# send second char
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await wait_reg1(cpu,caravelEnv,0XBB)
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await uart_send_char(caravelEnv,"M")
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await uart_check_char_recieved(caravelEnv,cpu)
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# send third char
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cocotb.log.info(f"[TEST] here")
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await wait_reg1(cpu,caravelEnv,0XCC)
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cocotb.log.info(f"[TEST] here")
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await uart_send_char(caravelEnv,"A")
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await uart_check_char_recieved(caravelEnv,cpu)
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async def uart_send_char(caravelEnv,char):
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char_bits = [int(x) for x in '{:08b}'.format(ord(char))]
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cocotb.log.info (f"[TEST] start sending on uart {char}")
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#send start bit
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caravelEnv.drive_gpio_in((5,5),0)
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await Timer(bit_rate_ns, units='ns')
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#send bits
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for i in range(8):
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caravelEnv.drive_gpio_in((5,5),char_bits[i])
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await Timer(bit_rate_ns, units='ns')
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# stop of frame
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caravelEnv.drive_gpio_in((5,5),1)
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await Timer(bit_rate_ns, units='ns')
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await Timer(bit_rate_ns, units='ns')
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# insert 4 bit delay just for debugging
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await Timer(bit_rate_ns, units='ns')
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await Timer(bit_rate_ns, units='ns')
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await Timer(bit_rate_ns, units='ns')
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await Timer(bit_rate_ns, units='ns')
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async def uart_check_char_recieved(caravelEnv,cpu):
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# check cpu recieved the correct character
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while True:
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reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr
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reg1 = cpu.read_debug_reg1()
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cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}")
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if reg1 == 0x1B:
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cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character {chr(int(reg_uart_data,2))}")
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return
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if reg1 == 0x1E:
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cocotb.log.error(f"[TEST] Failed Pass cpu has recieved the wrong character {chr(int(reg_uart_data,2))}")
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return
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await ClockCycles(caravelEnv.clk,1)
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@ -0,0 +1,63 @@
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/*
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* SPDX-FileCopyrightText: 2020 Efabless Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <defs.h>
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#include <stub.c>
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// --------------------------------------------------------
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void wait_for_char(char *c){
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while (uart_rxempty_read() == 1);
|
||||
if (reg_uart_data == *c){
|
||||
reg_debug_1 = 0x1B; // recieved the correct character
|
||||
}else{
|
||||
reg_debug_1 = 0x1E; // timeout didn't recieve the character
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void main(){
|
||||
int j;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
|
||||
// Set clock to 64 kbaud and enable the UART. It is important to do this
|
||||
// before applying the configuration, or else the Tx line initializes as
|
||||
// zero, which indicates the start of a byte to the receiver.
|
||||
|
||||
|
||||
// Now, apply the configuration
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
|
||||
reg_uart_enable = 1;
|
||||
|
||||
reg_debug_1 = 0xAA; // start sending B
|
||||
wait_for_char("B");
|
||||
|
||||
reg_debug_1 = 0xBB; // start sending M
|
||||
wait_for_char("M");
|
||||
|
||||
reg_debug_1 = 0xCC; // start sending A
|
||||
wait_for_char("A");
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue