From 18b4f365255cc9b1af8fc3f68395b96464b3466f Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 1 Oct 2022 02:23:47 -0700 Subject: [PATCH] add test uart_rx --- .../dv/cocotb/hex_files/timer0_periodic.hex | 118 +++++++++--------- verilog/dv/cocotb/hex_files/uart_rx.hex | 77 ++++++++++++ verilog/dv/cocotb/tests.json | 6 + verilog/dv/cocotb/tests/uart/uart.py | 76 ++++++++++- verilog/dv/cocotb/tests/uart/uart_rx.c | 63 ++++++++++ 5 files changed, 276 insertions(+), 64 deletions(-) create mode 100755 verilog/dv/cocotb/hex_files/uart_rx.hex create mode 100644 verilog/dv/cocotb/tests/uart/uart_rx.c diff --git a/verilog/dv/cocotb/hex_files/timer0_periodic.hex b/verilog/dv/cocotb/hex_files/timer0_periodic.hex index 45cfd920..d839cf32 100755 --- a/verilog/dv/cocotb/hex_files/timer0_periodic.hex +++ b/verilog/dv/cocotb/hex_files/timer0_periodic.hex @@ -1,60 +1,60 @@ @00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 2E 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FD 23 26 81 02 13 04 01 03 -B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 -B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 -93 87 C7 FF 23 A0 07 00 B7 57 00 F0 93 87 87 00 -23 A0 07 00 B7 57 00 F0 23 A0 07 00 B7 57 00 F0 -93 87 47 00 13 07 00 30 23 A0 E7 00 B7 57 00 F0 -93 87 87 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0 -93 87 C7 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0 -93 87 07 01 83 A7 07 00 23 26 F4 FE 23 24 04 FE -93 07 00 19 23 20 F4 FE 23 22 04 FE 6F 00 C0 0C -B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00 -B7 57 00 F0 93 87 07 01 83 A7 07 00 23 2E F4 FC -03 27 C4 FD 83 27 C4 FE 63 F8 E7 06 83 27 84 FE -93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 10 00 -63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 01 -23 A0 E7 00 6F 00 40 04 03 27 84 FE 93 07 20 00 -63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 02 -23 A0 E7 00 6F 00 40 02 03 27 84 FE 93 07 30 00 -63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 03 -23 A0 E7 00 6F 00 00 04 03 27 C4 FD 83 27 C4 FE -63 7A F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 04 -23 A0 E7 00 83 27 C4 FD 23 26 F4 FE 83 27 44 FE -93 87 17 00 23 22 F4 FE 03 27 44 FE 83 27 04 FE -E3 48 F7 F2 83 27 84 FE 63 9A 07 00 B7 07 10 30 -93 87 87 FF 13 07 E0 0E 23 A0 E7 00 B7 07 10 30 -93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00 -03 24 C1 02 13 01 01 03 67 80 00 00 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 2E 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FD 23 26 81 02 13 04 01 03 +B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 +B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 +93 87 C7 FF 23 A0 07 00 B7 57 00 F0 93 87 87 00 +23 A0 07 00 B7 57 00 F0 23 A0 07 00 B7 57 00 F0 +93 87 47 00 13 07 00 30 23 A0 E7 00 B7 57 00 F0 +93 87 87 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0 +93 87 C7 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0 +93 87 07 01 83 A7 07 00 23 26 F4 FE 23 24 04 FE +93 07 00 19 23 20 F4 FE 23 22 04 FE 6F 00 C0 0C +B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00 +B7 57 00 F0 93 87 07 01 83 A7 07 00 23 2E F4 FC +03 27 C4 FD 83 27 C4 FE 63 F8 E7 06 83 27 84 FE +93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 10 00 +63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 01 +23 A0 E7 00 6F 00 40 04 03 27 84 FE 93 07 20 00 +63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 02 +23 A0 E7 00 6F 00 40 02 03 27 84 FE 93 07 30 00 +63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 03 +23 A0 E7 00 6F 00 00 04 03 27 C4 FD 83 27 C4 FE +63 7A F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 04 +23 A0 E7 00 83 27 C4 FD 23 26 F4 FE 83 27 44 FE +93 87 17 00 23 22 F4 FE 03 27 44 FE 83 27 04 FE +E3 48 F7 F2 83 27 84 FE 63 9A 07 00 B7 07 10 30 +93 87 87 FF 13 07 E0 0E 23 A0 E7 00 B7 07 10 30 +93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00 +03 24 C1 02 13 01 01 03 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/uart_rx.hex b/verilog/dv/cocotb/hex_files/uart_rx.hex new file mode 100755 index 00000000..db6552a6 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/uart_rx.hex @@ -0,0 +1,77 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 C6 3C 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 40 28 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 +23 26 A4 FE 83 27 C4 FE 83 A7 07 00 13 85 07 00 +03 24 C1 01 13 01 01 02 67 80 00 00 13 01 01 FF +23 26 11 00 23 24 81 00 13 04 01 01 B7 67 00 F0 +13 85 87 80 EF F0 1F FC 93 07 05 00 13 85 07 00 +83 20 C1 00 03 24 81 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02 +93 07 05 00 A3 07 F4 FE 03 47 F4 FE 93 07 A0 00 +63 16 F7 00 13 05 D0 00 EF F0 9F FD 13 00 00 00 +B7 67 00 F0 93 87 47 80 03 A7 07 00 93 07 10 00 +E3 08 F7 FE B7 67 00 F0 93 87 07 80 03 47 F4 FE +23 A0 E7 00 13 00 00 00 83 20 C1 01 03 24 81 01 +13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 11 00 +23 2C 81 00 13 04 01 02 23 26 A4 FE 6F 00 C0 01 +83 27 C4 FE 13 87 17 00 23 26 E4 FE 83 C7 07 00 +13 85 07 00 EF F0 DF F6 83 27 C4 FE 83 C7 07 00 +E3 90 07 FE 13 00 00 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +13 00 00 00 EF F0 9F EF 13 07 05 00 93 07 10 00 +E3 0A F7 FE B7 67 00 F0 93 87 07 80 83 A7 07 00 +03 27 C4 FE 03 47 07 00 63 9C E7 00 B7 07 10 30 +93 87 87 FF 13 07 B0 01 23 A0 E7 00 6F 00 40 01 +B7 07 10 30 93 87 87 FF 13 07 E0 01 23 A0 E7 00 +13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02 +67 80 00 00 13 01 01 FF 23 26 11 00 23 24 81 00 +13 04 01 01 B7 47 00 F0 93 87 07 80 13 07 10 00 +23 A0 E7 00 B7 07 10 30 93 87 87 FF 23 A0 07 00 +B7 07 10 30 93 87 C7 FF 23 A0 07 00 B7 07 00 26 +93 87 C7 03 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 87 03 13 07 30 40 23 A0 E7 00 +B7 07 00 26 13 07 10 00 23 A0 E7 00 13 00 00 00 +B7 07 00 26 03 A7 07 00 93 07 10 00 E3 0A F7 FE +B7 67 00 F0 13 07 10 00 23 A0 E7 00 B7 07 10 30 +93 87 87 FF 13 07 A0 0A 23 A0 E7 00 B7 07 00 10 +13 85 87 48 EF F0 9F EE B7 07 10 30 93 87 87 FF +13 07 B0 0B 23 A0 E7 00 B7 07 00 10 13 85 C7 48 +EF F0 DF EC B7 07 10 30 93 87 87 FF 13 07 C0 0C +23 A0 E7 00 B7 07 00 10 13 85 07 49 EF F0 1F EB +13 00 00 00 83 20 C1 00 03 24 81 00 13 01 01 01 +67 80 00 00 +@00000484 +00 00 00 00 42 00 00 00 4D 00 00 00 41 00 00 00 +00 00 00 00 diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index f83fac8e..5d04ea74 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -156,5 +156,11 @@ "GL":["nightly","weekly","tape_out"], "GL_SDF":["weekly","tape_out"], "description":"test uart transmit"} + ,"uart_rx" :{"level":0, + "SW":true, + "RTL":["setup","nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"test uart reception"} } } \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index 729c6be9..e46854d0 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -13,7 +13,8 @@ from caravel import GPIO_MODE baud_rate = 9600 number_of_bits = 8 bit_rate_ns = round((10**9)/(baud_rate*number_of_bits) ) - +clk = 12.5 +bit_time = 10**5 * clk / (96) reg = Regs() @@ -25,19 +26,19 @@ async def uart_tx(dut): cpu.cpu_force_reset() cpu.cpu_release_reset() cocotb.log.info(f"[TEST] Start uart test") - expected_data = "Monitor: Test UART (RTL) passed" + expected_msg = "Monitor: Test UART (RTL) passed" await wait_reg1(cpu,caravelEnv,0XAA) - cocotb.log.info (f"[TEST] start sending on uart") + cocotb.log.info (f"[TEST] start receiving from uart") counter =0 data_out ='' while True: if counter %8 == 0: if counter != 0: data_out = data_out+chr(int(char,2)) - cocotb.log.info (f"[TEST] msg is:'{data_out}' expected '{expected_data}'") - if data_out == expected_data: + cocotb.log.info (f"[TEST] msg is:'{data_out}' expected '{expected_msg}'") + if data_out == expected_msg: cocotb.log.info (f"[TEST] Pass recieve the full expected msg '{data_out}'") break await start_of_tx(caravelEnv) @@ -54,3 +55,68 @@ async def start_of_tx(caravelEnv): break await Timer(bit_rate_ns, units='ns') await Timer(bit_rate_ns, units='ns') + + +@cocotb.test() +@repot_test +async def uart_rx(dut): + caravelEnv = await test_configure(dut,timeout_cycles=95844) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info(f"[TEST] Start uart test") + caravelEnv.drive_gpio_in((5,5),1) + + # send first char + await wait_reg1(cpu,caravelEnv,0XAA) + await uart_send_char(caravelEnv,"B") + await uart_check_char_recieved(caravelEnv,cpu) + # send second char + await wait_reg1(cpu,caravelEnv,0XBB) + await uart_send_char(caravelEnv,"M") + await uart_check_char_recieved(caravelEnv,cpu) + # send third char + cocotb.log.info(f"[TEST] here") + await wait_reg1(cpu,caravelEnv,0XCC) + cocotb.log.info(f"[TEST] here") + await uart_send_char(caravelEnv,"A") + await uart_check_char_recieved(caravelEnv,cpu) + + + +async def uart_send_char(caravelEnv,char): + char_bits = [int(x) for x in '{:08b}'.format(ord(char))] + cocotb.log.info (f"[TEST] start sending on uart {char}") + #send start bit + caravelEnv.drive_gpio_in((5,5),0) + await Timer(bit_rate_ns, units='ns') + #send bits + for i in range(8): + caravelEnv.drive_gpio_in((5,5),char_bits[i]) + await Timer(bit_rate_ns, units='ns') + + # stop of frame + caravelEnv.drive_gpio_in((5,5),1) + await Timer(bit_rate_ns, units='ns') + await Timer(bit_rate_ns, units='ns') + # insert 4 bit delay just for debugging + await Timer(bit_rate_ns, units='ns') + await Timer(bit_rate_ns, units='ns') + await Timer(bit_rate_ns, units='ns') + await Timer(bit_rate_ns, units='ns') + + +async def uart_check_char_recieved(caravelEnv,cpu): + # check cpu recieved the correct character + while True: + reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr + reg1 = cpu.read_debug_reg1() + cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}") + if reg1 == 0x1B: + cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character {chr(int(reg_uart_data,2))}") + return + if reg1 == 0x1E: + cocotb.log.error(f"[TEST] Failed Pass cpu has recieved the wrong character {chr(int(reg_uart_data,2))}") + return + + await ClockCycles(caravelEnv.clk,1) \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/uart/uart_rx.c b/verilog/dv/cocotb/tests/uart/uart_rx.c new file mode 100644 index 00000000..16779691 --- /dev/null +++ b/verilog/dv/cocotb/tests/uart/uart_rx.c @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +// -------------------------------------------------------- + +void wait_for_char(char *c){ + + while (uart_rxempty_read() == 1); + if (reg_uart_data == *c){ + reg_debug_1 = 0x1B; // recieved the correct character + }else{ + reg_debug_1 = 0x1E; // timeout didn't recieve the character + } + +} + +void main(){ + int j; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + + // Set clock to 64 kbaud and enable the UART. It is important to do this + // before applying the configuration, or else the Tx line initializes as + // zero, which indicates the start of a byte to the receiver. + + + // Now, apply the configuration + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + reg_uart_enable = 1; + + reg_debug_1 = 0xAA; // start sending B + wait_for_char("B"); + + reg_debug_1 = 0xBB; // start sending M + wait_for_char("M"); + + reg_debug_1 = 0xCC; // start sending A + wait_for_char("A"); + +}